1 /* $NetBSD: nouveau_nvkm_engine_gr_ctxtu102.c,v 1.2 2021/12/18 23:45:36 riastradh Exp $ */
2
3 /*
4 * Copyright 2019 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24 #include <sys/cdefs.h>
25 __KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_engine_gr_ctxtu102.c,v 1.2 2021/12/18 23:45:36 riastradh Exp $");
26
27 #include "ctxgf100.h"
28
29 static void
tu102_grctx_generate_r419c0c(struct gf100_gr * gr)30 tu102_grctx_generate_r419c0c(struct gf100_gr *gr)
31 {
32 struct nvkm_device *device = gr->base.engine.subdev.device;
33 nvkm_mask(device, 0x419c0c, 0x80000000, 0x80000000);
34 nvkm_mask(device, 0x40584c, 0x00000008, 0x00000000);
35 nvkm_mask(device, 0x400080, 0x00000000, 0x00000000);
36 }
37
38 static void
tu102_grctx_generate_sm_id(struct gf100_gr * gr,int gpc,int tpc,int sm)39 tu102_grctx_generate_sm_id(struct gf100_gr *gr, int gpc, int tpc, int sm)
40 {
41 struct nvkm_device *device = gr->base.engine.subdev.device;
42 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x608), sm);
43 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x088), sm);
44 }
45
46 static const struct gf100_gr_init
47 tu102_grctx_init_unknown_bundle_init_0[] = {
48 { 0x00001000, 1, 0x00000001, 0x00000004 },
49 { 0x00002020, 64, 0x00000001, 0x00000000 },
50 { 0x0001e100, 1, 0x00000001, 0x00000001 },
51 {}
52 };
53
54 static const struct gf100_gr_pack
55 tu102_grctx_pack_sw_veid_bundle_init[] = {
56 { gv100_grctx_init_sw_veid_bundle_init_0 },
57 { tu102_grctx_init_unknown_bundle_init_0 },
58 {}
59 };
60
61 static void
tu102_grctx_generate_attrib(struct gf100_grctx * info)62 tu102_grctx_generate_attrib(struct gf100_grctx *info)
63 {
64 const u64 size = 0x80000; /*XXX: educated guess */
65 const int s = 8;
66 const int b = mmio_vram(info, size, (1 << s), true);
67
68 gv100_grctx_generate_attrib(info);
69
70 mmio_refn(info, 0x408070, 0x00000000, s, b);
71 mmio_wr32(info, 0x408074, size >> s); /*XXX: guess */
72 mmio_refn(info, 0x419034, 0x00000000, s, b);
73 mmio_wr32(info, 0x408078, 0x00000000);
74 }
75
76 const struct gf100_grctx_func
77 tu102_grctx = {
78 .unkn88c = gv100_grctx_unkn88c,
79 .main = gf100_grctx_generate_main,
80 .unkn = gv100_grctx_generate_unkn,
81 .sw_veid_bundle_init = tu102_grctx_pack_sw_veid_bundle_init,
82 .bundle = gm107_grctx_generate_bundle,
83 .bundle_size = 0x3000,
84 .bundle_min_gpm_fifo_depth = 0x180,
85 .bundle_token_limit = 0xa80,
86 .pagepool = gp100_grctx_generate_pagepool,
87 .pagepool_size = 0x20000,
88 .attrib = tu102_grctx_generate_attrib,
89 .attrib_nr_max = 0x800,
90 .attrib_nr = 0x700,
91 .alpha_nr_max = 0xc00,
92 .alpha_nr = 0x800,
93 .gfxp_nr = 0xfa8,
94 .sm_id = tu102_grctx_generate_sm_id,
95 .skip_pd_num_tpc_per_gpc = true,
96 .rop_mapping = gv100_grctx_generate_rop_mapping,
97 .r406500 = gm200_grctx_generate_r406500,
98 .r400088 = gv100_grctx_generate_r400088,
99 .r419c0c = tu102_grctx_generate_r419c0c,
100 };
101