1 /* $NetBSD: tegra_drm.h,v 1.11 2021/12/19 12:44:50 riastradh Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef _ARM_TEGRA_DRM_H 30 #define _ARM_TEGRA_DRM_H 31 32 #include <sys/workqueue.h> 33 34 #include <drm/drm_encoder.h> 35 #include <drm/drm_fb_helper.h> 36 #include <drm/drm_gem_cma_helper.h> 37 38 #define DRIVER_AUTHOR "Jared McNeill" 39 40 #define DRIVER_NAME "tegra" 41 #define DRIVER_DESC "NVIDIA Tegra K1" 42 #define DRIVER_DATE "20151108" 43 44 #define DRIVER_MAJOR 0 45 #define DRIVER_MINOR 1 46 #define DRIVER_PATCHLEVEL 0 47 48 struct tegra_framebuffer; 49 50 struct tegra_drm_softc { 51 device_t sc_dev; 52 struct drm_device *sc_ddev; 53 54 bus_space_tag_t sc_bst; 55 bus_dma_tag_t sc_dmat; 56 57 int sc_phandle; 58 59 struct lwp *sc_task_thread; 60 SIMPLEQ_HEAD(, tegra_drm_task) sc_tasks; 61 struct workqueue *sc_task_wq; 62 63 bool sc_dev_registered; 64 65 struct clk *sc_clk_host1x; 66 struct fdtbus_reset *sc_rst_host1x; 67 68 struct clk *sc_clk_dc[2]; 69 struct clk *sc_clk_dc_parent[2]; 70 struct fdtbus_reset *sc_rst_dc[2]; 71 72 struct clk *sc_clk_hdmi; 73 struct clk *sc_clk_hdmi_parent; 74 struct fdtbus_reset *sc_rst_hdmi; 75 76 i2c_tag_t sc_ddc; 77 struct fdtbus_gpio_pin *sc_pin_hpd; 78 79 bool sc_force_dvi; 80 81 uint32_t sc_vbl_received[2]; 82 }; 83 84 struct tegra_drmfb_attach_args { 85 struct drm_device *tfa_drm_dev; 86 struct drm_fb_helper *tfa_fb_helper; 87 struct drm_fb_helper_surface_size tfa_fb_sizes; 88 bus_space_tag_t tfa_fb_bst; 89 bus_dma_tag_t tfa_fb_dmat; 90 uint32_t tfa_fb_linebytes; 91 }; 92 93 struct tegra_crtc { 94 struct drm_crtc base; 95 bus_space_tag_t bst; 96 bus_space_handle_t bsh; 97 bus_size_t size; 98 int intr; 99 int index; 100 void *ih; 101 bool enabled; 102 struct clk *clk_parent; 103 104 struct drm_gem_cma_object *cursor_obj; 105 int cursor_x; 106 int cursor_y; 107 }; 108 109 struct tegra_encoder { 110 struct drm_encoder base; 111 bus_space_tag_t bst; 112 bus_space_handle_t bsh; 113 bus_size_t size; 114 }; 115 116 struct tegra_connector { 117 struct drm_connector base; 118 i2c_tag_t ddc; 119 struct i2c_adapter *adapter; 120 struct fdtbus_gpio_pin *hpd; 121 122 bool has_hdmi_sink; 123 bool has_audio; 124 }; 125 126 struct tegra_framebuffer { 127 struct drm_framebuffer base; 128 struct drm_gem_cma_object *obj; 129 }; 130 131 struct tegra_fbdev { 132 struct drm_fb_helper helper; 133 }; 134 135 struct tegra_drm_task { 136 union { 137 SIMPLEQ_ENTRY(tegra_drm_task) queue; 138 struct work work; 139 } tdt_u; 140 void (*tdt_fn)(struct tegra_drm_task *); 141 }; 142 143 #define HDMI_READ(enc, reg) \ 144 bus_space_read_4((enc)->bst, (enc)->bsh, (reg)) 145 #define HDMI_WRITE(enc, reg, val) \ 146 bus_space_write_4((enc)->bst, (enc)->bsh, (reg), (val)) 147 #define HDMI_SET_CLEAR(enc, reg, set, clr) \ 148 tegra_reg_set_clear((enc)->bst, (enc)->bsh, (reg), (set), (clr)) 149 150 #define DC_READ(crtc, reg) \ 151 bus_space_read_4((crtc)->bst, (crtc)->bsh, (reg)) 152 #define DC_WRITE(crtc, reg, val) \ 153 bus_space_write_4((crtc)->bst, (crtc)->bsh, (reg), (val)) 154 #define DC_SET_CLEAR(crtc, reg, set, clr) \ 155 tegra_reg_set_clear((crtc)->bst, (crtc)->bsh, (reg), (set), (clr)) 156 157 #define TEGRA_DC_DEPTH 32 158 159 #define tegra_drm_private(ddev) (ddev)->dev_private 160 #define to_tegra_crtc(x) container_of(x, struct tegra_crtc, base) 161 #define to_tegra_encoder(x) container_of(x, struct tegra_encoder, base) 162 #define to_tegra_connector(x) container_of(x, struct tegra_connector, base) 163 #define to_tegra_framebuffer(x) container_of(x, struct tegra_framebuffer, base) 164 #define to_tegra_fbdev(x) container_of(x, struct tegra_fbdev, helper) 165 166 int tegra_drm_mode_init(struct drm_device *); 167 int tegra_drm_fb_init(struct drm_device *); 168 u32 tegra_drm_get_vblank_counter(struct drm_device *, unsigned int); 169 int tegra_drm_enable_vblank(struct drm_device *, unsigned int); 170 void tegra_drm_disable_vblank(struct drm_device *, unsigned int); 171 int tegra_drm_framebuffer_init(struct drm_device *, 172 struct tegra_framebuffer *); 173 174 void tegra_task_init(struct tegra_drm_task *, 175 void (*)(struct tegra_drm_task *)); 176 void tegra_task_schedule(device_t, struct tegra_drm_task *); 177 178 #endif /* _ARM_TEGRA_DRM_H */ 179