1 /* $NetBSD: if_stge.c,v 1.93 2024/07/05 04:31:51 rin Exp $ */
2
3 /*-
4 * Copyright (c) 2001 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 /*
33 * Device driver for the Sundance Tech. TC9021 10/100/1000
34 * Ethernet controller.
35 */
36
37 #include <sys/cdefs.h>
38 __KERNEL_RCSID(0, "$NetBSD: if_stge.c,v 1.93 2024/07/05 04:31:51 rin Exp $");
39
40
41 #include <sys/param.h>
42 #include <sys/systm.h>
43 #include <sys/callout.h>
44 #include <sys/mbuf.h>
45 #include <sys/kernel.h>
46 #include <sys/socket.h>
47 #include <sys/ioctl.h>
48 #include <sys/errno.h>
49 #include <sys/device.h>
50 #include <sys/queue.h>
51
52 #include <net/if.h>
53 #include <net/if_dl.h>
54 #include <net/if_media.h>
55 #include <net/if_ether.h>
56
57 #include <net/bpf.h>
58
59 #include <sys/bus.h>
60 #include <sys/intr.h>
61
62 #include <dev/mii/mii.h>
63 #include <dev/mii/miivar.h>
64 #include <dev/mii/mii_bitbang.h>
65
66 #include <dev/pci/pcireg.h>
67 #include <dev/pci/pcivar.h>
68 #include <dev/pci/pcidevs.h>
69
70 #include <dev/pci/if_stgereg.h>
71
72 #include <prop/proplib.h>
73
74 /* #define STGE_CU_BUG 1 */
75 #define STGE_VLAN_UNTAG 1
76 /* #define STGE_VLAN_CFI 1 */
77
78 /*
79 * Transmit descriptor list size.
80 */
81 #define STGE_NTXDESC 256
82 #define STGE_NTXDESC_MASK (STGE_NTXDESC - 1)
83 #define STGE_NEXTTX(x) (((x) + 1) & STGE_NTXDESC_MASK)
84
85 /*
86 * Receive descriptor list size.
87 */
88 #define STGE_NRXDESC 256
89 #define STGE_NRXDESC_MASK (STGE_NRXDESC - 1)
90 #define STGE_NEXTRX(x) (((x) + 1) & STGE_NRXDESC_MASK)
91
92 /*
93 * Only interrupt every N frames. Must be a power-of-two.
94 */
95 #define STGE_TXINTR_SPACING 16
96 #define STGE_TXINTR_SPACING_MASK (STGE_TXINTR_SPACING - 1)
97
98 /*
99 * Control structures are DMA'd to the TC9021 chip. We allocate them in
100 * a single clump that maps to a single DMA segment to make several things
101 * easier.
102 */
103 struct stge_control_data {
104 /*
105 * The transmit descriptors.
106 */
107 struct stge_tfd scd_txdescs[STGE_NTXDESC];
108
109 /*
110 * The receive descriptors.
111 */
112 struct stge_rfd scd_rxdescs[STGE_NRXDESC];
113 };
114
115 #define STGE_CDOFF(x) offsetof(struct stge_control_data, x)
116 #define STGE_CDTXOFF(x) STGE_CDOFF(scd_txdescs[(x)])
117 #define STGE_CDRXOFF(x) STGE_CDOFF(scd_rxdescs[(x)])
118
119 /*
120 * Software state for transmit and receive jobs.
121 */
122 struct stge_descsoft {
123 struct mbuf *ds_mbuf; /* head of our mbuf chain */
124 bus_dmamap_t ds_dmamap; /* our DMA map */
125 };
126
127 /*
128 * Software state per device.
129 */
130 struct stge_softc {
131 device_t sc_dev; /* generic device information */
132 bus_space_tag_t sc_st; /* bus space tag */
133 bus_space_handle_t sc_sh; /* bus space handle */
134 bus_dma_tag_t sc_dmat; /* bus DMA tag */
135 struct ethercom sc_ethercom; /* ethernet common data */
136 int sc_rev; /* silicon revision */
137
138 void *sc_ih; /* interrupt cookie */
139
140 struct mii_data sc_mii; /* MII/media information */
141
142 callout_t sc_tick_ch; /* tick callout */
143
144 bus_dmamap_t sc_cddmamap; /* control data DMA map */
145 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr
146
147 /*
148 * Software state for transmit and receive descriptors.
149 */
150 struct stge_descsoft sc_txsoft[STGE_NTXDESC];
151 struct stge_descsoft sc_rxsoft[STGE_NRXDESC];
152
153 /*
154 * Control data structures.
155 */
156 struct stge_control_data *sc_control_data;
157 #define sc_txdescs sc_control_data->scd_txdescs
158 #define sc_rxdescs sc_control_data->scd_rxdescs
159
160 #ifdef STGE_EVENT_COUNTERS
161 /*
162 * Event counters.
163 */
164 struct evcnt sc_ev_txstall; /* Tx stalled */
165 struct evcnt sc_ev_txdmaintr; /* Tx DMA interrupts */
166 struct evcnt sc_ev_txindintr; /* Tx Indicate interrupts */
167 struct evcnt sc_ev_rxintr; /* Rx interrupts */
168
169 struct evcnt sc_ev_txseg1; /* Tx packets w/ 1 segment */
170 struct evcnt sc_ev_txseg2; /* Tx packets w/ 2 segments */
171 struct evcnt sc_ev_txseg3; /* Tx packets w/ 3 segments */
172 struct evcnt sc_ev_txseg4; /* Tx packets w/ 4 segments */
173 struct evcnt sc_ev_txseg5; /* Tx packets w/ 5 segments */
174 struct evcnt sc_ev_txsegmore; /* Tx packets w/ more than 5 segments */
175 struct evcnt sc_ev_txcopy; /* Tx packets that we had to copy */
176
177 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */
178 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */
179 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-bound */
180
181 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */
182 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */
183 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */
184 #endif /* STGE_EVENT_COUNTERS */
185
186 int sc_txpending; /* number of Tx requests pending */
187 int sc_txdirty; /* first dirty Tx descriptor */
188 int sc_txlast; /* last used Tx descriptor */
189
190 int sc_rxptr; /* next ready Rx descriptor/descsoft */
191 int sc_rxdiscard;
192 int sc_rxlen;
193 struct mbuf *sc_rxhead;
194 struct mbuf *sc_rxtail;
195 struct mbuf **sc_rxtailp;
196
197 int sc_txthresh; /* Tx threshold */
198 uint32_t sc_usefiber:1; /* if we're fiber */
199 uint32_t sc_stge1023:1; /* are we a 1023 */
200 uint32_t sc_DMACtrl; /* prototype DMACtrl register */
201 uint32_t sc_MACCtrl; /* prototype MacCtrl register */
202 uint16_t sc_IntEnable; /* prototype IntEnable register */
203 uint16_t sc_ReceiveMode; /* prototype ReceiveMode register */
204 uint8_t sc_PhyCtrl; /* prototype PhyCtrl register */
205 };
206
207 #define STGE_RXCHAIN_RESET(sc) \
208 do { \
209 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \
210 *(sc)->sc_rxtailp = NULL; \
211 (sc)->sc_rxlen = 0; \
212 } while (/*CONSTCOND*/0)
213
214 #define STGE_RXCHAIN_LINK(sc, m) \
215 do { \
216 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \
217 (sc)->sc_rxtailp = &(m)->m_next; \
218 } while (/*CONSTCOND*/0)
219
220 /*
221 * Register access macros
222 */
223 #define CSR_WRITE_4(_sc, reg, val) \
224 bus_space_write_4((_sc)->sc_st, (_sc)->sc_sh, (reg), (val))
225 #define CSR_WRITE_2(_sc, reg, val) \
226 bus_space_write_2((_sc)->sc_st, (_sc)->sc_sh, (reg), (val))
227 #define CSR_WRITE_1(_sc, reg, val) \
228 bus_space_write_1((_sc)->sc_st, (_sc)->sc_sh, (reg), (val))
229
230 #define CSR_READ_4(_sc, reg) \
231 bus_space_read_4((_sc)->sc_st, (_sc)->sc_sh, (reg))
232 #define CSR_READ_2(_sc, reg) \
233 bus_space_read_2((_sc)->sc_st, (_sc)->sc_sh, (reg))
234 #define CSR_READ_1(_sc, reg) \
235 bus_space_read_1((_sc)->sc_st, (_sc)->sc_sh, (reg))
236
237 #define STGE_TIMEOUT 1000
238
239 #ifdef STGE_EVENT_COUNTERS
240 #define STGE_EVCNT_INCR(ev) (ev)->ev_count++
241 #else
242 #define STGE_EVCNT_INCR(ev) /* nothing */
243 #endif
244
245 #define STGE_CDTXADDR(sc, x) ((sc)->sc_cddma + STGE_CDTXOFF((x)))
246 #define STGE_CDRXADDR(sc, x) ((sc)->sc_cddma + STGE_CDRXOFF((x)))
247
248 #define STGE_CDTXSYNC(sc, x, ops) \
249 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \
250 STGE_CDTXOFF((x)), sizeof(struct stge_tfd), (ops))
251
252 #define STGE_CDRXSYNC(sc, x, ops) \
253 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \
254 STGE_CDRXOFF((x)), sizeof(struct stge_rfd), (ops))
255
256 #define STGE_INIT_RXDESC(sc, x) \
257 do { \
258 struct stge_descsoft *__ds = &(sc)->sc_rxsoft[(x)]; \
259 struct stge_rfd *__rfd = &(sc)->sc_rxdescs[(x)]; \
260 \
261 /* \
262 * Note: We scoot the packet forward 2 bytes in the buffer \
263 * so that the payload after the Ethernet header is aligned \
264 * to a 4-byte boundary. \
265 */ \
266 __rfd->rfd_frag.frag_word0 = \
267 htole64(FRAG_ADDR(__ds->ds_dmamap->dm_segs[0].ds_addr + 2) |\
268 FRAG_LEN(MCLBYTES - 2)); \
269 __rfd->rfd_next = \
270 htole64((uint64_t)STGE_CDRXADDR((sc), STGE_NEXTRX((x)))); \
271 __rfd->rfd_status = 0; \
272 STGE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); \
273 } while (/*CONSTCOND*/0)
274
275 static void stge_start(struct ifnet *);
276 static void stge_watchdog(struct ifnet *);
277 static int stge_ioctl(struct ifnet *, u_long, void *);
278 static int stge_init(struct ifnet *);
279 static void stge_stop(struct ifnet *, int);
280
281 static bool stge_shutdown(device_t, int);
282
283 static void stge_reset(struct stge_softc *);
284 static void stge_rxdrain(struct stge_softc *);
285 static int stge_add_rxbuf(struct stge_softc *, int);
286 static void stge_read_eeprom(struct stge_softc *, int, uint16_t *);
287 static void stge_tick(void *);
288
289 static void stge_stats_update(struct stge_softc *);
290
291 static void stge_set_filter(struct stge_softc *);
292
293 static int stge_intr(void *);
294 static void stge_txintr(struct stge_softc *);
295 static void stge_rxintr(struct stge_softc *);
296
297 static int stge_mii_readreg(device_t, int, int, uint16_t *);
298 static int stge_mii_writereg(device_t, int, int, uint16_t);
299 static void stge_mii_statchg(struct ifnet *);
300
301 static int stge_match(device_t, cfdata_t, void *);
302 static void stge_attach(device_t, device_t, void *);
303
304 int stge_copy_small = 0;
305
306 CFATTACH_DECL_NEW(stge, sizeof(struct stge_softc),
307 stge_match, stge_attach, NULL, NULL);
308
309 static uint32_t stge_mii_bitbang_read(device_t);
310 static void stge_mii_bitbang_write(device_t, uint32_t);
311
312 static const struct mii_bitbang_ops stge_mii_bitbang_ops = {
313 stge_mii_bitbang_read,
314 stge_mii_bitbang_write,
315 {
316 PC_MgmtData, /* MII_BIT_MDO */
317 PC_MgmtData, /* MII_BIT_MDI */
318 PC_MgmtClk, /* MII_BIT_MDC */
319 PC_MgmtDir, /* MII_BIT_DIR_HOST_PHY */
320 0, /* MII_BIT_DIR_PHY_HOST */
321 }
322 };
323
324 /*
325 * Devices supported by this driver.
326 */
327 static const struct stge_product {
328 pci_vendor_id_t stge_vendor;
329 pci_product_id_t stge_product;
330 const char *stge_name;
331 } stge_products[] = {
332 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST1023,
333 "Sundance ST-1023 Gigabit Ethernet" },
334
335 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST2021,
336 "Sundance ST-2021 Gigabit Ethernet" },
337
338 { PCI_VENDOR_TAMARACK, PCI_PRODUCT_TAMARACK_TC9021,
339 "Tamarack TC9021 Gigabit Ethernet" },
340
341 { PCI_VENDOR_TAMARACK, PCI_PRODUCT_TAMARACK_TC9021_ALT,
342 "Tamarack TC9021 Gigabit Ethernet" },
343
344 /*
345 * The Sundance sample boards use the Sundance vendor ID,
346 * but the Tamarack product ID.
347 */
348 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_TAMARACK_TC9021,
349 "Sundance TC9021 Gigabit Ethernet" },
350
351 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_TAMARACK_TC9021_ALT,
352 "Sundance TC9021 Gigabit Ethernet" },
353
354 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DL4000,
355 "D-Link DL-4000 Gigabit Ethernet" },
356
357 { PCI_VENDOR_ANTARES, PCI_PRODUCT_ANTARES_TC9021,
358 "Antares Gigabit Ethernet" },
359
360 { 0, 0,
361 NULL },
362 };
363
364 static const struct stge_product *
stge_lookup(const struct pci_attach_args * pa)365 stge_lookup(const struct pci_attach_args *pa)
366 {
367 const struct stge_product *sp;
368
369 for (sp = stge_products; sp->stge_name != NULL; sp++) {
370 if (PCI_VENDOR(pa->pa_id) == sp->stge_vendor &&
371 PCI_PRODUCT(pa->pa_id) == sp->stge_product)
372 return (sp);
373 }
374 return (NULL);
375 }
376
377 static int
stge_match(device_t parent,cfdata_t cf,void * aux)378 stge_match(device_t parent, cfdata_t cf, void *aux)
379 {
380 struct pci_attach_args *pa = aux;
381
382 if (stge_lookup(pa) != NULL)
383 return (1);
384
385 return (0);
386 }
387
388 static void
stge_attach(device_t parent,device_t self,void * aux)389 stge_attach(device_t parent, device_t self, void *aux)
390 {
391 struct stge_softc *sc = device_private(self);
392 struct pci_attach_args *pa = aux;
393 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
394 struct mii_data * const mii = &sc->sc_mii;
395 pci_chipset_tag_t pc = pa->pa_pc;
396 pci_intr_handle_t ih;
397 const char *intrstr = NULL;
398 bus_space_tag_t iot, memt;
399 bus_space_handle_t ioh, memh;
400 bus_dma_segment_t seg;
401 prop_dictionary_t dict;
402 prop_data_t data;
403 int ioh_valid, memh_valid;
404 int i, rseg, error;
405 const struct stge_product *sp;
406 uint8_t enaddr[ETHER_ADDR_LEN];
407 char intrbuf[PCI_INTRSTR_LEN];
408
409 sc->sc_dev = self;
410 callout_init(&sc->sc_tick_ch, 0);
411 callout_setfunc(&sc->sc_tick_ch, stge_tick, sc);
412
413 sp = stge_lookup(pa);
414 if (sp == NULL) {
415 printf("\n");
416 panic("ste_attach: impossible");
417 }
418
419 sc->sc_rev = PCI_REVISION(pa->pa_class);
420
421 pci_aprint_devinfo_fancy(pa, NULL, sp->stge_name, 1);
422
423 /*
424 * Map the device.
425 */
426 ioh_valid = (pci_mapreg_map(pa, STGE_PCI_IOBA,
427 PCI_MAPREG_TYPE_IO, 0,
428 &iot, &ioh, NULL, NULL) == 0);
429 memh_valid = (pci_mapreg_map(pa, STGE_PCI_MMBA,
430 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0,
431 &memt, &memh, NULL, NULL) == 0);
432
433 if (memh_valid) {
434 sc->sc_st = memt;
435 sc->sc_sh = memh;
436 } else if (ioh_valid) {
437 sc->sc_st = iot;
438 sc->sc_sh = ioh;
439 } else {
440 aprint_error_dev(self, "unable to map device registers\n");
441 return;
442 }
443
444 /*
445 * We have a 40-bit limit on our DMA addresses. This isn't an
446 * issue if we're only using a 32-bit DMA tag, but we have to
447 * account for it if the 64-bit DMA tag is available.
448 */
449 if (pci_dma64_available(pa)) {
450 if (bus_dmatag_subregion(pa->pa_dmat64,
451 0,
452 (bus_addr_t)FRAG_ADDR_MASK,
453 &sc->sc_dmat,
454 BUS_DMA_WAITOK) != 0) {
455 aprint_error_dev(self,
456 "WARNING: failed to restrict dma range,"
457 " falling back to parent bus dma range\n");
458 sc->sc_dmat = pa->pa_dmat64;
459 }
460 } else {
461 sc->sc_dmat = pa->pa_dmat;
462 }
463
464 /* Enable bus mastering. */
465 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
466 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) |
467 PCI_COMMAND_MASTER_ENABLE);
468
469 /* power up chip */
470 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, NULL)) &&
471 error != EOPNOTSUPP) {
472 aprint_error_dev(self, "cannot activate %d\n", error);
473 return;
474 }
475 /*
476 * Map and establish our interrupt.
477 */
478 if (pci_intr_map(pa, &ih)) {
479 aprint_error_dev(self, "unable to map interrupt\n");
480 return;
481 }
482 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf));
483 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, stge_intr, sc,
484 device_xname(self));
485 if (sc->sc_ih == NULL) {
486 aprint_error_dev(self, "unable to establish interrupt");
487 if (intrstr != NULL)
488 aprint_error(" at %s", intrstr);
489 aprint_error("\n");
490 return;
491 }
492 aprint_normal_dev(self, "interrupting at %s\n", intrstr);
493
494 /*
495 * Allocate the control data structures, and create and load the
496 * DMA map for it.
497 */
498 if ((error = bus_dmamem_alloc(sc->sc_dmat,
499 sizeof(struct stge_control_data), PAGE_SIZE, 0, &seg, 1, &rseg,
500 0)) != 0) {
501 aprint_error_dev(self,
502 "unable to allocate control data, error = %d\n", error);
503 goto fail_0;
504 }
505
506 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg,
507 sizeof(struct stge_control_data), (void **)&sc->sc_control_data,
508 BUS_DMA_COHERENT)) != 0) {
509 aprint_error_dev(self,
510 "unable to map control data, error = %d\n", error);
511 goto fail_1;
512 }
513
514 if ((error = bus_dmamap_create(sc->sc_dmat,
515 sizeof(struct stge_control_data), 1,
516 sizeof(struct stge_control_data), 0, 0, &sc->sc_cddmamap)) != 0) {
517 aprint_error_dev(self,
518 "unable to create control data DMA map, error = %d\n",
519 error);
520 goto fail_2;
521 }
522
523 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap,
524 sc->sc_control_data, sizeof(struct stge_control_data), NULL,
525 0)) != 0) {
526 aprint_error_dev(self,
527 "unable to load control data DMA map, error = %d\n",
528 error);
529 goto fail_3;
530 }
531
532 /*
533 * Create the transmit buffer DMA maps. Note that rev B.3
534 * and earlier seem to have a bug regarding multi-fragment
535 * packets. We need to limit the number of Tx segments on
536 * such chips to 1.
537 */
538 for (i = 0; i < STGE_NTXDESC; i++) {
539 if ((error = bus_dmamap_create(sc->sc_dmat,
540 ETHER_MAX_LEN_JUMBO, STGE_NTXFRAGS, MCLBYTES, 0, 0,
541 &sc->sc_txsoft[i].ds_dmamap)) != 0) {
542 aprint_error_dev(self,
543 "unable to create tx DMA map %d, error = %d\n",
544 i, error);
545 goto fail_4;
546 }
547 }
548
549 /*
550 * Create the receive buffer DMA maps.
551 */
552 for (i = 0; i < STGE_NRXDESC; i++) {
553 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1,
554 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].ds_dmamap)) != 0) {
555 aprint_error_dev(self,
556 "unable to create rx DMA map %d, error = %d\n",
557 i, error);
558 goto fail_5;
559 }
560 sc->sc_rxsoft[i].ds_mbuf = NULL;
561 }
562
563 /*
564 * Determine if we're copper or fiber. It affects how we
565 * reset the card.
566 */
567 if (CSR_READ_4(sc, STGE_AsicCtrl) & AC_PhyMedia)
568 sc->sc_usefiber = 1;
569 else
570 sc->sc_usefiber = 0;
571
572 /*
573 * Reset the chip to a known state.
574 */
575 stge_reset(sc);
576
577 /*
578 * Reading the station address from the EEPROM doesn't seem
579 * to work, at least on my sample boards. Instead, since
580 * the reset sequence does AutoInit, read it from the station
581 * address registers. For Sundance 1023 you can only read it
582 * from EEPROM.
583 */
584 if (sp->stge_product != PCI_PRODUCT_SUNDANCETI_ST1023) {
585 enaddr[0] = CSR_READ_2(sc, STGE_StationAddress0) & 0xff;
586 enaddr[1] = CSR_READ_2(sc, STGE_StationAddress0) >> 8;
587 enaddr[2] = CSR_READ_2(sc, STGE_StationAddress1) & 0xff;
588 enaddr[3] = CSR_READ_2(sc, STGE_StationAddress1) >> 8;
589 enaddr[4] = CSR_READ_2(sc, STGE_StationAddress2) & 0xff;
590 enaddr[5] = CSR_READ_2(sc, STGE_StationAddress2) >> 8;
591 sc->sc_stge1023 = 0;
592 } else {
593 data = prop_dictionary_get(device_properties(self),
594 "mac-address");
595 if (data != NULL) {
596 /*
597 * Try to get the station address from device
598 * properties first, in case the EEPROM is missing.
599 */
600 KASSERT(prop_object_type(data) == PROP_TYPE_DATA);
601 KASSERT(prop_data_size(data) == ETHER_ADDR_LEN);
602 (void)memcpy(enaddr, prop_data_value(data),
603 ETHER_ADDR_LEN);
604 } else {
605 uint16_t myaddr[ETHER_ADDR_LEN / 2];
606 for (i = 0; i <ETHER_ADDR_LEN / 2; i++) {
607 stge_read_eeprom(sc,
608 STGE_EEPROM_StationAddress0 + i,
609 &myaddr[i]);
610 myaddr[i] = le16toh(myaddr[i]);
611 }
612 (void)memcpy(enaddr, myaddr, sizeof(enaddr));
613 }
614 sc->sc_stge1023 = 1;
615 }
616
617 /* Set need_loaddspcode before mii_attach() */
618 dict = device_properties(self);
619 prop_dictionary_set_bool(dict, "need_loaddspcode",
620 ((sc->sc_rev >= 0x40) && (sc->sc_rev <= 0x4e)) ? true : false);
621
622 aprint_normal_dev(self, "Ethernet address %s\n",
623 ether_sprintf(enaddr));
624
625 /*
626 * Read some important bits from the PhyCtrl register.
627 */
628 sc->sc_PhyCtrl = CSR_READ_1(sc, STGE_PhyCtrl) &
629 (PC_PhyDuplexPolarity | PC_PhyLnkPolarity);
630
631 /*
632 * Initialize our media structures and probe the MII.
633 */
634 mii->mii_ifp = ifp;
635 mii->mii_readreg = stge_mii_readreg;
636 mii->mii_writereg = stge_mii_writereg;
637 mii->mii_statchg = stge_mii_statchg;
638 sc->sc_ethercom.ec_mii = mii;
639 ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange,
640 ether_mediastatus);
641 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY,
642 MII_OFFSET_ANY, MIIF_DOPAUSE);
643 if (LIST_FIRST(&mii->mii_phys) == NULL) {
644 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL);
645 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE);
646 } else
647 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO);
648
649 ifp = &sc->sc_ethercom.ec_if;
650 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ);
651 ifp->if_softc = sc;
652 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
653 ifp->if_ioctl = stge_ioctl;
654 ifp->if_start = stge_start;
655 ifp->if_watchdog = stge_watchdog;
656 ifp->if_init = stge_init;
657 ifp->if_stop = stge_stop;
658 IFQ_SET_READY(&ifp->if_snd);
659
660 /*
661 * The manual recommends disabling early transmit, so we
662 * do. It's disabled anyway, if using IP checksumming,
663 * since the entire packet must be in the FIFO in order
664 * for the chip to perform the checksum.
665 */
666 sc->sc_txthresh = 0x0fff;
667
668 /*
669 * Disable MWI if the PCI layer tells us to.
670 */
671 sc->sc_DMACtrl = 0;
672 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0)
673 sc->sc_DMACtrl |= DMAC_MWIDisable;
674
675 /*
676 * We can support 802.1Q VLAN-sized frames and jumbo
677 * Ethernet frames.
678 *
679 * XXX Figure out how to do hw-assisted VLAN tagging in
680 * XXX a reasonable way on this chip.
681 */
682 sc->sc_ethercom.ec_capabilities |=
683 ETHERCAP_VLAN_MTU | /* XXX ETHERCAP_JUMBO_MTU | */
684 ETHERCAP_VLAN_HWTAGGING;
685 sc->sc_ethercom.ec_capenable |= ETHERCAP_VLAN_HWTAGGING;
686
687 /*
688 * We can do IPv4/TCPv4/UDPv4 checksums in hardware.
689 */
690 sc->sc_ethercom.ec_if.if_capabilities |=
691 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx |
692 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx |
693 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx;
694
695 /*
696 * Attach the interface.
697 */
698 if_attach(ifp);
699 if_deferred_start_init(ifp, NULL);
700 ether_ifattach(ifp, enaddr);
701
702 #ifdef STGE_EVENT_COUNTERS
703 /*
704 * Attach event counters.
705 */
706 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC,
707 NULL, device_xname(self), "txstall");
708 evcnt_attach_dynamic(&sc->sc_ev_txdmaintr, EVCNT_TYPE_INTR,
709 NULL, device_xname(self), "txdmaintr");
710 evcnt_attach_dynamic(&sc->sc_ev_txindintr, EVCNT_TYPE_INTR,
711 NULL, device_xname(self), "txindintr");
712 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR,
713 NULL, device_xname(self), "rxintr");
714
715 evcnt_attach_dynamic(&sc->sc_ev_txseg1, EVCNT_TYPE_MISC,
716 NULL, device_xname(self), "txseg1");
717 evcnt_attach_dynamic(&sc->sc_ev_txseg2, EVCNT_TYPE_MISC,
718 NULL, device_xname(self), "txseg2");
719 evcnt_attach_dynamic(&sc->sc_ev_txseg3, EVCNT_TYPE_MISC,
720 NULL, device_xname(self), "txseg3");
721 evcnt_attach_dynamic(&sc->sc_ev_txseg4, EVCNT_TYPE_MISC,
722 NULL, device_xname(self), "txseg4");
723 evcnt_attach_dynamic(&sc->sc_ev_txseg5, EVCNT_TYPE_MISC,
724 NULL, device_xname(self), "txseg5");
725 evcnt_attach_dynamic(&sc->sc_ev_txsegmore, EVCNT_TYPE_MISC,
726 NULL, device_xname(self), "txsegmore");
727 evcnt_attach_dynamic(&sc->sc_ev_txcopy, EVCNT_TYPE_MISC,
728 NULL, device_xname(self), "txcopy");
729
730 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC,
731 NULL, device_xname(self), "rxipsum");
732 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC,
733 NULL, device_xname(self), "rxtcpsum");
734 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC,
735 NULL, device_xname(self), "rxudpsum");
736 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC,
737 NULL, device_xname(self), "txipsum");
738 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC,
739 NULL, device_xname(self), "txtcpsum");
740 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC,
741 NULL, device_xname(self), "txudpsum");
742 #endif /* STGE_EVENT_COUNTERS */
743
744 /*
745 * Make sure the interface is shutdown during reboot.
746 */
747 if (pmf_device_register1(self, NULL, NULL, stge_shutdown))
748 pmf_class_network_register(self, ifp);
749 else
750 aprint_error_dev(self, "couldn't establish power handler\n");
751
752 return;
753
754 /*
755 * Free any resources we've allocated during the failed attach
756 * attempt. Do this in reverse order and fall through.
757 */
758 fail_5:
759 for (i = 0; i < STGE_NRXDESC; i++) {
760 if (sc->sc_rxsoft[i].ds_dmamap != NULL)
761 bus_dmamap_destroy(sc->sc_dmat,
762 sc->sc_rxsoft[i].ds_dmamap);
763 }
764 fail_4:
765 for (i = 0; i < STGE_NTXDESC; i++) {
766 if (sc->sc_txsoft[i].ds_dmamap != NULL)
767 bus_dmamap_destroy(sc->sc_dmat,
768 sc->sc_txsoft[i].ds_dmamap);
769 }
770 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap);
771 fail_3:
772 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap);
773 fail_2:
774 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data,
775 sizeof(struct stge_control_data));
776 fail_1:
777 bus_dmamem_free(sc->sc_dmat, &seg, rseg);
778 fail_0:
779 return;
780 }
781
782 /*
783 * stge_shutdown:
784 *
785 * Make sure the interface is stopped at reboot time.
786 */
787 static bool
stge_shutdown(device_t self,int howto)788 stge_shutdown(device_t self, int howto)
789 {
790 struct stge_softc *sc = device_private(self);
791 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
792
793 stge_stop(ifp, 1);
794 stge_reset(sc);
795 return true;
796 }
797
798 static void
stge_dma_wait(struct stge_softc * sc)799 stge_dma_wait(struct stge_softc *sc)
800 {
801 int i;
802
803 for (i = 0; i < STGE_TIMEOUT; i++) {
804 delay(2);
805 if ((CSR_READ_4(sc, STGE_DMACtrl) & DMAC_TxDMAInProg) == 0)
806 break;
807 }
808
809 if (i == STGE_TIMEOUT)
810 printf("%s: DMA wait timed out\n", device_xname(sc->sc_dev));
811 }
812
813 /*
814 * stge_start: [ifnet interface function]
815 *
816 * Start packet transmission on the interface.
817 */
818 static void
stge_start(struct ifnet * ifp)819 stge_start(struct ifnet *ifp)
820 {
821 struct stge_softc *sc = ifp->if_softc;
822 struct mbuf *m0;
823 struct stge_descsoft *ds;
824 struct stge_tfd *tfd;
825 bus_dmamap_t dmamap;
826 int error, firsttx, nexttx, opending, seg, totlen;
827 uint64_t csum_flags;
828
829 if ((ifp->if_flags & IFF_RUNNING) != IFF_RUNNING)
830 return;
831
832 /*
833 * Remember the previous number of pending transmissions
834 * and the first descriptor we will use.
835 */
836 opending = sc->sc_txpending;
837 firsttx = STGE_NEXTTX(sc->sc_txlast);
838
839 /*
840 * Loop through the send queue, setting up transmit descriptors
841 * until we drain the queue, or use up all available transmit
842 * descriptors.
843 */
844 for (;;) {
845 uint64_t tfc;
846 bool have_vtag;
847 uint16_t vtag;
848
849 /*
850 * Grab a packet off the queue.
851 */
852 IFQ_POLL(&ifp->if_snd, m0);
853 if (m0 == NULL)
854 break;
855
856 /*
857 * Leave one unused descriptor at the end of the
858 * list to prevent wrapping completely around.
859 */
860 if (sc->sc_txpending == (STGE_NTXDESC - 1)) {
861 STGE_EVCNT_INCR(&sc->sc_ev_txstall);
862 break;
863 }
864
865 /*
866 * See if we have any VLAN stuff.
867 */
868 have_vtag = vlan_has_tag(m0);
869 if (have_vtag)
870 vtag = vlan_get_tag(m0);
871
872 /*
873 * Get the last and next available transmit descriptor.
874 */
875 nexttx = STGE_NEXTTX(sc->sc_txlast);
876 tfd = &sc->sc_txdescs[nexttx];
877 ds = &sc->sc_txsoft[nexttx];
878
879 dmamap = ds->ds_dmamap;
880
881 /*
882 * Load the DMA map. If this fails, the packet either
883 * didn't fit in the allotted number of segments, or we
884 * were short on resources. For the too-many-segments
885 * case, we simply report an error and drop the packet,
886 * since we can't sanely copy a jumbo packet to a single
887 * buffer.
888 */
889 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0,
890 BUS_DMA_NOWAIT);
891 if (error) {
892 if (error == EFBIG) {
893 printf("%s: Tx packet consumes too many "
894 "DMA segments, dropping...\n",
895 device_xname(sc->sc_dev));
896 IFQ_DEQUEUE(&ifp->if_snd, m0);
897 m_freem(m0);
898 continue;
899 }
900 /*
901 * Short on resources, just stop for now.
902 */
903 break;
904 }
905
906 IFQ_DEQUEUE(&ifp->if_snd, m0);
907
908 /*
909 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET.
910 */
911
912 /* Sync the DMA map. */
913 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize,
914 BUS_DMASYNC_PREWRITE);
915
916 /* Initialize the fragment list. */
917 for (totlen = 0, seg = 0; seg < dmamap->dm_nsegs; seg++) {
918 tfd->tfd_frags[seg].frag_word0 =
919 htole64(FRAG_ADDR(dmamap->dm_segs[seg].ds_addr) |
920 FRAG_LEN(dmamap->dm_segs[seg].ds_len));
921 totlen += dmamap->dm_segs[seg].ds_len;
922 }
923
924 #ifdef STGE_EVENT_COUNTERS
925 switch (dmamap->dm_nsegs) {
926 case 1:
927 STGE_EVCNT_INCR(&sc->sc_ev_txseg1);
928 break;
929 case 2:
930 STGE_EVCNT_INCR(&sc->sc_ev_txseg2);
931 break;
932 case 3:
933 STGE_EVCNT_INCR(&sc->sc_ev_txseg3);
934 break;
935 case 4:
936 STGE_EVCNT_INCR(&sc->sc_ev_txseg4);
937 break;
938 case 5:
939 STGE_EVCNT_INCR(&sc->sc_ev_txseg5);
940 break;
941 default:
942 STGE_EVCNT_INCR(&sc->sc_ev_txsegmore);
943 break;
944 }
945 #endif /* STGE_EVENT_COUNTERS */
946
947 /*
948 * Initialize checksumming flags in the descriptor.
949 * Byte-swap constants so the compiler can optimize.
950 */
951 csum_flags = 0;
952 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) {
953 STGE_EVCNT_INCR(&sc->sc_ev_txipsum);
954 csum_flags |= TFD_IPChecksumEnable;
955 }
956
957 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) {
958 STGE_EVCNT_INCR(&sc->sc_ev_txtcpsum);
959 csum_flags |= TFD_TCPChecksumEnable;
960 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) {
961 STGE_EVCNT_INCR(&sc->sc_ev_txudpsum);
962 csum_flags |= TFD_UDPChecksumEnable;
963 }
964
965 /*
966 * Initialize the descriptor and give it to the chip.
967 * Check to see if we have a VLAN tag to insert.
968 */
969
970 tfc = TFD_FrameId(nexttx) | TFD_WordAlign(/*totlen & */3) |
971 TFD_FragCount(seg) | csum_flags |
972 (((nexttx & STGE_TXINTR_SPACING_MASK) == 0) ?
973 TFD_TxDMAIndicate : 0);
974 if (have_vtag) {
975 #if 0
976 struct ether_header *eh =
977 mtod(m0, struct ether_header *);
978 uint16_t etype = ntohs(eh->ether_type);
979 printf("%s: xmit (tag %d) etype %x\n",
980 ifp->if_xname, *mtod(n, int *), etype);
981 #endif
982 tfc |= TFD_VLANTagInsert |
983 #ifdef STGE_VLAN_CFI
984 TFD_CFI |
985 #endif
986 TFD_VID(vtag);
987 }
988 tfd->tfd_control = htole64(tfc);
989
990 /* Sync the descriptor. */
991 STGE_CDTXSYNC(sc, nexttx,
992 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
993
994 /*
995 * Kick the transmit DMA logic.
996 */
997 CSR_WRITE_4(sc, STGE_DMACtrl,
998 sc->sc_DMACtrl | DMAC_TxDMAPollNow);
999
1000 /*
1001 * Store a pointer to the packet so we can free it later.
1002 */
1003 ds->ds_mbuf = m0;
1004
1005 /* Advance the tx pointer. */
1006 sc->sc_txpending++;
1007 sc->sc_txlast = nexttx;
1008
1009 /*
1010 * Pass the packet to any BPF listeners.
1011 */
1012 bpf_mtap(ifp, m0, BPF_D_OUT);
1013 }
1014
1015 if (sc->sc_txpending != opending) {
1016 /*
1017 * We enqueued packets. If the transmitter was idle,
1018 * reset the txdirty pointer.
1019 */
1020 if (opending == 0)
1021 sc->sc_txdirty = firsttx;
1022
1023 /* Set a watchdog timer in case the chip flakes out. */
1024 ifp->if_timer = 5;
1025 }
1026 }
1027
1028 /*
1029 * stge_watchdog: [ifnet interface function]
1030 *
1031 * Watchdog timer handler.
1032 */
1033 static void
stge_watchdog(struct ifnet * ifp)1034 stge_watchdog(struct ifnet *ifp)
1035 {
1036 struct stge_softc *sc = ifp->if_softc;
1037
1038 /*
1039 * Sweep up first, since we don't interrupt every frame.
1040 */
1041 stge_txintr(sc);
1042 if (sc->sc_txpending != 0) {
1043 printf("%s: device timeout\n", device_xname(sc->sc_dev));
1044 if_statinc(ifp, if_oerrors);
1045
1046 (void) stge_init(ifp);
1047
1048 /* Try to get more packets going. */
1049 stge_start(ifp);
1050 }
1051 }
1052
1053 /*
1054 * stge_ioctl: [ifnet interface function]
1055 *
1056 * Handle control requests from the operator.
1057 */
1058 static int
stge_ioctl(struct ifnet * ifp,u_long cmd,void * data)1059 stge_ioctl(struct ifnet *ifp, u_long cmd, void *data)
1060 {
1061 struct stge_softc *sc = ifp->if_softc;
1062 int s, error;
1063
1064 s = splnet();
1065
1066 error = ether_ioctl(ifp, cmd, data);
1067 if (error == ENETRESET) {
1068 error = 0;
1069
1070 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI)
1071 ;
1072 else if (ifp->if_flags & IFF_RUNNING) {
1073 /*
1074 * Multicast list has changed; set the hardware filter
1075 * accordingly.
1076 */
1077 stge_set_filter(sc);
1078 }
1079 }
1080
1081 /* Try to get more packets going. */
1082 stge_start(ifp);
1083
1084 splx(s);
1085 return (error);
1086 }
1087
1088 /*
1089 * stge_intr:
1090 *
1091 * Interrupt service routine.
1092 */
1093 static int
stge_intr(void * arg)1094 stge_intr(void *arg)
1095 {
1096 struct stge_softc *sc = arg;
1097 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1098 uint32_t txstat;
1099 int wantinit;
1100 uint16_t isr;
1101
1102 if ((CSR_READ_2(sc, STGE_IntStatus) & IS_InterruptStatus) == 0)
1103 return (0);
1104
1105 for (wantinit = 0; wantinit == 0;) {
1106 isr = CSR_READ_2(sc, STGE_IntStatusAck);
1107 if ((isr & sc->sc_IntEnable) == 0)
1108 break;
1109
1110 /* Host interface errors. */
1111 if (isr & IS_HostError) {
1112 printf("%s: Host interface error\n",
1113 device_xname(sc->sc_dev));
1114 wantinit = 1;
1115 continue;
1116 }
1117
1118 /* Receive interrupts. */
1119 if (isr & (IS_RxDMAComplete | IS_RFDListEnd)) {
1120 STGE_EVCNT_INCR(&sc->sc_ev_rxintr);
1121 stge_rxintr(sc);
1122 if (isr & IS_RFDListEnd) {
1123 printf("%s: receive ring overflow\n",
1124 device_xname(sc->sc_dev));
1125 /*
1126 * XXX Should try to recover from this
1127 * XXX more gracefully.
1128 */
1129 wantinit = 1;
1130 }
1131 }
1132
1133 /* Transmit interrupts. */
1134 if (isr & (IS_TxDMAComplete | IS_TxComplete)) {
1135 #ifdef STGE_EVENT_COUNTERS
1136 if (isr & IS_TxDMAComplete)
1137 STGE_EVCNT_INCR(&sc->sc_ev_txdmaintr);
1138 #endif
1139 stge_txintr(sc);
1140 }
1141
1142 /* Statistics overflow. */
1143 if (isr & IS_UpdateStats)
1144 stge_stats_update(sc);
1145
1146 /* Transmission errors. */
1147 if (isr & IS_TxComplete) {
1148 STGE_EVCNT_INCR(&sc->sc_ev_txindintr);
1149 for (;;) {
1150 txstat = CSR_READ_4(sc, STGE_TxStatus);
1151 if ((txstat & TS_TxComplete) == 0)
1152 break;
1153 if (txstat & TS_TxUnderrun) {
1154 sc->sc_txthresh++;
1155 if (sc->sc_txthresh > 0x0fff)
1156 sc->sc_txthresh = 0x0fff;
1157 printf("%s: transmit underrun, new "
1158 "threshold: %d bytes\n",
1159 device_xname(sc->sc_dev),
1160 sc->sc_txthresh << 5);
1161 }
1162 if (txstat & TS_MaxCollisions)
1163 printf("%s: excessive collisions\n",
1164 device_xname(sc->sc_dev));
1165 }
1166 wantinit = 1;
1167 }
1168
1169 }
1170
1171 if (wantinit)
1172 stge_init(ifp);
1173
1174 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable);
1175
1176 /* Try to get more packets going. */
1177 if_schedule_deferred_start(ifp);
1178
1179 return (1);
1180 }
1181
1182 /*
1183 * stge_txintr:
1184 *
1185 * Helper; handle transmit interrupts.
1186 */
1187 static void
stge_txintr(struct stge_softc * sc)1188 stge_txintr(struct stge_softc *sc)
1189 {
1190 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1191 struct stge_descsoft *ds;
1192 uint64_t control;
1193 int i;
1194
1195 /*
1196 * Go through our Tx list and free mbufs for those
1197 * frames which have been transmitted.
1198 */
1199 for (i = sc->sc_txdirty; sc->sc_txpending != 0;
1200 i = STGE_NEXTTX(i), sc->sc_txpending--) {
1201 ds = &sc->sc_txsoft[i];
1202
1203 STGE_CDTXSYNC(sc, i,
1204 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1205
1206 control = le64toh(sc->sc_txdescs[i].tfd_control);
1207 if ((control & TFD_TFDDone) == 0)
1208 break;
1209
1210 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap,
1211 0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
1212 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap);
1213 m_freem(ds->ds_mbuf);
1214 ds->ds_mbuf = NULL;
1215 }
1216
1217 /* Update the dirty transmit buffer pointer. */
1218 sc->sc_txdirty = i;
1219
1220 /*
1221 * If there are no more pending transmissions, cancel the watchdog
1222 * timer.
1223 */
1224 if (sc->sc_txpending == 0)
1225 ifp->if_timer = 0;
1226 }
1227
1228 /*
1229 * stge_rxintr:
1230 *
1231 * Helper; handle receive interrupts.
1232 */
1233 static void
stge_rxintr(struct stge_softc * sc)1234 stge_rxintr(struct stge_softc *sc)
1235 {
1236 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1237 struct stge_descsoft *ds;
1238 struct mbuf *m, *tailm;
1239 uint64_t status;
1240 int i, len;
1241
1242 for (i = sc->sc_rxptr;; i = STGE_NEXTRX(i)) {
1243 ds = &sc->sc_rxsoft[i];
1244
1245 STGE_CDRXSYNC(sc, i,
1246 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1247
1248 status = le64toh(sc->sc_rxdescs[i].rfd_status);
1249
1250 if ((status & RFD_RFDDone) == 0)
1251 break;
1252
1253 if (__predict_false(sc->sc_rxdiscard)) {
1254 STGE_INIT_RXDESC(sc, i);
1255 if (status & RFD_FrameEnd) {
1256 /* Reset our state. */
1257 sc->sc_rxdiscard = 0;
1258 }
1259 continue;
1260 }
1261
1262 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0,
1263 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
1264
1265 m = ds->ds_mbuf;
1266
1267 /*
1268 * Add a new receive buffer to the ring.
1269 */
1270 if (stge_add_rxbuf(sc, i) != 0) {
1271 /*
1272 * Failed, throw away what we've done so
1273 * far, and discard the rest of the packet.
1274 */
1275 if_statinc(ifp, if_ierrors);
1276 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0,
1277 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
1278 STGE_INIT_RXDESC(sc, i);
1279 if ((status & RFD_FrameEnd) == 0)
1280 sc->sc_rxdiscard = 1;
1281 m_freem(sc->sc_rxhead);
1282 STGE_RXCHAIN_RESET(sc);
1283 continue;
1284 }
1285
1286 #ifdef DIAGNOSTIC
1287 if (status & RFD_FrameStart) {
1288 KASSERT(sc->sc_rxhead == NULL);
1289 KASSERT(sc->sc_rxtailp == &sc->sc_rxhead);
1290 }
1291 #endif
1292
1293 STGE_RXCHAIN_LINK(sc, m);
1294
1295 /*
1296 * If this is not the end of the packet, keep
1297 * looking.
1298 */
1299 if ((status & RFD_FrameEnd) == 0) {
1300 sc->sc_rxlen += m->m_len;
1301 continue;
1302 }
1303
1304 /*
1305 * Okay, we have the entire packet now...
1306 */
1307 *sc->sc_rxtailp = NULL;
1308 m = sc->sc_rxhead;
1309 tailm = sc->sc_rxtail;
1310
1311 STGE_RXCHAIN_RESET(sc);
1312
1313 /*
1314 * If the packet had an error, drop it. Note we
1315 * count the error later in the periodic stats update.
1316 */
1317 if (status & (RFD_RxFIFOOverrun | RFD_RxRuntFrame |
1318 RFD_RxAlignmentError | RFD_RxFCSError |
1319 RFD_RxLengthError)) {
1320 m_freem(m);
1321 continue;
1322 }
1323
1324 /*
1325 * No errors.
1326 *
1327 * Note we have configured the chip to not include
1328 * the CRC at the end of the packet.
1329 */
1330 len = RFD_RxDMAFrameLen(status);
1331 tailm->m_len = len - sc->sc_rxlen;
1332
1333 /*
1334 * If the packet is small enough to fit in a
1335 * single header mbuf, allocate one and copy
1336 * the data into it. This greatly reduces
1337 * memory consumption when we receive lots
1338 * of small packets.
1339 */
1340 if (stge_copy_small != 0 && len <= (MHLEN - 2)) {
1341 struct mbuf *nm;
1342 MGETHDR(nm, M_DONTWAIT, MT_DATA);
1343 if (nm == NULL) {
1344 if_statinc(ifp, if_ierrors);
1345 m_freem(m);
1346 continue;
1347 }
1348 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner);
1349 nm->m_data += 2;
1350 nm->m_pkthdr.len = nm->m_len = len;
1351 m_copydata(m, 0, len, mtod(nm, void *));
1352 m_freem(m);
1353 m = nm;
1354 }
1355
1356 /*
1357 * Set the incoming checksum information for the packet.
1358 */
1359 if (status & RFD_IPDetected) {
1360 STGE_EVCNT_INCR(&sc->sc_ev_rxipsum);
1361 m->m_pkthdr.csum_flags |= M_CSUM_IPv4;
1362 if (status & RFD_IPError)
1363 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD;
1364 if (status & RFD_TCPDetected) {
1365 STGE_EVCNT_INCR(&sc->sc_ev_rxtcpsum);
1366 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4;
1367 if (status & RFD_TCPError)
1368 m->m_pkthdr.csum_flags |=
1369 M_CSUM_TCP_UDP_BAD;
1370 } else if (status & RFD_UDPDetected) {
1371 STGE_EVCNT_INCR(&sc->sc_ev_rxudpsum);
1372 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4;
1373 if (status & RFD_UDPError)
1374 m->m_pkthdr.csum_flags |=
1375 M_CSUM_TCP_UDP_BAD;
1376 }
1377 }
1378
1379 m_set_rcvif(m, ifp);
1380 m->m_pkthdr.len = len;
1381
1382 /*
1383 * Pass this up to any BPF listeners, but only
1384 * pass if up the stack if it's for us.
1385 */
1386 #ifdef STGE_VLAN_UNTAG
1387 /*
1388 * Check for VLAN tagged packets
1389 */
1390 if (status & RFD_VLANDetected)
1391 vlan_set_tag(m, RFD_TCI(status));
1392
1393 #endif
1394 #if 0
1395 if (status & RFD_VLANDetected) {
1396 struct ether_header *eh;
1397 uint16_t etype;
1398
1399 eh = mtod(m, struct ether_header *);
1400 etype = ntohs(eh->ether_type);
1401 printf("%s: VLANtag detected (TCI %d) etype %x\n",
1402 ifp->if_xname, (uint16_t) RFD_TCI(status),
1403 etype);
1404 }
1405 #endif
1406 /* Pass it on. */
1407 if_percpuq_enqueue(ifp->if_percpuq, m);
1408 }
1409
1410 /* Update the receive pointer. */
1411 sc->sc_rxptr = i;
1412 }
1413
1414 /*
1415 * stge_tick:
1416 *
1417 * One second timer, used to tick the MII.
1418 */
1419 static void
stge_tick(void * arg)1420 stge_tick(void *arg)
1421 {
1422 struct stge_softc *sc = arg;
1423 int s;
1424
1425 s = splnet();
1426 mii_tick(&sc->sc_mii);
1427 stge_stats_update(sc);
1428 splx(s);
1429
1430 callout_schedule(&sc->sc_tick_ch, hz);
1431 }
1432
1433 /*
1434 * stge_stats_update:
1435 *
1436 * Read the TC9021 statistics counters.
1437 */
1438 static void
stge_stats_update(struct stge_softc * sc)1439 stge_stats_update(struct stge_softc *sc)
1440 {
1441 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1442
1443 (void) CSR_READ_4(sc, STGE_OctetRcvOk);
1444
1445 (void) CSR_READ_4(sc, STGE_FramesRcvdOk);
1446
1447 net_stat_ref_t nsr = IF_STAT_GETREF(ifp);
1448
1449 if_statadd_ref(ifp, nsr, if_ierrors,
1450 (u_int) CSR_READ_2(sc, STGE_FramesLostRxErrors));
1451
1452 (void) CSR_READ_4(sc, STGE_OctetXmtdOk);
1453
1454 if_statadd_ref(ifp, nsr, if_opackets,
1455 CSR_READ_4(sc, STGE_FramesXmtdOk));
1456
1457 if_statadd_ref(ifp, nsr, if_collisions,
1458 CSR_READ_4(sc, STGE_LateCollisions) +
1459 CSR_READ_4(sc, STGE_MultiColFrames) +
1460 CSR_READ_4(sc, STGE_SingleColFrames));
1461
1462 if_statadd_ref(ifp, nsr, if_oerrors,
1463 (u_int) CSR_READ_2(sc, STGE_FramesAbortXSColls) +
1464 (u_int) CSR_READ_2(sc, STGE_FramesWEXDeferal));
1465
1466 IF_STAT_PUTREF(ifp);
1467 }
1468
1469 /*
1470 * stge_reset:
1471 *
1472 * Perform a soft reset on the TC9021.
1473 */
1474 static void
stge_reset(struct stge_softc * sc)1475 stge_reset(struct stge_softc *sc)
1476 {
1477 uint32_t ac;
1478 int i;
1479
1480 ac = CSR_READ_4(sc, STGE_AsicCtrl);
1481
1482 /*
1483 * Only assert RstOut if we're fiber. We need GMII clocks
1484 * to be present in order for the reset to complete on fiber
1485 * cards.
1486 */
1487 CSR_WRITE_4(sc, STGE_AsicCtrl,
1488 ac | AC_GlobalReset | AC_RxReset | AC_TxReset |
1489 AC_DMA | AC_FIFO | AC_Network | AC_Host | AC_AutoInit |
1490 (sc->sc_usefiber ? AC_RstOut : 0));
1491
1492 delay(50000);
1493
1494 for (i = 0; i < STGE_TIMEOUT; i++) {
1495 delay(5000);
1496 if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0)
1497 break;
1498 }
1499
1500 if (i == STGE_TIMEOUT)
1501 printf("%s: reset failed to complete\n",
1502 device_xname(sc->sc_dev));
1503
1504 delay(1000);
1505 }
1506
1507 /*
1508 * stge_init: [ ifnet interface function ]
1509 *
1510 * Initialize the interface. Must be called at splnet().
1511 */
1512 static int
stge_init(struct ifnet * ifp)1513 stge_init(struct ifnet *ifp)
1514 {
1515 struct stge_softc *sc = ifp->if_softc;
1516 struct stge_descsoft *ds;
1517 int i, error = 0;
1518
1519 /*
1520 * Cancel any pending I/O.
1521 */
1522 stge_stop(ifp, 0);
1523
1524 /*
1525 * Reset the chip to a known state.
1526 */
1527 stge_reset(sc);
1528
1529 /*
1530 * Initialize the transmit descriptor ring.
1531 */
1532 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs));
1533 for (i = 0; i < STGE_NTXDESC; i++) {
1534 sc->sc_txdescs[i].tfd_next = htole64(
1535 STGE_CDTXADDR(sc, STGE_NEXTTX(i)));
1536 sc->sc_txdescs[i].tfd_control = htole64(TFD_TFDDone);
1537 }
1538 sc->sc_txpending = 0;
1539 sc->sc_txdirty = 0;
1540 sc->sc_txlast = STGE_NTXDESC - 1;
1541
1542 /*
1543 * Initialize the receive descriptor and receive job
1544 * descriptor rings.
1545 */
1546 for (i = 0; i < STGE_NRXDESC; i++) {
1547 ds = &sc->sc_rxsoft[i];
1548 if (ds->ds_mbuf == NULL) {
1549 if ((error = stge_add_rxbuf(sc, i)) != 0) {
1550 printf("%s: unable to allocate or map rx "
1551 "buffer %d, error = %d\n",
1552 device_xname(sc->sc_dev), i, error);
1553 /*
1554 * XXX Should attempt to run with fewer receive
1555 * XXX buffers instead of just failing.
1556 */
1557 stge_rxdrain(sc);
1558 goto out;
1559 }
1560 } else
1561 STGE_INIT_RXDESC(sc, i);
1562 }
1563 sc->sc_rxptr = 0;
1564 sc->sc_rxdiscard = 0;
1565 STGE_RXCHAIN_RESET(sc);
1566
1567 /* Set the station address. */
1568 for (i = 0; i < 6; i++)
1569 CSR_WRITE_1(sc, STGE_StationAddress0 + i,
1570 CLLADDR(ifp->if_sadl)[i]);
1571
1572 /*
1573 * Set the statistics masks. Disable all the RMON stats,
1574 * and disable selected stats in the non-RMON stats registers.
1575 */
1576 CSR_WRITE_4(sc, STGE_RMONStatisticsMask, 0xffffffff);
1577 CSR_WRITE_4(sc, STGE_StatisticsMask,
1578 (1U << 1) | (1U << 2) | (1U << 3) | (1U << 4) | (1U << 5) |
1579 (1U << 6) | (1U << 7) | (1U << 8) | (1U << 9) | (1U << 10) |
1580 (1U << 13) | (1U << 14) | (1U << 15) | (1U << 19) | (1U << 20) |
1581 (1U << 21));
1582
1583 /* Set up the receive filter. */
1584 stge_set_filter(sc);
1585
1586 /*
1587 * Give the transmit and receive ring to the chip.
1588 */
1589 CSR_WRITE_4(sc, STGE_TFDListPtrHi,
1590 ((uint64_t)STGE_CDTXADDR(sc, sc->sc_txdirty)) >> 32);
1591 CSR_WRITE_4(sc, STGE_TFDListPtrLo,
1592 STGE_CDTXADDR(sc, sc->sc_txdirty));
1593
1594 CSR_WRITE_4(sc, STGE_RFDListPtrHi,
1595 ((uint64_t)STGE_CDRXADDR(sc, sc->sc_rxptr)) >> 32);
1596 CSR_WRITE_4(sc, STGE_RFDListPtrLo,
1597 STGE_CDRXADDR(sc, sc->sc_rxptr));
1598
1599 /*
1600 * Initialize the Tx auto-poll period. It's OK to make this number
1601 * large (255 is the max, but we use 127) -- we explicitly kick the
1602 * transmit engine when there's actually a packet.
1603 */
1604 CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127);
1605
1606 /* ..and the Rx auto-poll period. */
1607 CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 64);
1608
1609 /* Initialize the Tx start threshold. */
1610 CSR_WRITE_2(sc, STGE_TxStartThresh, sc->sc_txthresh);
1611
1612 /* RX DMA thresholds, from linux */
1613 CSR_WRITE_1(sc, STGE_RxDMABurstThresh, 0x30);
1614 CSR_WRITE_1(sc, STGE_RxDMAUrgentThresh, 0x30);
1615
1616 /* Rx early threhold, from Linux */
1617 CSR_WRITE_2(sc, STGE_RxEarlyThresh, 0x7ff);
1618
1619 /* Tx DMA thresholds, from Linux */
1620 CSR_WRITE_1(sc, STGE_TxDMABurstThresh, 0x30);
1621 CSR_WRITE_1(sc, STGE_TxDMAUrgentThresh, 0x04);
1622
1623 /*
1624 * Initialize the Rx DMA interrupt control register. We
1625 * request an interrupt after every incoming packet, but
1626 * defer it for 32us (64 * 512 ns). When the number of
1627 * interrupts pending reaches 8, we stop deferring the
1628 * interrupt, and signal it immediately.
1629 */
1630 CSR_WRITE_4(sc, STGE_RxDMAIntCtrl,
1631 RDIC_RxFrameCount(8) | RDIC_RxDMAWaitTime(512));
1632
1633 /*
1634 * Initialize the interrupt mask.
1635 */
1636 sc->sc_IntEnable = IS_HostError | IS_TxComplete | IS_UpdateStats |
1637 IS_TxDMAComplete | IS_RxDMAComplete | IS_RFDListEnd;
1638 CSR_WRITE_2(sc, STGE_IntStatus, 0xffff);
1639 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable);
1640
1641 /*
1642 * Configure the DMA engine.
1643 * XXX Should auto-tune TxBurstLimit.
1644 */
1645 CSR_WRITE_4(sc, STGE_DMACtrl, sc->sc_DMACtrl |
1646 DMAC_TxBurstLimit(3));
1647
1648 /*
1649 * Send a PAUSE frame when we reach 29,696 bytes in the Rx
1650 * FIFO, and send an un-PAUSE frame when we reach 3056 bytes
1651 * in the Rx FIFO.
1652 */
1653 CSR_WRITE_2(sc, STGE_FlowOnTresh, 29696 / 16);
1654 CSR_WRITE_2(sc, STGE_FlowOffThresh, 3056 / 16);
1655
1656 /*
1657 * Set the maximum frame size.
1658 */
1659 CSR_WRITE_2(sc, STGE_MaxFrameSize,
1660 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN +
1661 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ?
1662 ETHER_VLAN_ENCAP_LEN : 0));
1663
1664 /*
1665 * Initialize MacCtrl -- do it before setting the media,
1666 * as setting the media will actually program the register.
1667 *
1668 * Note: We have to poke the IFS value before poking
1669 * anything else.
1670 */
1671 sc->sc_MACCtrl = MC_IFSSelect(0);
1672 CSR_WRITE_4(sc, STGE_MACCtrl, sc->sc_MACCtrl);
1673 sc->sc_MACCtrl |= MC_StatisticsEnable | MC_TxEnable | MC_RxEnable;
1674 #ifdef STGE_VLAN_UNTAG
1675 sc->sc_MACCtrl |= MC_AutoVLANuntagging;
1676 #endif
1677
1678 if (sc->sc_rev >= 6) { /* >= B.2 */
1679 /* Multi-frag frame bug work-around. */
1680 CSR_WRITE_2(sc, STGE_DebugCtrl,
1681 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0200);
1682
1683 /* Tx Poll Now bug work-around. */
1684 CSR_WRITE_2(sc, STGE_DebugCtrl,
1685 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0010);
1686 /* XXX ? from linux */
1687 CSR_WRITE_2(sc, STGE_DebugCtrl,
1688 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0020);
1689 }
1690
1691 /*
1692 * Set the current media.
1693 */
1694 if ((error = ether_mediachange(ifp)) != 0)
1695 goto out;
1696
1697 /*
1698 * Start the one second MII clock.
1699 */
1700 callout_schedule(&sc->sc_tick_ch, hz);
1701
1702 /*
1703 * ...all done!
1704 */
1705 ifp->if_flags |= IFF_RUNNING;
1706
1707 out:
1708 if (error)
1709 printf("%s: interface not running\n", device_xname(sc->sc_dev));
1710 return (error);
1711 }
1712
1713 /*
1714 * stge_drain:
1715 *
1716 * Drain the receive queue.
1717 */
1718 static void
stge_rxdrain(struct stge_softc * sc)1719 stge_rxdrain(struct stge_softc *sc)
1720 {
1721 struct stge_descsoft *ds;
1722 int i;
1723
1724 for (i = 0; i < STGE_NRXDESC; i++) {
1725 ds = &sc->sc_rxsoft[i];
1726 if (ds->ds_mbuf != NULL) {
1727 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap);
1728 ds->ds_mbuf->m_next = NULL;
1729 m_freem(ds->ds_mbuf);
1730 ds->ds_mbuf = NULL;
1731 }
1732 }
1733 }
1734
1735 /*
1736 * stge_stop: [ ifnet interface function ]
1737 *
1738 * Stop transmission on the interface.
1739 */
1740 static void
stge_stop(struct ifnet * ifp,int disable)1741 stge_stop(struct ifnet *ifp, int disable)
1742 {
1743 struct stge_softc *sc = ifp->if_softc;
1744 struct stge_descsoft *ds;
1745 int i;
1746
1747 /*
1748 * Stop the one second clock.
1749 */
1750 callout_stop(&sc->sc_tick_ch);
1751
1752 /* Down the MII. */
1753 mii_down(&sc->sc_mii);
1754
1755 /*
1756 * Disable interrupts.
1757 */
1758 CSR_WRITE_2(sc, STGE_IntEnable, 0);
1759
1760 /*
1761 * Stop receiver, transmitter, and stats update.
1762 */
1763 CSR_WRITE_4(sc, STGE_MACCtrl,
1764 MC_StatisticsDisable | MC_TxDisable | MC_RxDisable);
1765
1766 /*
1767 * Stop the transmit and receive DMA.
1768 */
1769 stge_dma_wait(sc);
1770 CSR_WRITE_4(sc, STGE_TFDListPtrHi, 0);
1771 CSR_WRITE_4(sc, STGE_TFDListPtrLo, 0);
1772 CSR_WRITE_4(sc, STGE_RFDListPtrHi, 0);
1773 CSR_WRITE_4(sc, STGE_RFDListPtrLo, 0);
1774
1775 /*
1776 * Release any queued transmit buffers.
1777 */
1778 for (i = 0; i < STGE_NTXDESC; i++) {
1779 ds = &sc->sc_txsoft[i];
1780 if (ds->ds_mbuf != NULL) {
1781 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap);
1782 m_freem(ds->ds_mbuf);
1783 ds->ds_mbuf = NULL;
1784 }
1785 }
1786
1787 /*
1788 * Mark the interface down and cancel the watchdog timer.
1789 */
1790 ifp->if_flags &= ~IFF_RUNNING;
1791 ifp->if_timer = 0;
1792
1793 if (disable)
1794 stge_rxdrain(sc);
1795 }
1796
1797 static int
stge_eeprom_wait(struct stge_softc * sc)1798 stge_eeprom_wait(struct stge_softc *sc)
1799 {
1800 int i;
1801
1802 for (i = 0; i < STGE_TIMEOUT; i++) {
1803 delay(1000);
1804 if ((CSR_READ_2(sc, STGE_EepromCtrl) & EC_EepromBusy) == 0)
1805 return (0);
1806 }
1807 return (1);
1808 }
1809
1810 /*
1811 * stge_read_eeprom:
1812 *
1813 * Read data from the serial EEPROM.
1814 */
1815 static void
stge_read_eeprom(struct stge_softc * sc,int offset,uint16_t * data)1816 stge_read_eeprom(struct stge_softc *sc, int offset, uint16_t *data)
1817 {
1818
1819 if (stge_eeprom_wait(sc))
1820 printf("%s: EEPROM failed to come ready\n",
1821 device_xname(sc->sc_dev));
1822
1823 CSR_WRITE_2(sc, STGE_EepromCtrl,
1824 EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_RR));
1825 if (stge_eeprom_wait(sc))
1826 printf("%s: EEPROM read timed out\n",
1827 device_xname(sc->sc_dev));
1828 *data = CSR_READ_2(sc, STGE_EepromData);
1829 }
1830
1831 /*
1832 * stge_add_rxbuf:
1833 *
1834 * Add a receive buffer to the indicated descriptor.
1835 */
1836 static int
stge_add_rxbuf(struct stge_softc * sc,int idx)1837 stge_add_rxbuf(struct stge_softc *sc, int idx)
1838 {
1839 struct stge_descsoft *ds = &sc->sc_rxsoft[idx];
1840 struct mbuf *m;
1841 int error;
1842
1843 MGETHDR(m, M_DONTWAIT, MT_DATA);
1844 if (m == NULL)
1845 return (ENOBUFS);
1846
1847 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner);
1848 MCLGET(m, M_DONTWAIT);
1849 if ((m->m_flags & M_EXT) == 0) {
1850 m_freem(m);
1851 return (ENOBUFS);
1852 }
1853
1854 m->m_data = m->m_ext.ext_buf + 2;
1855 m->m_len = MCLBYTES - 2;
1856
1857 if (ds->ds_mbuf != NULL)
1858 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap);
1859
1860 ds->ds_mbuf = m;
1861
1862 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap,
1863 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT);
1864 if (error) {
1865 printf("%s: can't load rx DMA map %d, error = %d\n",
1866 device_xname(sc->sc_dev), idx, error);
1867 panic("stge_add_rxbuf"); /* XXX */
1868 }
1869
1870 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0,
1871 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
1872
1873 STGE_INIT_RXDESC(sc, idx);
1874
1875 return (0);
1876 }
1877
1878 /*
1879 * stge_set_filter:
1880 *
1881 * Set up the receive filter.
1882 */
1883 static void
stge_set_filter(struct stge_softc * sc)1884 stge_set_filter(struct stge_softc *sc)
1885 {
1886 struct ethercom *ec = &sc->sc_ethercom;
1887 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1888 struct ether_multi *enm;
1889 struct ether_multistep step;
1890 uint32_t crc;
1891 uint32_t mchash[2];
1892
1893 sc->sc_ReceiveMode = RM_ReceiveUnicast;
1894 if (ifp->if_flags & IFF_BROADCAST)
1895 sc->sc_ReceiveMode |= RM_ReceiveBroadcast;
1896
1897 /* XXX: ST1023 only works in promiscuous mode */
1898 if (sc->sc_stge1023)
1899 ifp->if_flags |= IFF_PROMISC;
1900
1901 if (ifp->if_flags & IFF_PROMISC) {
1902 sc->sc_ReceiveMode |= RM_ReceiveAllFrames;
1903 goto allmulti;
1904 }
1905
1906 /*
1907 * Set up the multicast address filter by passing all multicast
1908 * addresses through a CRC generator, and then using the low-order
1909 * 6 bits as an index into the 64 bit multicast hash table. The
1910 * high order bits select the register, while the rest of the bits
1911 * select the bit within the register.
1912 */
1913
1914 memset(mchash, 0, sizeof(mchash));
1915
1916 ETHER_LOCK(ec);
1917 ETHER_FIRST_MULTI(step, ec, enm);
1918 if (enm == NULL) {
1919 ETHER_UNLOCK(ec);
1920 goto done;
1921 }
1922
1923 while (enm != NULL) {
1924 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
1925 /*
1926 * We must listen to a range of multicast addresses.
1927 * For now, just accept all multicasts, rather than
1928 * trying to set only those filter bits needed to match
1929 * the range. (At this time, the only use of address
1930 * ranges is for IP multicast routing, for which the
1931 * range is big enough to require all bits set.)
1932 */
1933 ETHER_UNLOCK(ec);
1934 goto allmulti;
1935 }
1936
1937 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN);
1938
1939 /* Just want the 6 least significant bits. */
1940 crc &= 0x3f;
1941
1942 /* Set the corresponding bit in the hash table. */
1943 mchash[crc >> 5] |= 1 << (crc & 0x1f);
1944
1945 ETHER_NEXT_MULTI(step, enm);
1946 }
1947 ETHER_UNLOCK(ec);
1948
1949 sc->sc_ReceiveMode |= RM_ReceiveMulticastHash;
1950
1951 ifp->if_flags &= ~IFF_ALLMULTI;
1952 goto done;
1953
1954 allmulti:
1955 ifp->if_flags |= IFF_ALLMULTI;
1956 sc->sc_ReceiveMode |= RM_ReceiveMulticast;
1957
1958 done:
1959 if ((ifp->if_flags & IFF_ALLMULTI) == 0) {
1960 /*
1961 * Program the multicast hash table.
1962 */
1963 CSR_WRITE_4(sc, STGE_HashTable0, mchash[0]);
1964 CSR_WRITE_4(sc, STGE_HashTable1, mchash[1]);
1965 }
1966
1967 CSR_WRITE_2(sc, STGE_ReceiveMode, sc->sc_ReceiveMode);
1968 }
1969
1970 /*
1971 * stge_mii_readreg: [mii interface function]
1972 *
1973 * Read a PHY register on the MII of the TC9021.
1974 */
1975 static int
stge_mii_readreg(device_t self,int phy,int reg,uint16_t * val)1976 stge_mii_readreg(device_t self, int phy, int reg, uint16_t *val)
1977 {
1978
1979 return mii_bitbang_readreg(self, &stge_mii_bitbang_ops, phy, reg, val);
1980 }
1981
1982 /*
1983 * stge_mii_writereg: [mii interface function]
1984 *
1985 * Write a PHY register on the MII of the TC9021.
1986 */
1987 static int
stge_mii_writereg(device_t self,int phy,int reg,uint16_t val)1988 stge_mii_writereg(device_t self, int phy, int reg, uint16_t val)
1989 {
1990
1991 return mii_bitbang_writereg(self, &stge_mii_bitbang_ops, phy, reg,
1992 val);
1993 }
1994
1995 /*
1996 * stge_mii_statchg: [mii interface function]
1997 *
1998 * Callback from MII layer when media changes.
1999 */
2000 static void
stge_mii_statchg(struct ifnet * ifp)2001 stge_mii_statchg(struct ifnet *ifp)
2002 {
2003 struct stge_softc *sc = ifp->if_softc;
2004
2005 sc->sc_MACCtrl &= ~(MC_DuplexSelect | MC_RxFlowControlEnable |
2006 MC_TxFlowControlEnable);
2007
2008 if (sc->sc_mii.mii_media_active & IFM_FDX)
2009 sc->sc_MACCtrl |= MC_DuplexSelect;
2010 if ((sc->sc_mii.mii_media_active & IFM_ETH_RXPAUSE) != 0)
2011 sc->sc_MACCtrl |= MC_RxFlowControlEnable;
2012 if ((sc->sc_mii.mii_media_active & IFM_ETH_TXPAUSE) != 0)
2013 sc->sc_MACCtrl |= MC_TxFlowControlEnable;
2014
2015 CSR_WRITE_4(sc, STGE_MACCtrl, sc->sc_MACCtrl);
2016 }
2017
2018 /*
2019 * sste_mii_bitbang_read: [mii bit-bang interface function]
2020 *
2021 * Read the MII serial port for the MII bit-bang module.
2022 */
2023 static uint32_t
stge_mii_bitbang_read(device_t self)2024 stge_mii_bitbang_read(device_t self)
2025 {
2026 struct stge_softc *sc = device_private(self);
2027
2028 return (CSR_READ_1(sc, STGE_PhyCtrl));
2029 }
2030
2031 /*
2032 * stge_mii_bitbang_write: [mii big-bang interface function]
2033 *
2034 * Write the MII serial port for the MII bit-bang module.
2035 */
2036 static void
stge_mii_bitbang_write(device_t self,uint32_t val)2037 stge_mii_bitbang_write(device_t self, uint32_t val)
2038 {
2039 struct stge_softc *sc = device_private(self);
2040
2041 CSR_WRITE_1(sc, STGE_PhyCtrl, val | sc->sc_PhyCtrl);
2042 }
2043