1 /* $NetBSD: sunxi_hdmiphy.c,v 1.8 2021/01/27 03:10:20 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 2019 Jared McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30
31 __KERNEL_RCSID(0, "$NetBSD: sunxi_hdmiphy.c,v 1.8 2021/01/27 03:10:20 thorpej Exp $");
32
33 #include <sys/param.h>
34 #include <sys/bus.h>
35 #include <sys/device.h>
36 #include <sys/intr.h>
37 #include <sys/systm.h>
38
39 #include <dev/fdt/fdtvar.h>
40
41 #include <arm/sunxi/sunxi_hdmiphy.h>
42
43 #define DBG_CTRL 0x000
44 #define DBG_CTRL_POL __BITS(15,8)
45 #define DBG_CTRL_POL_NVSYNC 1
46 #define DBG_CTRL_POL_NHSYNC 2
47
48 #define READ_EN 0x010
49 #define READ_EN_MAGIC 0x54524545 /* "TREE" */
50
51 #define UNSCRAMBLE 0x014
52 #define UNSCRAMBLE_MAGIC 0x42494E47 /* "BING" */
53
54 #define ANA_CFG1 0x020
55 #define ANA_CFG1_ENRCAL __BIT(19)
56 #define ANA_CFG1_ENCALOG __BIT(18)
57 #define ANA_CFG1_TMDSCLK_EN __BIT(16)
58 #define ANA_CFG1_TXEN __BITS(15,12)
59 #define ANA_CFG1_BIASEN __BITS(11,8)
60 #define ANA_CFG1_ENP2S __BITS(7,4)
61 #define ANA_CFG1_CKEN __BIT(3)
62 #define ANA_CFG1_LDOEN __BIT(2)
63 #define ANA_CFG1_ENVBS __BIT(1)
64 #define ANA_CFG1_ENBI __BIT(0)
65
66 #define ANA_CFG2 0x024
67 #define ANA_CFG2_REG_RESDI __BITS(5,0)
68
69 #define ANA_CFG3 0x028
70 #define ANA_CFG3_REG_SDAEN __BIT(2)
71 #define ANA_CFG3_REG_SCLEN __BIT(0)
72
73 #define PLL_CFG1 0x02c
74 #define PLL_CFG1_REG_OD1 __BIT(31)
75 #define PLL_CFG1_REG_OD0 __BIT(30)
76 #define PLL_CFG1_CKIN_SEL __BIT(26)
77 #define PLL_CFG1_PLLEN __BIT(25)
78 #define PLL_CFG1_B_IN __BITS(5,0)
79
80 #define PLL_CFG2 0x030
81 #define PLL_CFG2_PREDIV __BITS(3,0)
82
83 #define PLL_CFG3 0x034
84
85 #define ANA_STS 0x038
86 #define ANA_STS_HPDO __BIT(19)
87 #define ANA_STS_B_OUT __BITS(16,11)
88 #define ANA_STS_RCALEND2D __BIT(7)
89 #define ANA_STS_RESDO2D __BITS(5,0)
90
91 #define CEC 0x03c
92 #define CEC_CONTROL_SEL __BIT(7)
93 #define CEC_INPUT_DATA __BIT(1)
94 #define CEC_OUTPUT_DATA __BIT(0)
95
96 #define CONTROLLER_VER 0xff8
97
98 #define PHY_VER 0xffc
99
100 struct sunxi_hdmiphy_softc;
101
102 static int sunxi_hdmiphy_match(device_t, cfdata_t, void *);
103 static void sunxi_hdmiphy_attach(device_t, device_t, void *);
104
105 static void sun8i_h3_hdmiphy_init(struct sunxi_hdmiphy_softc *);
106 static int sun8i_h3_hdmiphy_config(struct sunxi_hdmiphy_softc *, u_int);
107
108 struct sunxi_hdmiphy_data {
109 void (*init)(struct sunxi_hdmiphy_softc *);
110 int (*config)(struct sunxi_hdmiphy_softc *, u_int);
111 };
112
113 static const struct sunxi_hdmiphy_data sun8i_h3_hdmiphy_data = {
114 .init = sun8i_h3_hdmiphy_init,
115 .config = sun8i_h3_hdmiphy_config,
116 };
117
118 static const struct device_compatible_entry compat_data[] = {
119 { .compat = "allwinner,sun8i-h3-hdmi-phy",
120 .data = &sun8i_h3_hdmiphy_data },
121 { .compat = "allwinner,sun50i-a64-hdmi-phy",
122 .data = &sun8i_h3_hdmiphy_data },
123
124 DEVICE_COMPAT_EOL
125 };
126
127 struct sunxi_hdmiphy_softc {
128 device_t sc_dev;
129 bus_space_tag_t sc_bst;
130 bus_space_handle_t sc_bsh;
131
132 const struct sunxi_hdmiphy_data *sc_data;
133
134 struct fdtbus_reset *sc_rst;
135 struct clk *sc_clk_bus;
136 struct clk *sc_clk_mod;
137 struct clk *sc_clk_pll0;
138
139 u_int sc_rcalib;
140 };
141
142 #define PHY_READ(sc, reg) \
143 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
144 #define PHY_WRITE(sc, reg, val) \
145 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
146 #define PHY_SET_CLEAR(sc, reg, set, clr) \
147 do { \
148 uint32_t _tval = PHY_READ((sc), (reg)); \
149 _tval &= ~(clr); \
150 _tval |= (set); \
151 PHY_WRITE((sc), (reg), _tval); \
152 } while (0)
153 #define PHY_SET(sc, reg, set) \
154 PHY_SET_CLEAR(sc, reg, set, 0)
155 #define PHY_CLEAR(sc, reg, clr) \
156 PHY_SET_CLEAR(sc, reg, 0, clr)
157
158 CFATTACH_DECL_NEW(sunxi_hdmiphy, sizeof(struct sunxi_hdmiphy_softc),
159 sunxi_hdmiphy_match, sunxi_hdmiphy_attach, NULL, NULL);
160
161 static void *
sunxi_hdmiphy_acquire(device_t dev,const void * data,size_t len)162 sunxi_hdmiphy_acquire(device_t dev, const void *data, size_t len)
163 {
164 struct sunxi_hdmiphy_softc * const sc = device_private(dev);
165
166 if (len != 0)
167 return NULL;
168
169 return sc;
170 }
171
172 static void
sunxi_hdmiphy_release(device_t dev,void * priv)173 sunxi_hdmiphy_release(device_t dev, void *priv)
174 {
175 }
176
177 static int
sunxi_hdmiphy_enable(device_t dev,void * priv,bool enable)178 sunxi_hdmiphy_enable(device_t dev, void *priv, bool enable)
179 {
180 return 0;
181 }
182
183 static const struct fdtbus_phy_controller_func sunxi_hdmiphy_funcs = {
184 .acquire = sunxi_hdmiphy_acquire,
185 .release = sunxi_hdmiphy_release,
186 .enable = sunxi_hdmiphy_enable,
187 };
188
189 #ifdef SUNXI_HDMIPHY_DEBUG
190 static void
sunxi_hdmiphy_dump(struct sunxi_hdmiphy_softc * sc)191 sunxi_hdmiphy_dump(struct sunxi_hdmiphy_softc *sc)
192 {
193 device_printf(sc->sc_dev, "ANA_CFG1: %#x\tANA_CFG2: %#x\tANA_CFG3: %#x\n",
194 PHY_READ(sc, ANA_CFG1), PHY_READ(sc, ANA_CFG2), PHY_READ(sc, ANA_CFG3));
195 device_printf(sc->sc_dev, "PLL_CFG1: %#x\tPLL_CFG2: %#x\tPLL_CFG3: %#x\n",
196 PHY_READ(sc, PLL_CFG1), PHY_READ(sc, PLL_CFG2), PHY_READ(sc, PLL_CFG3));
197 device_printf(sc->sc_dev, "DBG_CTRL: %#x\tANA_STS: %#x\n",
198 PHY_READ(sc, DBG_CTRL), PHY_READ(sc, ANA_STS));
199 }
200 #endif
201
202 static void
sun8i_h3_hdmiphy_init(struct sunxi_hdmiphy_softc * sc)203 sun8i_h3_hdmiphy_init(struct sunxi_hdmiphy_softc *sc)
204 {
205 uint32_t val;
206 int retry;
207
208 PHY_WRITE(sc, ANA_CFG1, 0);
209
210 PHY_SET(sc, ANA_CFG1, ANA_CFG1_ENBI);
211 delay(5);
212
213 /* Enable TMDS clock */
214 PHY_SET(sc, ANA_CFG1, ANA_CFG1_TMDSCLK_EN);
215
216 /* Enable common voltage reference bias module */
217 PHY_SET(sc, ANA_CFG1, ANA_CFG1_ENVBS);
218 delay(20);
219
220 /* Enable internal LDO */
221 PHY_SET(sc, ANA_CFG1, ANA_CFG1_LDOEN);
222 delay(5);
223
224 /* Enable common clock module */
225 PHY_SET(sc, ANA_CFG1, ANA_CFG1_CKEN);
226 delay(100);
227
228 /* Enable resistance calibration analog and digital modules */
229 PHY_SET(sc, ANA_CFG1, ANA_CFG1_ENRCAL);
230 delay(200);
231 PHY_SET(sc, ANA_CFG1, ANA_CFG1_ENCALOG);
232
233 /* P2S module enable for TMDS data lane */
234 PHY_SET_CLEAR(sc, ANA_CFG1, __SHIFTIN(0x7, ANA_CFG1_ENP2S), ANA_CFG1_ENP2S);
235
236 /* Wait for resistance calibration to finish */
237 for (retry = 2000; retry > 0; retry--) {
238 if ((PHY_READ(sc, ANA_STS) & ANA_STS_RCALEND2D) != 0)
239 break;
240 delay(1);
241 }
242 if (retry == 0)
243 aprint_error_dev(sc->sc_dev, "HDMI PHY resistance calibration timed out\n");
244
245 /* Enable current and voltage module */
246 PHY_SET_CLEAR(sc, ANA_CFG1, __SHIFTIN(0xf, ANA_CFG1_BIASEN), ANA_CFG1_BIASEN);
247
248 /* P2S module enable for TMDS clock lane */
249 PHY_SET_CLEAR(sc, ANA_CFG1, __SHIFTIN(0xf, ANA_CFG1_ENP2S), ANA_CFG1_ENP2S);
250
251 /* Enable DDC */
252 PHY_SET(sc, ANA_CFG3, ANA_CFG3_REG_SDAEN | ANA_CFG3_REG_SCLEN);
253
254 /* Set parent clock to videopll0 */
255 PHY_CLEAR(sc, PLL_CFG1, PLL_CFG1_CKIN_SEL);
256
257 /* Clear software control of CEC pins */
258 PHY_CLEAR(sc, CEC, CEC_CONTROL_SEL);
259
260 /* Read calibration value for source termination resistors */
261 val = PHY_READ(sc, ANA_STS);
262 sc->sc_rcalib = __SHIFTOUT(val, ANA_STS_RESDO2D);
263 }
264
265 /*
266 * The following table is based on data from the "HDMI TX PHY S40 Specification".
267 */
268 static const struct sun8i_h3_hdmiphy_init {
269 /* PLL Recommended Configuration */
270 uint32_t pll_cfg1;
271 uint32_t pll_cfg2;
272 uint32_t pll_cfg3;
273 /* TMDS Characteristics Recommended Configuration */
274 uint32_t ana_cfg1;
275 uint32_t ana_cfg2;
276 uint32_t ana_cfg3;
277 bool ana_cfg2_rcal_200;
278 u_int b_offset;
279 } sun8i_h3_hdmiphy_inittab[] = {
280 /* 27 MHz */
281 [0] = {
282 .pll_cfg1 = 0x3ddc5040, .pll_cfg2 = 0x8008430a, .pll_cfg3 = 0x1,
283 .ana_cfg1 = 0x11ffff7f, .ana_cfg2 = 0x80623000, .ana_cfg3 = 0x0f80c285,
284 .ana_cfg2_rcal_200 = true,
285 },
286 /* 74.25 MHz */
287 [1] = {
288 .pll_cfg1 = 0x3ddc5040, .pll_cfg2 = 0x80084343, .pll_cfg3 = 0x1,
289 .ana_cfg1 = 0x11ffff7f, .ana_cfg2 = 0x80623000, .ana_cfg3 = 0x0f814385,
290 .ana_cfg2_rcal_200 = true,
291 },
292 /* 148.5 MHz */
293 [2] = {
294 .pll_cfg1 = 0x3ddc5040, .pll_cfg2 = 0x80084381, .pll_cfg3 = 0x1,
295 .ana_cfg1 = 0x01ffff7f, .ana_cfg2 = 0x8063a800, .ana_cfg3 = 0x0f81c485,
296 },
297 /* 297 MHz */
298 [3] = {
299 .pll_cfg1 = 0x35dc5fc0, .pll_cfg2 = 0x800863c0, .pll_cfg3 = 0x1,
300 .ana_cfg1 = 0x01ffff7f, .ana_cfg2 = 0x8063b000, .ana_cfg3 = 0x0f8246b5,
301 .b_offset = 2,
302 },
303 };
304
305 static int
sun8i_h3_hdmiphy_config(struct sunxi_hdmiphy_softc * sc,u_int rate)306 sun8i_h3_hdmiphy_config(struct sunxi_hdmiphy_softc *sc, u_int rate)
307 {
308 const struct sun8i_h3_hdmiphy_init *inittab;
309 u_int init_index, b_out, prediv;
310 uint32_t val, rcalib;
311
312 if (rate == 0) {
313 /* Disable the PHY */
314 PHY_WRITE(sc, ANA_CFG1, ANA_CFG1_LDOEN | ANA_CFG1_ENVBS | ANA_CFG1_ENBI);
315 PHY_WRITE(sc, PLL_CFG1, 0);
316 return 0;
317 }
318
319 init_index = 0;
320 if (rate > 27000000)
321 init_index++;
322 if (rate > 74250000)
323 init_index++;
324 if (rate > 148500000)
325 init_index++;
326 inittab = &sun8i_h3_hdmiphy_inittab[init_index];
327
328 val = PHY_READ(sc, PLL_CFG2);
329 prediv = val & PLL_CFG2_PREDIV;
330
331 /* Config PLL */
332 PHY_WRITE(sc, PLL_CFG1, inittab->pll_cfg1 & ~PLL_CFG1_CKIN_SEL);
333 PHY_WRITE(sc, PLL_CFG2, (inittab->pll_cfg2 & ~PLL_CFG2_PREDIV) | prediv);
334 delay(15000);
335 PHY_WRITE(sc, PLL_CFG3, inittab->pll_cfg3);
336
337 /* Enable PLL */
338 PHY_SET(sc, PLL_CFG1, PLL_CFG1_PLLEN);
339 delay(100000);
340
341 /* Config PLL */
342 val = PHY_READ(sc, ANA_STS);
343 b_out = __SHIFTOUT(val, ANA_STS_B_OUT);
344 b_out = MIN(b_out + inittab->b_offset, __SHIFTOUT_MASK(ANA_STS_B_OUT));
345
346 PHY_SET(sc, PLL_CFG1, PLL_CFG1_REG_OD1 | PLL_CFG1_REG_OD0);
347 PHY_SET(sc, PLL_CFG1, __SHIFTIN(b_out, PLL_CFG1_B_IN));
348 delay(100000);
349
350 /* Config TMDS characteristics */
351 if (inittab->ana_cfg2_rcal_200)
352 rcalib = sc->sc_rcalib >> 2;
353 else
354 rcalib = 0;
355 PHY_WRITE(sc, ANA_CFG1, inittab->ana_cfg1);
356 PHY_WRITE(sc, ANA_CFG2, inittab->ana_cfg2 | rcalib);
357 PHY_WRITE(sc, ANA_CFG3, inittab->ana_cfg3);
358
359 #ifdef SUNXI_HDMIPHY_DEBUG
360 sunxi_hdmiphy_dump(sc);
361 #endif
362
363 return 0;
364 }
365
366 static int
sunxi_hdmiphy_set_rate(struct sunxi_hdmiphy_softc * sc,u_int new_rate)367 sunxi_hdmiphy_set_rate(struct sunxi_hdmiphy_softc *sc, u_int new_rate)
368 {
369 u_int prediv, best_prediv, best_rate;
370
371 if (sc->sc_clk_pll0 == NULL)
372 return 0;
373
374 const u_int parent_rate = clk_get_rate(sc->sc_clk_pll0);
375
376 best_rate = 0;
377
378 for (prediv = 0; prediv <= __SHIFTOUT_MASK(PLL_CFG2_PREDIV); prediv++) {
379 const u_int tmp_rate = parent_rate / (prediv + 1);
380 const int diff = new_rate - tmp_rate;
381 if (diff >= 0 && tmp_rate > best_rate) {
382 best_rate = tmp_rate;
383 best_prediv = prediv;
384 }
385 }
386
387 if (best_rate == 0)
388 return ERANGE;
389
390 PHY_SET_CLEAR(sc, PLL_CFG2, __SHIFTIN(best_prediv, PLL_CFG2_PREDIV), PLL_CFG2_PREDIV);
391
392 return 0;
393 }
394
395 static int
sunxi_hdmiphy_match(device_t parent,cfdata_t cf,void * aux)396 sunxi_hdmiphy_match(device_t parent, cfdata_t cf, void *aux)
397 {
398 struct fdt_attach_args * const faa = aux;
399
400 return of_compatible_match(faa->faa_phandle, compat_data);
401 }
402
403 static void
sunxi_hdmiphy_attach(device_t parent,device_t self,void * aux)404 sunxi_hdmiphy_attach(device_t parent, device_t self, void *aux)
405 {
406 struct sunxi_hdmiphy_softc * const sc = device_private(self);
407 struct fdt_attach_args * const faa = aux;
408 const int phandle = faa->faa_phandle;
409 struct clk *clk_bus, *clk_mod, *clk_pll0;
410 struct fdtbus_reset *rst;
411 bus_addr_t addr;
412 bus_size_t size;
413
414 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
415 aprint_error(": couldn't get registers\n");
416 return;
417 }
418
419 rst = fdtbus_reset_get(phandle, "phy");
420 if (rst == NULL) {
421 aprint_error(": couldn't get reset\n");
422 return;
423 }
424 clk_bus = fdtbus_clock_get(phandle, "bus");
425 clk_mod = fdtbus_clock_get(phandle, "mod");
426 clk_pll0 = fdtbus_clock_get(phandle, "pll-0");
427 if (clk_bus == NULL || clk_mod == NULL || clk_pll0 == NULL) {
428 aprint_error(": couldn't get clocks\n");
429 return;
430 }
431
432 sc->sc_dev = self;
433 sc->sc_bst = faa->faa_bst;
434 sc->sc_data = of_compatible_lookup(phandle, compat_data)->data;
435 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
436 aprint_error(": couldn't map registers\n");
437 return;
438 }
439 sc->sc_rst = rst;
440 sc->sc_clk_bus = clk_bus;
441 sc->sc_clk_mod = clk_mod;
442 sc->sc_clk_pll0 = clk_pll0;
443
444 aprint_naive("\n");
445 aprint_normal(": HDMI PHY\n");
446
447 fdtbus_register_phy_controller(self, phandle, &sunxi_hdmiphy_funcs);
448 }
449
450 void
sunxi_hdmiphy_init(struct fdtbus_phy * phy)451 sunxi_hdmiphy_init(struct fdtbus_phy *phy)
452 {
453 device_t dev = fdtbus_phy_device(phy);
454 struct sunxi_hdmiphy_softc * const sc = device_private(dev);
455
456 clk_enable(sc->sc_clk_bus);
457 clk_enable(sc->sc_clk_mod);
458 clk_enable(sc->sc_clk_pll0);
459
460 fdtbus_reset_deassert(sc->sc_rst);
461
462 sc->sc_data->init(sc);
463
464 PHY_WRITE(sc, READ_EN, READ_EN_MAGIC);
465 PHY_WRITE(sc, UNSCRAMBLE, UNSCRAMBLE_MAGIC);
466
467 #ifdef SUNXI_HDMIPHY_DEBUG
468 sunxi_hdmiphy_dump(sc);
469 #endif
470 }
471
472 int
sunxi_hdmiphy_config(struct fdtbus_phy * phy,struct drm_display_mode * mode)473 sunxi_hdmiphy_config(struct fdtbus_phy *phy, struct drm_display_mode *mode)
474 {
475 device_t dev = fdtbus_phy_device(phy);
476 struct sunxi_hdmiphy_softc * const sc = device_private(dev);
477 u_int pol;
478 int error;
479
480 pol = 0;
481 if ((mode->flags & DRM_MODE_FLAG_NHSYNC) != 0)
482 pol |= __SHIFTIN(DBG_CTRL_POL_NHSYNC, DBG_CTRL_POL);
483 if ((mode->flags & DRM_MODE_FLAG_NVSYNC) != 0)
484 pol |= __SHIFTIN(DBG_CTRL_POL_NVSYNC, DBG_CTRL_POL);
485
486 PHY_SET_CLEAR(sc, DBG_CTRL, pol, DBG_CTRL_POL);
487
488 error = sunxi_hdmiphy_set_rate(sc, mode->crtc_clock * 1000);
489 if (error != 0) {
490 aprint_error_dev(dev, "failed to set HDMI PHY clock: %d\n", error);
491 return error;
492 }
493
494 return sc->sc_data->config(sc, mode->crtc_clock * 1000);
495 }
496
497 bool
sunxi_hdmiphy_detect(struct fdtbus_phy * phy,bool force)498 sunxi_hdmiphy_detect(struct fdtbus_phy *phy, bool force)
499 {
500 device_t dev = fdtbus_phy_device(phy);
501 struct sunxi_hdmiphy_softc * const sc = device_private(dev);
502 uint32_t val;
503
504 val = PHY_READ(sc, ANA_STS);
505
506 return ISSET(val, ANA_STS_HPDO);
507 }
508