xref: /netbsd-src/sys/arch/arm/sunxi/sun4i_a10_codec.c (revision e622eac459adf11c2e710d7a4de0f05510bbbe61)
1 /* $NetBSD: sun4i_a10_codec.c,v 1.3 2019/05/08 13:40:14 isaki Exp $ */
2 
3 /*-
4  * Copyright (c) 2014-2017 Jared McNeill <jmcneill@invisible.ca>
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  */
28 
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: sun4i_a10_codec.c,v 1.3 2019/05/08 13:40:14 isaki Exp $");
31 
32 #include <sys/param.h>
33 #include <sys/bus.h>
34 #include <sys/cpu.h>
35 #include <sys/device.h>
36 #include <sys/kmem.h>
37 #include <sys/bitops.h>
38 
39 #include <sys/audioio.h>
40 #include <dev/audio/audio_if.h>
41 
42 #include <arm/sunxi/sunxi_codec.h>
43 
44 #define	A10_DEFAULT_PAVOL	0x20
45 
46 #define	A10_DAC_ACTRL		0x10
47 #define	 A10_DACAREN		__BIT(31)
48 #define	 A10_DACALEN		__BIT(30)
49 #define	 A10_MIXEN		__BIT(29)
50 #define	 A10_LNG		__BIT(26)
51 #define	 A10_FMG		__BITS(25,23)
52 #define	 A10_MICG		__BITS(22,20)
53 #define	 A10_LLNS		__BIT(19)
54 #define	 A10_RLNS		__BIT(18)
55 #define	 A10_LFMS		__BIT(17)
56 #define	 A10_RFMS		__BIT(16)
57 #define	 A10_LDACLMIXS		__BIT(15)
58 #define	 A10_RDACRMIXS		__BIT(14)
59 #define	 A10_LDACRMIXS		__BIT(13)
60 #define	 A10_MICLS		__BIT(12)
61 #define	 A10_MICRS		__BIT(11)
62 #define	 A10_DACPAS		__BIT(8)
63 #define	 A10_MIXPAS		__BIT(7)
64 #define	 A10_PAMUTE		__BIT(6)
65 #define	 A10_PAVOL		__BITS(5,0)
66 
67 #define	A10_ADC_ACTRL		0x28
68 #define	 A10_ADCREN		__BIT(31)
69 #define	 A10_ADCLEN		__BIT(30)
70 #define	 A10_PREG1EN		__BIT(29)
71 #define	 A10_PREG2EN		__BIT(28)
72 #define	 A10_VMICEN		__BIT(27)
73 #define	 A10_PREG1		__BITS(26,25)
74 #define	 A10_PREG2		__BITS(24,23)
75 #define	 A10_ADCG		__BITS(22,20)
76 #define	 A10_ADCIS		__BITS(19,17)
77 #define	 A10_LNRDF		__BIT(16)
78 #define	 A10_LNPREG		__BITS(15,13)
79 #define	 A10_MIC1NEN		__BIT(12)
80 #define	 A10_DITHER		__BIT(8)
81 #define	 A10_PA_EN		__BIT(4)
82 #define	 A10_DDE		__BIT(3)
83 #define	 A10_COMPTEN		__BIT(2)
84 #define	 A10_PTDBS		__BITS(1,0)
85 
86 enum a10_codec_mixer_ctrl {
87 	A10_CODEC_OUTPUT_CLASS,
88 	A10_CODEC_INPUT_CLASS,
89 
90 	A10_CODEC_OUTPUT_MASTER_VOLUME,
91 	A10_CODEC_INPUT_DAC_VOLUME,
92 
93 	A10_CODEC_MIXER_CTRL_LAST
94 };
95 
96 static const struct a10_codec_mixer {
97 	const char *			name;
98 	enum a10_codec_mixer_ctrl	mixer_class;
99 	u_int				reg;
100 	u_int				mask;
101 } a10_codec_mixers[A10_CODEC_MIXER_CTRL_LAST] = {
102 	[A10_CODEC_OUTPUT_MASTER_VOLUME]	= { AudioNmaster,
103 	    A10_CODEC_OUTPUT_CLASS, A10_DAC_ACTRL, A10_PAVOL },
104 	[A10_CODEC_INPUT_DAC_VOLUME]		= { AudioNdac,
105 	    A10_CODEC_INPUT_CLASS, A10_DAC_ACTRL, A10_PAVOL },
106 };
107 
108 #define	RD4(sc, reg)			\
109 	bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
110 #define	WR4(sc, reg, val)		\
111 	bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
112 #define	SET4(sc, reg, mask)		\
113 	WR4((sc), (reg), RD4((sc), (reg)) | (mask))
114 #define	CLR4(sc, reg, mask)		\
115 	WR4((sc), (reg), RD4((sc), (reg)) & ~(mask))
116 
117 static int
a10_codec_init(struct sunxi_codec_softc * sc)118 a10_codec_init(struct sunxi_codec_softc *sc)
119 {
120 
121 	/* Unmute PA */
122 	SET4(sc, A10_DAC_ACTRL, A10_PAMUTE);
123 
124 	/* Set initial volume */
125 	CLR4(sc, A10_DAC_ACTRL, A10_PAVOL);
126 	SET4(sc, A10_DAC_ACTRL, __SHIFTIN(A10_DEFAULT_PAVOL, A10_PAVOL));
127 
128 	/* Enable DAC analog l/r channels and output mixer */
129 	SET4(sc, A10_DAC_ACTRL, A10_DACAREN | A10_DACALEN | A10_DACPAS);
130 
131 	/* Enable ADC analog l/r channels */
132 	SET4(sc, A10_ADC_ACTRL, A10_ADCREN | A10_ADCLEN);
133 
134 	/* Enable PA */
135 	SET4(sc, A10_ADC_ACTRL, A10_PA_EN);
136 
137 	return 0;
138 }
139 
140 static void
a10_codec_mute(struct sunxi_codec_softc * sc,int mute,u_int mode)141 a10_codec_mute(struct sunxi_codec_softc *sc, int mute, u_int mode)
142 {
143 	if (mode == AUMODE_PLAY) {
144 		if (sc->sc_pin_pa != NULL)
145 			fdtbus_gpio_write(sc->sc_pin_pa, !mute);
146 	}
147 }
148 
149 static int
a10_codec_set_port(struct sunxi_codec_softc * sc,mixer_ctrl_t * mc)150 a10_codec_set_port(struct sunxi_codec_softc *sc, mixer_ctrl_t *mc)
151 {
152 	const struct a10_codec_mixer *mix;
153 	u_int val, shift;
154 	int nvol;
155 
156 	switch (mc->dev) {
157 	case A10_CODEC_OUTPUT_MASTER_VOLUME:
158 	case A10_CODEC_INPUT_DAC_VOLUME:
159 		mix = &a10_codec_mixers[mc->dev];
160 		val = RD4(sc, mix->reg);
161 		shift = 8 - fls32(__SHIFTOUT_MASK(mix->mask));
162 		nvol = mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] >> shift;
163 		val &= ~mix->mask;
164 		val |= __SHIFTIN(nvol, mix->mask);
165 		WR4(sc, mix->reg, val);
166 		return 0;
167 	}
168 
169 	return ENXIO;
170 }
171 
172 static int
a10_codec_get_port(struct sunxi_codec_softc * sc,mixer_ctrl_t * mc)173 a10_codec_get_port(struct sunxi_codec_softc *sc, mixer_ctrl_t *mc)
174 {
175 	const struct a10_codec_mixer *mix;
176 	u_int val, shift;
177 	int nvol;
178 
179 	switch (mc->dev) {
180 	case A10_CODEC_OUTPUT_MASTER_VOLUME:
181 	case A10_CODEC_INPUT_DAC_VOLUME:
182 		mix = &a10_codec_mixers[mc->dev];
183 		val = RD4(sc, mix->reg);
184 		shift = 8 - fls32(__SHIFTOUT_MASK(mix->mask));
185 		nvol = __SHIFTOUT(val, mix->mask) << shift;
186 		mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] = nvol;
187 		mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] = nvol;
188 		return 0;
189 	}
190 
191 	return ENXIO;
192 }
193 
194 static int
a10_codec_query_devinfo(struct sunxi_codec_softc * sc,mixer_devinfo_t * di)195 a10_codec_query_devinfo(struct sunxi_codec_softc *sc, mixer_devinfo_t *di)
196 {
197 	const struct a10_codec_mixer *mix;
198 
199 	switch (di->index) {
200 	case A10_CODEC_OUTPUT_CLASS:
201 		di->mixer_class = di->index;
202 		strcpy(di->label.name, AudioCoutputs);
203 		di->type = AUDIO_MIXER_CLASS;
204 		di->next = di->prev = AUDIO_MIXER_LAST;
205 		return 0;
206 
207 	case A10_CODEC_INPUT_CLASS:
208 		di->mixer_class = di->index;
209 		strcpy(di->label.name, AudioCinputs);
210 		di->type = AUDIO_MIXER_CLASS;
211 		di->next = di->prev = AUDIO_MIXER_LAST;
212 		return 0;
213 
214 	case A10_CODEC_OUTPUT_MASTER_VOLUME:
215 	case A10_CODEC_INPUT_DAC_VOLUME:
216 		mix = &a10_codec_mixers[di->index];
217 		di->mixer_class = mix->mixer_class;
218 		strcpy(di->label.name, mix->name);
219 		di->un.v.delta =
220 		    256 / (__SHIFTOUT_MASK(mix->mask) + 1);
221 		di->type = AUDIO_MIXER_VALUE;
222 		di->next = di->prev = AUDIO_MIXER_LAST;
223 		di->un.v.num_channels = 2;
224 		strcpy(di->un.v.units.name, AudioNvolume);
225 		return 0;
226 	}
227 
228 	return ENXIO;
229 }
230 
231 const struct sunxi_codec_conf sun4i_a10_codecconf = {
232 	.name = "A10 Audio Codec",
233 
234 	.init = a10_codec_init,
235 	.mute = a10_codec_mute,
236 	.set_port = a10_codec_set_port,
237 	.get_port = a10_codec_get_port,
238 	.query_devinfo = a10_codec_query_devinfo,
239 
240 	.DPC		= 0x00,
241 	.DAC_FIFOC	= 0x04,
242 	.DAC_FIFOS	= 0x08,
243 	.DAC_TXDATA	= 0x0c,
244 	.ADC_FIFOC	= 0x1c,
245 	.ADC_FIFOS	= 0x20,
246 	.ADC_RXDATA	= 0x24,
247 	.DAC_CNT	= 0x30,
248 	.ADC_CNT	= 0x34,
249 };
250