1 /* RISC-V disassembler
2 Copyright (C) 2011-2024 Free Software Foundation, Inc.
3
4 Contributed by Andrew Waterman (andrew@sifive.com).
5 Based on MIPS target.
6
7 This file is part of the GNU opcodes library.
8
9 This library is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
12 any later version.
13
14 It is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
22
23 #include "sysdep.h"
24 #include "disassemble.h"
25 #include "libiberty.h"
26 #include "opcode/riscv.h"
27 #include "opintl.h"
28 #include "elf-bfd.h"
29 #include "elf/riscv.h"
30 #include "elfxx-riscv.h"
31
32 #include <stdint.h>
33 #include <ctype.h>
34
35 /* Current XLEN for the disassembler. */
36 static unsigned xlen = 0;
37
38 /* Default ISA specification version (constant as of now). */
39 static enum riscv_spec_class default_isa_spec = ISA_SPEC_CLASS_DRAFT - 1;
40
41 /* Default privileged specification
42 (as specified by the ELF attributes or the `priv-spec' option). */
43 static enum riscv_spec_class default_priv_spec = PRIV_SPEC_CLASS_NONE;
44
45 static riscv_subset_list_t riscv_subsets;
46 static riscv_parse_subset_t riscv_rps_dis =
47 {
48 &riscv_subsets, /* subset_list. */
49 opcodes_error_handler,/* error_handler. */
50 &xlen, /* xlen. */
51 &default_isa_spec, /* isa_spec. */
52 false, /* check_unknown_prefixed_ext. */
53 };
54
55 struct riscv_private_data
56 {
57 bfd_vma gp;
58 bfd_vma print_addr;
59 bfd_vma hi_addr[OP_MASK_RD + 1];
60 bool to_print_addr;
61 bool has_gp;
62 };
63
64 /* Used for mapping symbols. */
65 static int last_map_symbol = -1;
66 static bfd_vma last_stop_offset = 0;
67 static bfd_vma last_map_symbol_boundary = 0;
68 static enum riscv_seg_mstate last_map_state = MAP_NONE;
69 static asection *last_map_section = NULL;
70
71 /* Register names as used by the disassembler. */
72 static const char (*riscv_gpr_names)[NRC];
73 static const char (*riscv_fpr_names)[NRC];
74
75 /* If set, disassemble as most general instruction. */
76 static bool no_aliases = false;
77
78
79 /* Set default RISC-V disassembler options. */
80
81 static void
set_default_riscv_dis_options(void)82 set_default_riscv_dis_options (void)
83 {
84 riscv_gpr_names = riscv_gpr_names_abi;
85 riscv_fpr_names = riscv_fpr_names_abi;
86 no_aliases = false;
87 }
88
89 /* Parse RISC-V disassembler option (without arguments). */
90
91 static bool
parse_riscv_dis_option_without_args(const char * option)92 parse_riscv_dis_option_without_args (const char *option)
93 {
94 if (strcmp (option, "no-aliases") == 0)
95 no_aliases = true;
96 else if (strcmp (option, "numeric") == 0)
97 {
98 riscv_gpr_names = riscv_gpr_names_numeric;
99 riscv_fpr_names = riscv_fpr_names_numeric;
100 }
101 else
102 return false;
103 return true;
104 }
105
106 /* Parse RISC-V disassembler option (possibly with arguments). */
107
108 static void
parse_riscv_dis_option(const char * option)109 parse_riscv_dis_option (const char *option)
110 {
111 char *equal, *value;
112
113 if (parse_riscv_dis_option_without_args (option))
114 return;
115
116 equal = strchr (option, '=');
117 if (equal == NULL)
118 {
119 /* The option without '=' should be defined above. */
120 opcodes_error_handler (_("unrecognized disassembler option: %s"), option);
121 return;
122 }
123 if (equal == option
124 || *(equal + 1) == '\0')
125 {
126 /* Invalid options with '=', no option name before '=',
127 and no value after '='. */
128 opcodes_error_handler (_("unrecognized disassembler option with '=': %s"),
129 option);
130 return;
131 }
132
133 *equal = '\0';
134 value = equal + 1;
135 if (strcmp (option, "priv-spec") == 0)
136 {
137 enum riscv_spec_class priv_spec = PRIV_SPEC_CLASS_NONE;
138 const char *name = NULL;
139
140 RISCV_GET_PRIV_SPEC_CLASS (value, priv_spec);
141 if (priv_spec == PRIV_SPEC_CLASS_NONE)
142 opcodes_error_handler (_("unknown privileged spec set by %s=%s"),
143 option, value);
144 else if (default_priv_spec == PRIV_SPEC_CLASS_NONE)
145 default_priv_spec = priv_spec;
146 else if (default_priv_spec != priv_spec)
147 {
148 RISCV_GET_PRIV_SPEC_NAME (name, default_priv_spec);
149 opcodes_error_handler (_("mis-matched privilege spec set by %s=%s, "
150 "the elf privilege attribute is %s"),
151 option, value, name);
152 }
153 }
154 else
155 {
156 /* xgettext:c-format */
157 opcodes_error_handler (_("unrecognized disassembler option: %s"), option);
158 }
159 }
160
161 /* Parse RISC-V disassembler options. */
162
163 static void
parse_riscv_dis_options(const char * opts_in)164 parse_riscv_dis_options (const char *opts_in)
165 {
166 char *opts = xstrdup (opts_in), *opt = opts, *opt_end = opts;
167
168 set_default_riscv_dis_options ();
169
170 for ( ; opt_end != NULL; opt = opt_end + 1)
171 {
172 if ((opt_end = strchr (opt, ',')) != NULL)
173 *opt_end = 0;
174 parse_riscv_dis_option (opt);
175 }
176
177 free (opts);
178 }
179
180 /* Print one argument from an array. */
181
182 static void
arg_print(struct disassemble_info * info,unsigned long val,const char * const * array,size_t size)183 arg_print (struct disassemble_info *info, unsigned long val,
184 const char* const* array, size_t size)
185 {
186 const char *s = val >= size || array[val] == NULL ? "unknown" : array[val];
187 (*info->fprintf_styled_func) (info->stream, dis_style_text, "%s", s);
188 }
189
190 /* If we need to print an address, set its value and state. */
191
192 static void
maybe_print_address(struct riscv_private_data * pd,int base_reg,int offset,int wide)193 maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset,
194 int wide)
195 {
196 if (pd->hi_addr[base_reg] != (bfd_vma)-1)
197 {
198 pd->print_addr = (base_reg != 0 ? pd->hi_addr[base_reg] : 0) + offset;
199 pd->hi_addr[base_reg] = -1;
200 }
201 else if (base_reg == X_GP && pd->has_gp)
202 pd->print_addr = pd->gp + offset;
203 else if (base_reg == X_TP || base_reg == 0)
204 pd->print_addr = offset;
205 else
206 return; /* Don't print the address. */
207 pd->to_print_addr = true;
208
209 /* Sign-extend a 32-bit value to a 64-bit value. */
210 if (wide)
211 pd->print_addr = (bfd_vma)(int32_t) pd->print_addr;
212
213 /* Fit into a 32-bit value on RV32. */
214 if (xlen == 32)
215 pd->print_addr = (bfd_vma)(uint32_t)pd->print_addr;
216 }
217
218 /* Print insn arguments for 32/64-bit code. */
219
220 static void
print_insn_args(const char * oparg,insn_t l,bfd_vma pc,disassemble_info * info)221 print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info)
222 {
223 struct riscv_private_data *pd = info->private_data;
224 int rs1 = (l >> OP_SH_RS1) & OP_MASK_RS1;
225 int rd = (l >> OP_SH_RD) & OP_MASK_RD;
226 fprintf_styled_ftype print = info->fprintf_styled_func;
227 const char *opargStart;
228
229 if (*oparg != '\0')
230 print (info->stream, dis_style_text, "\t");
231
232 for (; *oparg != '\0'; oparg++)
233 {
234 opargStart = oparg;
235 switch (*oparg)
236 {
237 case 'C': /* RVC */
238 switch (*++oparg)
239 {
240 case 's': /* RS1 x8-x15. */
241 case 'w': /* RS1 x8-x15. */
242 print (info->stream, dis_style_register, "%s",
243 riscv_gpr_names[EXTRACT_OPERAND (CRS1S, l) + 8]);
244 break;
245 case 't': /* RS2 x8-x15. */
246 case 'x': /* RS2 x8-x15. */
247 print (info->stream, dis_style_register, "%s",
248 riscv_gpr_names[EXTRACT_OPERAND (CRS2S, l) + 8]);
249 break;
250 case 'U': /* RS1, constrained to equal RD. */
251 print (info->stream, dis_style_register,
252 "%s", riscv_gpr_names[rd]);
253 break;
254 case 'c': /* RS1, constrained to equal sp. */
255 print (info->stream, dis_style_register, "%s",
256 riscv_gpr_names[X_SP]);
257 break;
258 case 'V': /* RS2 */
259 print (info->stream, dis_style_register, "%s",
260 riscv_gpr_names[EXTRACT_OPERAND (CRS2, l)]);
261 break;
262 case 'o':
263 case 'j':
264 if (((l & MASK_C_ADDI) == MATCH_C_ADDI) && rd != 0)
265 maybe_print_address (pd, rd, EXTRACT_CITYPE_IMM (l), 0);
266 if (info->mach == bfd_mach_riscv64
267 && ((l & MASK_C_ADDIW) == MATCH_C_ADDIW) && rd != 0)
268 maybe_print_address (pd, rd, EXTRACT_CITYPE_IMM (l), 1);
269 print (info->stream, dis_style_immediate, "%d",
270 (int)EXTRACT_CITYPE_IMM (l));
271 break;
272 case 'k':
273 print (info->stream, dis_style_address_offset, "%d",
274 (int)EXTRACT_CLTYPE_LW_IMM (l));
275 break;
276 case 'l':
277 print (info->stream, dis_style_address_offset, "%d",
278 (int)EXTRACT_CLTYPE_LD_IMM (l));
279 break;
280 case 'm':
281 print (info->stream, dis_style_address_offset, "%d",
282 (int)EXTRACT_CITYPE_LWSP_IMM (l));
283 break;
284 case 'n':
285 print (info->stream, dis_style_address_offset, "%d",
286 (int)EXTRACT_CITYPE_LDSP_IMM (l));
287 break;
288 case 'K':
289 print (info->stream, dis_style_immediate, "%d",
290 (int)EXTRACT_CIWTYPE_ADDI4SPN_IMM (l));
291 break;
292 case 'L':
293 print (info->stream, dis_style_immediate, "%d",
294 (int)EXTRACT_CITYPE_ADDI16SP_IMM (l));
295 break;
296 case 'M':
297 print (info->stream, dis_style_address_offset, "%d",
298 (int)EXTRACT_CSSTYPE_SWSP_IMM (l));
299 break;
300 case 'N':
301 print (info->stream, dis_style_address_offset, "%d",
302 (int)EXTRACT_CSSTYPE_SDSP_IMM (l));
303 break;
304 case 'p':
305 info->target = EXTRACT_CBTYPE_IMM (l) + pc;
306 (*info->print_address_func) (info->target, info);
307 break;
308 case 'a':
309 info->target = EXTRACT_CJTYPE_IMM (l) + pc;
310 (*info->print_address_func) (info->target, info);
311 break;
312 case 'u':
313 print (info->stream, dis_style_immediate, "0x%x",
314 (unsigned)(EXTRACT_CITYPE_IMM (l) & (RISCV_BIGIMM_REACH-1)));
315 break;
316 case '>':
317 print (info->stream, dis_style_immediate, "0x%x",
318 (unsigned)EXTRACT_CITYPE_IMM (l) & 0x3f);
319 break;
320 case '<':
321 print (info->stream, dis_style_immediate, "0x%x",
322 (unsigned)EXTRACT_CITYPE_IMM (l) & 0x1f);
323 break;
324 case 'T': /* Floating-point RS2. */
325 print (info->stream, dis_style_register, "%s",
326 riscv_fpr_names[EXTRACT_OPERAND (CRS2, l)]);
327 break;
328 case 'D': /* Floating-point RS2 x8-x15. */
329 print (info->stream, dis_style_register, "%s",
330 riscv_fpr_names[EXTRACT_OPERAND (CRS2S, l) + 8]);
331 break;
332 }
333 break;
334
335 case 'V': /* RVV */
336 switch (*++oparg)
337 {
338 case 'd':
339 case 'f':
340 print (info->stream, dis_style_register, "%s",
341 riscv_vecr_names_numeric[EXTRACT_OPERAND (VD, l)]);
342 break;
343 case 'e':
344 if (!EXTRACT_OPERAND (VWD, l))
345 print (info->stream, dis_style_register, "%s",
346 riscv_gpr_names[0]);
347 else
348 print (info->stream, dis_style_register, "%s",
349 riscv_vecr_names_numeric[EXTRACT_OPERAND (VD, l)]);
350 break;
351 case 's':
352 print (info->stream, dis_style_register, "%s",
353 riscv_vecr_names_numeric[EXTRACT_OPERAND (VS1, l)]);
354 break;
355 case 't':
356 case 'u': /* VS1 == VS2 already verified at this point. */
357 case 'v': /* VD == VS1 == VS2 already verified at this point. */
358 print (info->stream, dis_style_register, "%s",
359 riscv_vecr_names_numeric[EXTRACT_OPERAND (VS2, l)]);
360 break;
361 case '0':
362 print (info->stream, dis_style_register, "%s",
363 riscv_vecr_names_numeric[0]);
364 break;
365 case 'b':
366 case 'c':
367 {
368 int imm = (*oparg == 'b') ? EXTRACT_RVV_VB_IMM (l)
369 : EXTRACT_RVV_VC_IMM (l);
370 unsigned int imm_vlmul = EXTRACT_OPERAND (VLMUL, imm);
371 unsigned int imm_vsew = EXTRACT_OPERAND (VSEW, imm);
372 unsigned int imm_vta = EXTRACT_OPERAND (VTA, imm);
373 unsigned int imm_vma = EXTRACT_OPERAND (VMA, imm);
374 unsigned int imm_vtype_res = (imm >> 8);
375
376 if (imm_vsew < ARRAY_SIZE (riscv_vsew)
377 && imm_vlmul < ARRAY_SIZE (riscv_vlmul)
378 && imm_vta < ARRAY_SIZE (riscv_vta)
379 && imm_vma < ARRAY_SIZE (riscv_vma)
380 && !imm_vtype_res
381 && riscv_vsew[imm_vsew] != NULL
382 && riscv_vlmul[imm_vlmul] != NULL)
383 print (info->stream, dis_style_text, "%s,%s,%s,%s",
384 riscv_vsew[imm_vsew],
385 riscv_vlmul[imm_vlmul], riscv_vta[imm_vta],
386 riscv_vma[imm_vma]);
387 else
388 print (info->stream, dis_style_immediate, "%d", imm);
389 }
390 break;
391 case 'i':
392 print (info->stream, dis_style_immediate, "%d",
393 (int)EXTRACT_RVV_VI_IMM (l));
394 break;
395 case 'j':
396 print (info->stream, dis_style_immediate, "%d",
397 (int)EXTRACT_RVV_VI_UIMM (l));
398 break;
399 case 'k':
400 print (info->stream, dis_style_immediate, "%d",
401 (int)EXTRACT_RVV_OFFSET (l));
402 break;
403 case 'l':
404 print (info->stream, dis_style_immediate, "%d",
405 (int)EXTRACT_RVV_VI_UIMM6 (l));
406 break;
407 case 'm':
408 if (!EXTRACT_OPERAND (VMASK, l))
409 {
410 print (info->stream, dis_style_text, ",");
411 print (info->stream, dis_style_register, "%s",
412 riscv_vecm_names_numeric[0]);
413 }
414 break;
415 }
416 break;
417
418 case ',':
419 case '(':
420 case ')':
421 case '[':
422 case ']':
423 print (info->stream, dis_style_text, "%c", *oparg);
424 break;
425
426 case '0':
427 /* Only print constant 0 if it is the last argument. */
428 if (!oparg[1])
429 print (info->stream, dis_style_immediate, "0");
430 break;
431
432 case 's':
433 if ((l & MASK_JALR) == MATCH_JALR)
434 maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 0);
435 print (info->stream, dis_style_register, "%s", riscv_gpr_names[rs1]);
436 break;
437
438 case 't':
439 print (info->stream, dis_style_register, "%s",
440 riscv_gpr_names[EXTRACT_OPERAND (RS2, l)]);
441 break;
442
443 case 'u':
444 print (info->stream, dis_style_immediate, "0x%x",
445 (unsigned)EXTRACT_UTYPE_IMM (l) >> RISCV_IMM_BITS);
446 break;
447
448 case 'm':
449 arg_print (info, EXTRACT_OPERAND (RM, l),
450 riscv_rm, ARRAY_SIZE (riscv_rm));
451 break;
452
453 case 'P':
454 arg_print (info, EXTRACT_OPERAND (PRED, l),
455 riscv_pred_succ, ARRAY_SIZE (riscv_pred_succ));
456 break;
457
458 case 'Q':
459 arg_print (info, EXTRACT_OPERAND (SUCC, l),
460 riscv_pred_succ, ARRAY_SIZE (riscv_pred_succ));
461 break;
462
463 case 'o':
464 maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 0);
465 /* Fall through. */
466 case 'j':
467 if (((l & MASK_ADDI) == MATCH_ADDI && rs1 != 0)
468 || (l & MASK_JALR) == MATCH_JALR)
469 maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 0);
470 if (info->mach == bfd_mach_riscv64
471 && ((l & MASK_ADDIW) == MATCH_ADDIW) && rs1 != 0)
472 maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 1);
473 print (info->stream, dis_style_immediate, "%d",
474 (int)EXTRACT_ITYPE_IMM (l));
475 break;
476
477 case 'q':
478 maybe_print_address (pd, rs1, EXTRACT_STYPE_IMM (l), 0);
479 print (info->stream, dis_style_address_offset, "%d",
480 (int)EXTRACT_STYPE_IMM (l));
481 break;
482
483 case 'a':
484 info->target = EXTRACT_JTYPE_IMM (l) + pc;
485 (*info->print_address_func) (info->target, info);
486 break;
487
488 case 'p':
489 info->target = EXTRACT_BTYPE_IMM (l) + pc;
490 (*info->print_address_func) (info->target, info);
491 break;
492
493 case 'd':
494 if ((l & MASK_AUIPC) == MATCH_AUIPC)
495 pd->hi_addr[rd] = pc + EXTRACT_UTYPE_IMM (l);
496 else if ((l & MASK_LUI) == MATCH_LUI)
497 pd->hi_addr[rd] = EXTRACT_UTYPE_IMM (l);
498 else if ((l & MASK_C_LUI) == MATCH_C_LUI)
499 pd->hi_addr[rd] = EXTRACT_CITYPE_LUI_IMM (l);
500 print (info->stream, dis_style_register, "%s", riscv_gpr_names[rd]);
501 break;
502
503 case 'y':
504 print (info->stream, dis_style_immediate, "0x%x",
505 EXTRACT_OPERAND (BS, l));
506 break;
507
508 case 'z':
509 print (info->stream, dis_style_register, "%s", riscv_gpr_names[0]);
510 break;
511
512 case '>':
513 print (info->stream, dis_style_immediate, "0x%x",
514 EXTRACT_OPERAND (SHAMT, l));
515 break;
516
517 case '<':
518 print (info->stream, dis_style_immediate, "0x%x",
519 EXTRACT_OPERAND (SHAMTW, l));
520 break;
521
522 case 'S':
523 case 'U':
524 print (info->stream, dis_style_register, "%s", riscv_fpr_names[rs1]);
525 break;
526
527 case 'T':
528 print (info->stream, dis_style_register, "%s",
529 riscv_fpr_names[EXTRACT_OPERAND (RS2, l)]);
530 break;
531
532 case 'D':
533 print (info->stream, dis_style_register, "%s", riscv_fpr_names[rd]);
534 break;
535
536 case 'R':
537 print (info->stream, dis_style_register, "%s",
538 riscv_fpr_names[EXTRACT_OPERAND (RS3, l)]);
539 break;
540
541 case 'E':
542 {
543 static const char *riscv_csr_hash[4096]; /* Total 2^12 CSRs. */
544 static bool init_csr = false;
545 unsigned int csr = EXTRACT_OPERAND (CSR, l);
546
547 if (!init_csr)
548 {
549 unsigned int i;
550 for (i = 0; i < 4096; i++)
551 riscv_csr_hash[i] = NULL;
552
553 /* Set to the newest privileged version. */
554 if (default_priv_spec == PRIV_SPEC_CLASS_NONE)
555 default_priv_spec = PRIV_SPEC_CLASS_DRAFT - 1;
556
557 #define DECLARE_CSR(name, num, class, define_version, abort_version) \
558 if (riscv_csr_hash[num] == NULL \
559 && ((define_version == PRIV_SPEC_CLASS_NONE \
560 && abort_version == PRIV_SPEC_CLASS_NONE) \
561 || (default_priv_spec >= define_version \
562 && default_priv_spec < abort_version))) \
563 riscv_csr_hash[num] = #name;
564 #define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \
565 DECLARE_CSR (name, num, class, define_version, abort_version)
566 #include "opcode/riscv-opc.h"
567 #undef DECLARE_CSR
568 }
569
570 if (riscv_csr_hash[csr] != NULL)
571 if (riscv_subset_supports (&riscv_rps_dis, "xtheadvector")
572 && (csr == CSR_VSTART
573 || csr == CSR_VXSAT
574 || csr == CSR_VXRM
575 || csr == CSR_VL
576 || csr == CSR_VTYPE
577 || csr == CSR_VLENB))
578 print (info->stream, dis_style_register, "%s",
579 concat ("th.", riscv_csr_hash[csr], NULL));
580 else
581 print (info->stream, dis_style_register, "%s",
582 riscv_csr_hash[csr]);
583 else
584 print (info->stream, dis_style_immediate, "0x%x", csr);
585 break;
586 }
587
588 case 'Y':
589 print (info->stream, dis_style_immediate, "0x%x",
590 EXTRACT_OPERAND (RNUM, l));
591 break;
592
593 case 'Z':
594 print (info->stream, dis_style_immediate, "%d", rs1);
595 break;
596
597 case 'W': /* Various operands for standard z extensions. */
598 switch (*++oparg)
599 {
600 case 'i':
601 switch (*++oparg)
602 {
603 case 'f':
604 print (info->stream, dis_style_address_offset, "%d",
605 (int) EXTRACT_STYPE_IMM (l));
606 break;
607 default:
608 goto undefined_modifier;
609 }
610 break;
611 case 'f':
612 switch (*++oparg)
613 {
614 case 'v':
615 if (riscv_fli_symval[rs1])
616 print (info->stream, dis_style_text, "%s",
617 riscv_fli_symval[rs1]);
618 else
619 print (info->stream, dis_style_immediate, "%a",
620 riscv_fli_numval[rs1]);
621 break;
622 default:
623 goto undefined_modifier;
624 }
625 break;
626 case 'c': /* Zcb extension 16 bits length instruction fields. */
627 switch (*++oparg)
628 {
629 case 'b':
630 print (info->stream, dis_style_immediate, "%d",
631 (int)EXTRACT_ZCB_BYTE_UIMM (l));
632 break;
633 case 'h':
634 print (info->stream, dis_style_immediate, "%d",
635 (int)EXTRACT_ZCB_HALFWORD_UIMM (l));
636 break;
637 default:
638 goto undefined_modifier;
639 }
640 break;
641 default:
642 goto undefined_modifier;
643 }
644 break;
645
646 case 'X': /* Vendor-specific operands. */
647 switch (*++oparg)
648 {
649 case 't': /* Vendor-specific (T-head) operands. */
650 {
651 size_t n;
652 size_t s;
653 bool sign;
654 switch (*++oparg)
655 {
656 case 'V':
657 ++oparg;
658 if (*oparg != 'c')
659 goto undefined_modifier;
660
661 int imm = (*oparg == 'b') ? EXTRACT_RVV_VB_IMM (l)
662 : EXTRACT_RVV_VC_IMM (l);
663 unsigned int imm_vediv = EXTRACT_OPERAND (XTHEADVEDIV, imm);
664 unsigned int imm_vlmul = EXTRACT_OPERAND (XTHEADVLMUL, imm);
665 unsigned int imm_vsew = EXTRACT_OPERAND (XTHEADVSEW, imm);
666 unsigned int imm_vtype_res
667 = EXTRACT_OPERAND (XTHEADVTYPE_RES, imm);
668 if (imm_vsew < ARRAY_SIZE (riscv_vsew)
669 && imm_vlmul < ARRAY_SIZE (riscv_th_vlen)
670 && imm_vediv < ARRAY_SIZE (riscv_th_vediv)
671 && ! imm_vtype_res)
672 print (info->stream, dis_style_text, "%s,%s,%s",
673 riscv_vsew[imm_vsew], riscv_th_vlen[imm_vlmul],
674 riscv_th_vediv[imm_vediv]);
675 else
676 print (info->stream, dis_style_immediate, "%d", imm);
677 break;
678 case 'l': /* Integer immediate, literal. */
679 oparg++;
680 while (*oparg && *oparg != ',')
681 {
682 print (info->stream, dis_style_immediate, "%c", *oparg);
683 oparg++;
684 }
685 oparg--;
686 break;
687 case 's': /* Integer immediate, 'XsN@S' ... N-bit signed immediate at bit S. */
688 sign = true;
689 goto print_imm;
690 case 'u': /* Integer immediate, 'XuN@S' ... N-bit unsigned immediate at bit S. */
691 sign = false;
692 goto print_imm;
693 print_imm:
694 n = strtol (oparg + 1, (char **)&oparg, 10);
695 if (*oparg != '@')
696 goto undefined_modifier;
697 s = strtol (oparg + 1, (char **)&oparg, 10);
698 oparg--;
699
700 if (!sign)
701 print (info->stream, dis_style_immediate, "%lu",
702 (unsigned long)EXTRACT_U_IMM (n, s, l));
703 else
704 print (info->stream, dis_style_immediate, "%li",
705 (signed long)EXTRACT_S_IMM (n, s, l));
706 break;
707 default:
708 goto undefined_modifier;
709 }
710 }
711 break;
712 case 'c': /* Vendor-specific (CORE-V) operands. */
713 switch (*++oparg)
714 {
715 case '2':
716 print (info->stream, dis_style_immediate, "%d",
717 ((int) EXTRACT_CV_IS2_UIMM5 (l)));
718 break;
719 case '3':
720 print (info->stream, dis_style_immediate, "%d",
721 ((int) EXTRACT_CV_IS3_UIMM5 (l)));
722 break;
723 default:
724 goto undefined_modifier;
725 }
726 break;
727 case 's': /* Vendor-specific (SiFive) operands. */
728 switch (*++oparg)
729 {
730 /* SiFive vector coprocessor interface. */
731 case 'd':
732 print (info->stream, dis_style_register, "0x%x",
733 (unsigned) EXTRACT_OPERAND (RD, l));
734 break;
735 case 't':
736 print (info->stream, dis_style_register, "0x%x",
737 (unsigned) EXTRACT_OPERAND (RS2, l));
738 break;
739 case 'O':
740 switch (*++oparg)
741 {
742 case '2':
743 print (info->stream, dis_style_register, "0x%x",
744 (unsigned) EXTRACT_OPERAND (XSO2, l));
745 break;
746 case '1':
747 print (info->stream, dis_style_register, "0x%x",
748 (unsigned) EXTRACT_OPERAND (XSO1, l));
749 break;
750 }
751 break;
752 }
753 break;
754 default:
755 goto undefined_modifier;
756 }
757 break;
758
759 default:
760 undefined_modifier:
761 /* xgettext:c-format */
762 print (info->stream, dis_style_text,
763 _("# internal error, undefined modifier (%c)"),
764 *opargStart);
765 return;
766 }
767 }
768 }
769
770 /* Print the RISC-V instruction at address MEMADDR in debugged memory,
771 on using INFO. Returns length of the instruction, in bytes.
772 BIGENDIAN must be 1 if this is big-endian code, 0 if
773 this is little-endian code. */
774
775 static int
riscv_disassemble_insn(bfd_vma memaddr,insn_t word,const bfd_byte * packet,disassemble_info * info)776 riscv_disassemble_insn (bfd_vma memaddr,
777 insn_t word,
778 const bfd_byte *packet,
779 disassemble_info *info)
780 {
781 const struct riscv_opcode *op;
782 static bool init = false;
783 static const struct riscv_opcode *riscv_hash[OP_MASK_OP + 1];
784 struct riscv_private_data *pd = info->private_data;
785 int insnlen, i;
786 bool printed;
787
788 #define OP_HASH_IDX(i) ((i) & (riscv_insn_length (i) == 2 ? 0x3 : OP_MASK_OP))
789
790 /* Build a hash table to shorten the search time. */
791 if (! init)
792 {
793 for (op = riscv_opcodes; op->name; op++)
794 if (!riscv_hash[OP_HASH_IDX (op->match)])
795 riscv_hash[OP_HASH_IDX (op->match)] = op;
796
797 init = true;
798 }
799
800 insnlen = riscv_insn_length (word);
801
802 /* RISC-V instructions are always little-endian. */
803 info->endian_code = BFD_ENDIAN_LITTLE;
804
805 info->bytes_per_chunk = insnlen % 4 == 0 ? 4 : 2;
806 info->bytes_per_line = 8;
807 /* We don't support constant pools, so this must be code. */
808 info->display_endian = info->endian_code;
809 info->insn_info_valid = 1;
810 info->branch_delay_insns = 0;
811 info->data_size = 0;
812 info->insn_type = dis_nonbranch;
813 info->target = 0;
814 info->target2 = 0;
815
816 op = riscv_hash[OP_HASH_IDX (word)];
817 if (op != NULL)
818 {
819 /* If XLEN is not known, get its value from the ELF class. */
820 if (info->mach == bfd_mach_riscv64)
821 xlen = 64;
822 else if (info->mach == bfd_mach_riscv32)
823 xlen = 32;
824 else if (info->section != NULL)
825 {
826 Elf_Internal_Ehdr *ehdr = elf_elfheader (info->section->owner);
827 xlen = ehdr->e_ident[EI_CLASS] == ELFCLASS64 ? 64 : 32;
828 }
829
830 /* If arch has the Zfinx extension, replace FPR with GPR. */
831 if (riscv_subset_supports (&riscv_rps_dis, "zfinx"))
832 riscv_fpr_names = riscv_gpr_names;
833 else
834 riscv_fpr_names = riscv_gpr_names == riscv_gpr_names_abi ?
835 riscv_fpr_names_abi : riscv_fpr_names_numeric;
836
837 for (; op->name; op++)
838 {
839 /* Ignore macro insns. */
840 if (op->pinfo == INSN_MACRO)
841 continue;
842 /* Does the opcode match? */
843 if (! (op->match_func) (op, word))
844 continue;
845 /* Is this a pseudo-instruction and may we print it as such? */
846 if (no_aliases && (op->pinfo & INSN_ALIAS))
847 continue;
848 /* Is this instruction restricted to a certain value of XLEN? */
849 if ((op->xlen_requirement != 0) && (op->xlen_requirement != xlen))
850 continue;
851 /* Is this instruction supported by the current architecture? */
852 if (!riscv_multi_subset_supports (&riscv_rps_dis, op->insn_class))
853 continue;
854
855 /* It's a match. */
856 (*info->fprintf_styled_func) (info->stream, dis_style_mnemonic,
857 "%s", op->name);
858 print_insn_args (op->args, word, memaddr, info);
859
860 /* Try to disassemble multi-instruction addressing sequences. */
861 if (pd->to_print_addr)
862 {
863 info->target = pd->print_addr;
864 (*info->fprintf_styled_func)
865 (info->stream, dis_style_comment_start, " # ");
866 (*info->print_address_func) (info->target, info);
867 pd->to_print_addr = false;
868 }
869
870 /* Finish filling out insn_info fields. */
871 switch (op->pinfo & INSN_TYPE)
872 {
873 case INSN_BRANCH:
874 info->insn_type = dis_branch;
875 break;
876 case INSN_CONDBRANCH:
877 info->insn_type = dis_condbranch;
878 break;
879 case INSN_JSR:
880 info->insn_type = dis_jsr;
881 break;
882 case INSN_DREF:
883 info->insn_type = dis_dref;
884 break;
885 default:
886 break;
887 }
888
889 if (op->pinfo & INSN_DATA_SIZE)
890 {
891 int size = ((op->pinfo & INSN_DATA_SIZE)
892 >> INSN_DATA_SIZE_SHIFT);
893 info->data_size = 1 << (size - 1);
894 }
895
896 return insnlen;
897 }
898 }
899
900 /* We did not find a match, so just print the instruction bits in
901 the shape of an assembler .insn directive. */
902 info->insn_type = dis_noninsn;
903 (*info->fprintf_styled_func)
904 (info->stream, dis_style_assembler_directive, ".insn");
905 (*info->fprintf_styled_func) (info->stream, dis_style_text, "\t");
906 (*info->fprintf_styled_func) (info->stream, dis_style_immediate,
907 "%d", insnlen);
908 (*info->fprintf_styled_func) (info->stream, dis_style_text, ", ");
909 (*info->fprintf_styled_func) (info->stream, dis_style_immediate, "0x");
910 for (i = insnlen, printed = false; i >= 2; )
911 {
912 i -= 2;
913 word = bfd_get_bits (packet + i, 16, false);
914 if (!word && !printed)
915 continue;
916
917 (*info->fprintf_styled_func) (info->stream, dis_style_immediate,
918 "%04x", (unsigned int) word);
919 printed = true;
920 }
921
922 return insnlen;
923 }
924
925 /* If we find the suitable mapping symbol update the STATE.
926 Otherwise, do nothing. */
927
928 static void
riscv_update_map_state(int n,enum riscv_seg_mstate * state,struct disassemble_info * info)929 riscv_update_map_state (int n,
930 enum riscv_seg_mstate *state,
931 struct disassemble_info *info)
932 {
933 const char *name;
934
935 /* If the symbol is in a different section, ignore it. */
936 if (info->section != NULL
937 && info->section != info->symtab[n]->section)
938 return;
939
940 name = bfd_asymbol_name(info->symtab[n]);
941 if (strcmp (name, "$x") == 0)
942 *state = MAP_INSN;
943 else if (strcmp (name, "$d") == 0)
944 *state = MAP_DATA;
945 else if (strncmp (name, "$xrv", 4) == 0)
946 {
947 *state = MAP_INSN;
948 riscv_release_subset_list (&riscv_subsets);
949
950 /* ISA mapping string may be numbered, suffixed with '.n'. Do not
951 consider this as part of the ISA string. */
952 char *suffix = strchr (name, '.');
953 if (suffix)
954 {
955 int suffix_index = (int)(suffix - name);
956 char *name_substr = xmalloc (suffix_index + 1);
957 strncpy (name_substr, name, suffix_index);
958 name_substr[suffix_index] = '\0';
959 riscv_parse_subset (&riscv_rps_dis, name_substr + 2);
960 free (name_substr);
961 }
962 else
963 riscv_parse_subset (&riscv_rps_dis, name + 2);
964 }
965 }
966
967 /* Return true if we find the suitable mapping symbol.
968 Otherwise, return false. */
969
970 static bool
riscv_is_valid_mapping_symbol(int n,struct disassemble_info * info)971 riscv_is_valid_mapping_symbol (int n,
972 struct disassemble_info *info)
973 {
974 const char *name;
975
976 /* If the symbol is in a different section, ignore it. */
977 if (info->section != NULL
978 && info->section != info->symtab[n]->section)
979 return false;
980
981 name = bfd_asymbol_name(info->symtab[n]);
982 return riscv_elf_is_mapping_symbols (name);
983 }
984
985 /* Check the sorted symbol table (sorted by the symbol value), find the
986 suitable mapping symbols. */
987
988 static enum riscv_seg_mstate
riscv_search_mapping_symbol(bfd_vma memaddr,struct disassemble_info * info)989 riscv_search_mapping_symbol (bfd_vma memaddr,
990 struct disassemble_info *info)
991 {
992 enum riscv_seg_mstate mstate;
993 bool from_last_map_symbol;
994 bool found = false;
995 int symbol = -1;
996 int n;
997
998 /* Return the last map state if the address is still within the range of the
999 last mapping symbol. */
1000 if (last_map_section == info->section
1001 && (memaddr < last_map_symbol_boundary))
1002 return last_map_state;
1003
1004 last_map_section = info->section;
1005
1006 /* Decide whether to print the data or instruction by default, in case
1007 we can not find the corresponding mapping symbols. */
1008 mstate = MAP_DATA;
1009 if ((info->section
1010 && info->section->flags & SEC_CODE)
1011 || !info->section)
1012 mstate = MAP_INSN;
1013
1014 if (info->symtab_size == 0
1015 || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
1016 return mstate;
1017
1018 /* Reset the last_map_symbol if we start to dump a new section. */
1019 if (memaddr <= 0)
1020 last_map_symbol = -1;
1021
1022 /* If the last stop offset is different from the current one, then
1023 don't use the last_map_symbol to search. We usually reset the
1024 info->stop_offset when handling a new section. */
1025 from_last_map_symbol = (last_map_symbol >= 0
1026 && info->stop_offset == last_stop_offset);
1027
1028 /* Start scanning at the start of the function, or wherever
1029 we finished last time. */
1030 n = info->symtab_pos + 1;
1031 if (from_last_map_symbol && n >= last_map_symbol)
1032 n = last_map_symbol;
1033
1034 /* Find the suitable mapping symbol to dump. */
1035 for (; n < info->symtab_size; n++)
1036 {
1037 bfd_vma addr = bfd_asymbol_value (info->symtab[n]);
1038 /* We have searched all possible symbols in the range. */
1039 if (addr > memaddr)
1040 break;
1041 if (riscv_is_valid_mapping_symbol (n, info))
1042 {
1043 symbol = n;
1044 found = true;
1045 /* Do not stop searching, in case there are some mapping
1046 symbols have the same value, but have different names.
1047 Use the last one. */
1048 }
1049 }
1050
1051 /* We can not find the suitable mapping symbol above. Therefore, we
1052 look forwards and try to find it again, but don't go past the start
1053 of the section. Otherwise a data section without mapping symbols
1054 can pick up a text mapping symbol of a preceeding section. */
1055 if (!found)
1056 {
1057 n = info->symtab_pos;
1058 if (from_last_map_symbol && n >= last_map_symbol)
1059 n = last_map_symbol;
1060
1061 for (; n >= 0; n--)
1062 {
1063 bfd_vma addr = bfd_asymbol_value (info->symtab[n]);
1064 /* We have searched all possible symbols in the range. */
1065 if (addr < (info->section ? info->section->vma : 0))
1066 break;
1067 /* Stop searching once we find the closed mapping symbol. */
1068 if (riscv_is_valid_mapping_symbol (n, info))
1069 {
1070 symbol = n;
1071 found = true;
1072 break;
1073 }
1074 }
1075 }
1076
1077 if (found)
1078 {
1079 riscv_update_map_state (symbol, &mstate, info);
1080
1081 /* Find the next mapping symbol to determine the boundary of this mapping
1082 symbol. */
1083
1084 bool found_next = false;
1085 /* Try to found next mapping symbol. */
1086 for (n = symbol + 1; n < info->symtab_size; n++)
1087 {
1088 if (info->symtab[symbol]->section != info->symtab[n]->section)
1089 continue;
1090
1091 bfd_vma addr = bfd_asymbol_value (info->symtab[n]);
1092 const char *sym_name = bfd_asymbol_name(info->symtab[n]);
1093 if (sym_name[0] == '$' && (sym_name[1] == 'x' || sym_name[1] == 'd'))
1094 {
1095 /* The next mapping symbol has been found, and it represents the
1096 boundary of this mapping symbol. */
1097 found_next = true;
1098 last_map_symbol_boundary = addr;
1099 break;
1100 }
1101 }
1102
1103 /* No further mapping symbol has been found, indicating that the boundary
1104 of the current mapping symbol is the end of this section. */
1105 if (!found_next)
1106 last_map_symbol_boundary = info->section->vma + info->section->size;
1107 }
1108
1109 /* Save the information for next use. */
1110 last_map_symbol = symbol;
1111 last_stop_offset = info->stop_offset;
1112
1113 return mstate;
1114 }
1115
1116 /* Decide which data size we should print. */
1117
1118 static bfd_vma
riscv_data_length(bfd_vma memaddr,disassemble_info * info)1119 riscv_data_length (bfd_vma memaddr,
1120 disassemble_info *info)
1121 {
1122 bfd_vma length;
1123 bool found = false;
1124
1125 length = 4;
1126 if (info->symtab_size != 0
1127 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour
1128 && last_map_symbol >= 0)
1129 {
1130 int n;
1131 enum riscv_seg_mstate m = MAP_NONE;
1132 for (n = last_map_symbol + 1; n < info->symtab_size; n++)
1133 {
1134 bfd_vma addr = bfd_asymbol_value (info->symtab[n]);
1135 if (addr > memaddr
1136 && riscv_is_valid_mapping_symbol (n, info))
1137 {
1138 if (addr - memaddr < length)
1139 length = addr - memaddr;
1140 found = true;
1141 riscv_update_map_state (n, &m, info);
1142 break;
1143 }
1144 }
1145 }
1146 if (!found)
1147 {
1148 /* Do not set the length which exceeds the section size. */
1149 bfd_vma offset = info->section->vma + info->section->size;
1150 offset -= memaddr;
1151 length = (offset < length) ? offset : length;
1152 }
1153 length = length == 3 ? 2 : length;
1154 return length;
1155 }
1156
1157 /* Dump the data contents. */
1158
1159 static int
riscv_disassemble_data(bfd_vma memaddr ATTRIBUTE_UNUSED,insn_t data,const bfd_byte * packet ATTRIBUTE_UNUSED,disassemble_info * info)1160 riscv_disassemble_data (bfd_vma memaddr ATTRIBUTE_UNUSED,
1161 insn_t data,
1162 const bfd_byte *packet ATTRIBUTE_UNUSED,
1163 disassemble_info *info)
1164 {
1165 info->display_endian = info->endian;
1166
1167 switch (info->bytes_per_chunk)
1168 {
1169 case 1:
1170 info->bytes_per_line = 6;
1171 (*info->fprintf_styled_func)
1172 (info->stream, dis_style_assembler_directive, ".byte");
1173 (*info->fprintf_styled_func) (info->stream, dis_style_text, "\t");
1174 (*info->fprintf_styled_func) (info->stream, dis_style_immediate,
1175 "0x%02x", (unsigned)data);
1176 break;
1177 case 2:
1178 info->bytes_per_line = 8;
1179 (*info->fprintf_styled_func)
1180 (info->stream, dis_style_assembler_directive, ".short");
1181 (*info->fprintf_styled_func) (info->stream, dis_style_text, "\t");
1182 (*info->fprintf_styled_func)
1183 (info->stream, dis_style_immediate, "0x%04x", (unsigned) data);
1184 break;
1185 case 4:
1186 info->bytes_per_line = 8;
1187 (*info->fprintf_styled_func)
1188 (info->stream, dis_style_assembler_directive, ".word");
1189 (*info->fprintf_styled_func) (info->stream, dis_style_text, "\t");
1190 (*info->fprintf_styled_func)
1191 (info->stream, dis_style_immediate, "0x%08lx",
1192 (unsigned long) data);
1193 break;
1194 case 8:
1195 info->bytes_per_line = 8;
1196 (*info->fprintf_styled_func)
1197 (info->stream, dis_style_assembler_directive, ".dword");
1198 (*info->fprintf_styled_func) (info->stream, dis_style_text, "\t");
1199 (*info->fprintf_styled_func)
1200 (info->stream, dis_style_immediate, "0x%016llx",
1201 (unsigned long long) data);
1202 break;
1203 default:
1204 abort ();
1205 }
1206 return info->bytes_per_chunk;
1207 }
1208
1209 static bool
riscv_init_disasm_info(struct disassemble_info * info)1210 riscv_init_disasm_info (struct disassemble_info *info)
1211 {
1212 int i;
1213
1214 struct riscv_private_data *pd =
1215 xcalloc (1, sizeof (struct riscv_private_data));
1216 pd->gp = 0;
1217 pd->print_addr = 0;
1218 for (i = 0; i < (int) ARRAY_SIZE (pd->hi_addr); i++)
1219 pd->hi_addr[i] = -1;
1220 pd->to_print_addr = false;
1221 pd->has_gp = false;
1222
1223 for (i = 0; i < info->symtab_size; i++)
1224 {
1225 asymbol *sym = info->symtab[i];
1226 if (strcmp (bfd_asymbol_name (sym), RISCV_GP_SYMBOL) == 0)
1227 {
1228 pd->gp = bfd_asymbol_value (sym);
1229 pd->has_gp = true;
1230 }
1231 }
1232
1233 info->private_data = pd;
1234 return true;
1235 }
1236
1237 int
print_insn_riscv(bfd_vma memaddr,struct disassemble_info * info)1238 print_insn_riscv (bfd_vma memaddr, struct disassemble_info *info)
1239 {
1240 bfd_byte packet[RISCV_MAX_INSN_LEN];
1241 insn_t insn = 0;
1242 bfd_vma dump_size;
1243 int status;
1244 enum riscv_seg_mstate mstate;
1245 int (*riscv_disassembler) (bfd_vma, insn_t, const bfd_byte *,
1246 struct disassemble_info *);
1247
1248 if (info->disassembler_options != NULL)
1249 {
1250 parse_riscv_dis_options (info->disassembler_options);
1251 /* Avoid repeatedly parsing the options. */
1252 info->disassembler_options = NULL;
1253 }
1254 else if (riscv_gpr_names == NULL)
1255 set_default_riscv_dis_options ();
1256
1257 if (info->private_data == NULL && !riscv_init_disasm_info (info))
1258 return -1;
1259
1260 mstate = riscv_search_mapping_symbol (memaddr, info);
1261 /* Save the last mapping state. */
1262 last_map_state = mstate;
1263
1264 /* Set the size to dump. */
1265 if (mstate == MAP_DATA
1266 && (info->flags & DISASSEMBLE_DATA) == 0)
1267 {
1268 dump_size = riscv_data_length (memaddr, info);
1269 info->bytes_per_chunk = dump_size;
1270 riscv_disassembler = riscv_disassemble_data;
1271 }
1272 else
1273 {
1274 /* Get the first 2-bytes to check the lenghth of instruction. */
1275 status = (*info->read_memory_func) (memaddr, packet, 2, info);
1276 if (status != 0)
1277 {
1278 (*info->memory_error_func) (status, memaddr, info);
1279 return -1;
1280 }
1281 insn = (insn_t) bfd_getl16 (packet);
1282 dump_size = riscv_insn_length (insn);
1283 riscv_disassembler = riscv_disassemble_insn;
1284 }
1285
1286 /* Fetch the instruction to dump. */
1287 status = (*info->read_memory_func) (memaddr, packet, dump_size, info);
1288 if (status != 0)
1289 {
1290 (*info->memory_error_func) (status, memaddr, info);
1291 return -1;
1292 }
1293 insn = (insn_t) bfd_get_bits (packet, dump_size * 8, false);
1294
1295 return (*riscv_disassembler) (memaddr, insn, packet, info);
1296 }
1297
1298 disassembler_ftype
riscv_get_disassembler(bfd * abfd)1299 riscv_get_disassembler (bfd *abfd)
1300 {
1301 const char *default_arch = "rv64gc";
1302
1303 if (abfd && bfd_get_flavour (abfd) == bfd_target_elf_flavour)
1304 {
1305 const char *sec_name = get_elf_backend_data (abfd)->obj_attrs_section;
1306 if (bfd_get_section_by_name (abfd, sec_name) != NULL)
1307 {
1308 obj_attribute *attr = elf_known_obj_attributes_proc (abfd);
1309 unsigned int Tag_a = Tag_RISCV_priv_spec;
1310 unsigned int Tag_b = Tag_RISCV_priv_spec_minor;
1311 unsigned int Tag_c = Tag_RISCV_priv_spec_revision;
1312 riscv_get_priv_spec_class_from_numbers (attr[Tag_a].i,
1313 attr[Tag_b].i,
1314 attr[Tag_c].i,
1315 &default_priv_spec);
1316 default_arch = attr[Tag_RISCV_arch].s;
1317 }
1318 }
1319
1320 riscv_release_subset_list (&riscv_subsets);
1321 riscv_parse_subset (&riscv_rps_dis, default_arch);
1322 return print_insn_riscv;
1323 }
1324
1325 /* Prevent use of the fake labels that are generated as part of the DWARF
1326 and for relaxable relocations in the assembler. */
1327
1328 bool
riscv_symbol_is_valid(asymbol * sym,struct disassemble_info * info ATTRIBUTE_UNUSED)1329 riscv_symbol_is_valid (asymbol * sym,
1330 struct disassemble_info * info ATTRIBUTE_UNUSED)
1331 {
1332 const char * name;
1333
1334 if (sym == NULL)
1335 return false;
1336
1337 name = bfd_asymbol_name (sym);
1338
1339 return (strcmp (name, RISCV_FAKE_LABEL_NAME) != 0
1340 && !riscv_elf_is_mapping_symbols (name));
1341 }
1342
1343
1344 /* Indices into option argument vector for options accepting an argument.
1345 Use RISCV_OPTION_ARG_NONE for options accepting no argument. */
1346
1347 typedef enum
1348 {
1349 RISCV_OPTION_ARG_NONE = -1,
1350 RISCV_OPTION_ARG_PRIV_SPEC,
1351
1352 RISCV_OPTION_ARG_COUNT
1353 } riscv_option_arg_t;
1354
1355 /* Valid RISCV disassembler options. */
1356
1357 static struct
1358 {
1359 const char *name;
1360 const char *description;
1361 riscv_option_arg_t arg;
1362 } riscv_options[] =
1363 {
1364 { "numeric",
1365 N_("Print numeric register names, rather than ABI names."),
1366 RISCV_OPTION_ARG_NONE },
1367 { "no-aliases",
1368 N_("Disassemble only into canonical instructions."),
1369 RISCV_OPTION_ARG_NONE },
1370 { "priv-spec=",
1371 N_("Print the CSR according to the chosen privilege spec."),
1372 RISCV_OPTION_ARG_PRIV_SPEC }
1373 };
1374
1375 /* Build the structure representing valid RISCV disassembler options.
1376 This is done dynamically for maintenance ease purpose; a static
1377 initializer would be unreadable. */
1378
1379 const disasm_options_and_args_t *
disassembler_options_riscv(void)1380 disassembler_options_riscv (void)
1381 {
1382 static disasm_options_and_args_t *opts_and_args;
1383
1384 if (opts_and_args == NULL)
1385 {
1386 size_t num_options = ARRAY_SIZE (riscv_options);
1387 size_t num_args = RISCV_OPTION_ARG_COUNT;
1388 disasm_option_arg_t *args;
1389 disasm_options_t *opts;
1390 size_t i, priv_spec_count;
1391
1392 args = XNEWVEC (disasm_option_arg_t, num_args + 1);
1393
1394 args[RISCV_OPTION_ARG_PRIV_SPEC].name = "SPEC";
1395 priv_spec_count = PRIV_SPEC_CLASS_DRAFT - PRIV_SPEC_CLASS_NONE - 1;
1396 args[RISCV_OPTION_ARG_PRIV_SPEC].values
1397 = XNEWVEC (const char *, priv_spec_count + 1);
1398 for (i = 0; i < priv_spec_count; i++)
1399 args[RISCV_OPTION_ARG_PRIV_SPEC].values[i]
1400 = riscv_priv_specs[i].name;
1401 /* The array we return must be NULL terminated. */
1402 args[RISCV_OPTION_ARG_PRIV_SPEC].values[i] = NULL;
1403
1404 /* The array we return must be NULL terminated. */
1405 args[num_args].name = NULL;
1406 args[num_args].values = NULL;
1407
1408 opts_and_args = XNEW (disasm_options_and_args_t);
1409 opts_and_args->args = args;
1410
1411 opts = &opts_and_args->options;
1412 opts->name = XNEWVEC (const char *, num_options + 1);
1413 opts->description = XNEWVEC (const char *, num_options + 1);
1414 opts->arg = XNEWVEC (const disasm_option_arg_t *, num_options + 1);
1415 for (i = 0; i < num_options; i++)
1416 {
1417 opts->name[i] = riscv_options[i].name;
1418 opts->description[i] = _(riscv_options[i].description);
1419 if (riscv_options[i].arg != RISCV_OPTION_ARG_NONE)
1420 opts->arg[i] = &args[riscv_options[i].arg];
1421 else
1422 opts->arg[i] = NULL;
1423 }
1424 /* The array we return must be NULL terminated. */
1425 opts->name[i] = NULL;
1426 opts->description[i] = NULL;
1427 opts->arg[i] = NULL;
1428 }
1429
1430 return opts_and_args;
1431 }
1432
1433 void
print_riscv_disassembler_options(FILE * stream)1434 print_riscv_disassembler_options (FILE *stream)
1435 {
1436 const disasm_options_and_args_t *opts_and_args;
1437 const disasm_option_arg_t *args;
1438 const disasm_options_t *opts;
1439 size_t max_len = 0;
1440 size_t i;
1441 size_t j;
1442
1443 opts_and_args = disassembler_options_riscv ();
1444 opts = &opts_and_args->options;
1445 args = opts_and_args->args;
1446
1447 fprintf (stream, _("\n\
1448 The following RISC-V specific disassembler options are supported for use\n\
1449 with the -M switch (multiple options should be separated by commas):\n"));
1450 fprintf (stream, "\n");
1451
1452 /* Compute the length of the longest option name. */
1453 for (i = 0; opts->name[i] != NULL; i++)
1454 {
1455 size_t len = strlen (opts->name[i]);
1456
1457 if (opts->arg[i] != NULL)
1458 len += strlen (opts->arg[i]->name);
1459 if (max_len < len)
1460 max_len = len;
1461 }
1462
1463 for (i = 0, max_len++; opts->name[i] != NULL; i++)
1464 {
1465 fprintf (stream, " %s", opts->name[i]);
1466 if (opts->arg[i] != NULL)
1467 fprintf (stream, "%s", opts->arg[i]->name);
1468 if (opts->description[i] != NULL)
1469 {
1470 size_t len = strlen (opts->name[i]);
1471
1472 if (opts->arg != NULL && opts->arg[i] != NULL)
1473 len += strlen (opts->arg[i]->name);
1474 fprintf (stream, "%*c %s", (int) (max_len - len), ' ',
1475 opts->description[i]);
1476 }
1477 fprintf (stream, "\n");
1478 }
1479
1480 for (i = 0; args[i].name != NULL; i++)
1481 {
1482 if (args[i].values == NULL)
1483 continue;
1484 fprintf (stream, _("\n\
1485 For the options above, the following values are supported for \"%s\":\n "),
1486 args[i].name);
1487 for (j = 0; args[i].values[j] != NULL; j++)
1488 fprintf (stream, " %s", args[i].values[j]);
1489 fprintf (stream, _("\n"));
1490 }
1491
1492 fprintf (stream, _("\n"));
1493 }
1494
disassemble_free_riscv(struct disassemble_info * info ATTRIBUTE_UNUSED)1495 void disassemble_free_riscv (struct disassemble_info *info ATTRIBUTE_UNUSED)
1496 {
1497 riscv_release_subset_list (&riscv_subsets);
1498 }
1499