1 /* SPDX-License-Identifier: BSD-3-Clause
2 *
3 * Copyright(c) 2019-2021 Xilinx, Inc.
4 * Copyright(c) 2009-2019 Solarflare Communications Inc.
5 */
6
7 #include "efx.h"
8 #include "efx_impl.h"
9
10 #if EFSYS_OPT_SIENA
11
12 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
13
14 __checkReturn efx_rc_t
siena_nvram_partn_size(__in efx_nic_t * enp,__in uint32_t partn,__out size_t * sizep)15 siena_nvram_partn_size(
16 __in efx_nic_t *enp,
17 __in uint32_t partn,
18 __out size_t *sizep)
19 {
20 efx_rc_t rc;
21 efx_nvram_info_t eni = { 0 };
22
23 if ((1 << partn) & ~enp->en_u.siena.enu_partn_mask) {
24 rc = ENOTSUP;
25 goto fail1;
26 }
27
28 if ((rc = efx_mcdi_nvram_info(enp, partn, &eni)) != 0)
29 goto fail2;
30
31 *sizep = eni.eni_partn_size;
32
33 return (0);
34
35 fail2:
36 EFSYS_PROBE(fail2);
37 fail1:
38 EFSYS_PROBE1(fail1, efx_rc_t, rc);
39
40 return (rc);
41 }
42
43 __checkReturn efx_rc_t
siena_nvram_partn_info(__in efx_nic_t * enp,__in uint32_t partn,__out efx_nvram_info_t * enip)44 siena_nvram_partn_info(
45 __in efx_nic_t *enp,
46 __in uint32_t partn,
47 __out efx_nvram_info_t * enip)
48 {
49 efx_rc_t rc;
50
51 if ((rc = efx_mcdi_nvram_info(enp, partn, enip)) != 0)
52 goto fail1;
53
54 if (enip->eni_write_size == 0)
55 enip->eni_write_size = SIENA_NVRAM_CHUNK;
56
57 return (0);
58
59 fail1:
60 EFSYS_PROBE1(fail1, efx_rc_t, rc);
61
62 return (rc);
63 }
64
65
66 __checkReturn efx_rc_t
siena_nvram_partn_lock(__in efx_nic_t * enp,__in uint32_t partn)67 siena_nvram_partn_lock(
68 __in efx_nic_t *enp,
69 __in uint32_t partn)
70 {
71 efx_rc_t rc;
72
73 if ((rc = efx_mcdi_nvram_update_start(enp, partn)) != 0) {
74 goto fail1;
75 }
76
77 return (0);
78
79 fail1:
80 EFSYS_PROBE1(fail1, efx_rc_t, rc);
81
82 return (rc);
83 }
84
85 __checkReturn efx_rc_t
siena_nvram_partn_read(__in efx_nic_t * enp,__in uint32_t partn,__in unsigned int offset,__out_bcount (size)caddr_t data,__in size_t size)86 siena_nvram_partn_read(
87 __in efx_nic_t *enp,
88 __in uint32_t partn,
89 __in unsigned int offset,
90 __out_bcount(size) caddr_t data,
91 __in size_t size)
92 {
93 size_t chunk;
94 efx_rc_t rc;
95
96 while (size > 0) {
97 chunk = MIN(size, SIENA_NVRAM_CHUNK);
98
99 if ((rc = efx_mcdi_nvram_read(enp, partn, offset, data, chunk,
100 MC_CMD_NVRAM_READ_IN_V2_DEFAULT)) != 0) {
101 goto fail1;
102 }
103
104 size -= chunk;
105 data += chunk;
106 offset += chunk;
107 }
108
109 return (0);
110
111 fail1:
112 EFSYS_PROBE1(fail1, efx_rc_t, rc);
113
114 return (rc);
115 }
116
117 __checkReturn efx_rc_t
siena_nvram_partn_erase(__in efx_nic_t * enp,__in uint32_t partn,__in unsigned int offset,__in size_t size)118 siena_nvram_partn_erase(
119 __in efx_nic_t *enp,
120 __in uint32_t partn,
121 __in unsigned int offset,
122 __in size_t size)
123 {
124 efx_rc_t rc;
125
126 if ((rc = efx_mcdi_nvram_erase(enp, partn, offset, size)) != 0) {
127 goto fail1;
128 }
129
130 return (0);
131
132 fail1:
133 EFSYS_PROBE1(fail1, efx_rc_t, rc);
134
135 return (rc);
136 }
137
138 __checkReturn efx_rc_t
siena_nvram_partn_write(__in efx_nic_t * enp,__in uint32_t partn,__in unsigned int offset,__out_bcount (size)caddr_t data,__in size_t size)139 siena_nvram_partn_write(
140 __in efx_nic_t *enp,
141 __in uint32_t partn,
142 __in unsigned int offset,
143 __out_bcount(size) caddr_t data,
144 __in size_t size)
145 {
146 size_t chunk;
147 efx_rc_t rc;
148
149 while (size > 0) {
150 chunk = MIN(size, SIENA_NVRAM_CHUNK);
151
152 if ((rc = efx_mcdi_nvram_write(enp, partn, offset,
153 data, chunk)) != 0) {
154 goto fail1;
155 }
156
157 size -= chunk;
158 data += chunk;
159 offset += chunk;
160 }
161
162 return (0);
163
164 fail1:
165 EFSYS_PROBE1(fail1, efx_rc_t, rc);
166
167 return (rc);
168 }
169
170 __checkReturn efx_rc_t
siena_nvram_partn_unlock(__in efx_nic_t * enp,__in uint32_t partn,__out_opt uint32_t * verify_resultp)171 siena_nvram_partn_unlock(
172 __in efx_nic_t *enp,
173 __in uint32_t partn,
174 __out_opt uint32_t *verify_resultp)
175 {
176 boolean_t reboot;
177 uint32_t flags = 0;
178 efx_rc_t rc;
179
180 /*
181 * Reboot into the new image only for PHYs. The driver has to
182 * explicitly cope with an MC reboot after a firmware update.
183 */
184 reboot = (partn == MC_CMD_NVRAM_TYPE_PHY_PORT0 ||
185 partn == MC_CMD_NVRAM_TYPE_PHY_PORT1 ||
186 partn == MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO);
187
188 rc = efx_mcdi_nvram_update_finish(enp, partn, reboot, flags,
189 verify_resultp);
190 if (rc != 0)
191 goto fail1;
192
193 return (0);
194
195 fail1:
196 EFSYS_PROBE1(fail1, efx_rc_t, rc);
197
198 return (rc);
199 }
200
201 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
202
203 #if EFSYS_OPT_NVRAM
204
205 typedef struct siena_parttbl_entry_s {
206 unsigned int partn;
207 unsigned int port;
208 efx_nvram_type_t nvtype;
209 } siena_parttbl_entry_t;
210
211 static siena_parttbl_entry_t siena_parttbl[] = {
212 {MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO, 1, EFX_NVRAM_NULLPHY},
213 {MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO, 2, EFX_NVRAM_NULLPHY},
214 {MC_CMD_NVRAM_TYPE_MC_FW, 1, EFX_NVRAM_MC_FIRMWARE},
215 {MC_CMD_NVRAM_TYPE_MC_FW, 2, EFX_NVRAM_MC_FIRMWARE},
216 {MC_CMD_NVRAM_TYPE_MC_FW_BACKUP, 1, EFX_NVRAM_MC_GOLDEN},
217 {MC_CMD_NVRAM_TYPE_MC_FW_BACKUP, 2, EFX_NVRAM_MC_GOLDEN},
218 {MC_CMD_NVRAM_TYPE_EXP_ROM, 1, EFX_NVRAM_BOOTROM},
219 {MC_CMD_NVRAM_TYPE_EXP_ROM, 2, EFX_NVRAM_BOOTROM},
220 {MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0, 1, EFX_NVRAM_BOOTROM_CFG},
221 {MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1, 2, EFX_NVRAM_BOOTROM_CFG},
222 {MC_CMD_NVRAM_TYPE_PHY_PORT0, 1, EFX_NVRAM_PHY},
223 {MC_CMD_NVRAM_TYPE_PHY_PORT1, 2, EFX_NVRAM_PHY},
224 {MC_CMD_NVRAM_TYPE_FPGA, 1, EFX_NVRAM_FPGA},
225 {MC_CMD_NVRAM_TYPE_FPGA, 2, EFX_NVRAM_FPGA},
226 {MC_CMD_NVRAM_TYPE_FPGA_BACKUP, 1, EFX_NVRAM_FPGA_BACKUP},
227 {MC_CMD_NVRAM_TYPE_FPGA_BACKUP, 2, EFX_NVRAM_FPGA_BACKUP},
228 {MC_CMD_NVRAM_TYPE_FC_FW, 1, EFX_NVRAM_FCFW},
229 {MC_CMD_NVRAM_TYPE_FC_FW, 2, EFX_NVRAM_FCFW},
230 {MC_CMD_NVRAM_TYPE_CPLD, 1, EFX_NVRAM_CPLD},
231 {MC_CMD_NVRAM_TYPE_CPLD, 2, EFX_NVRAM_CPLD},
232 {MC_CMD_NVRAM_TYPE_LICENSE, 1, EFX_NVRAM_LICENSE},
233 {MC_CMD_NVRAM_TYPE_LICENSE, 2, EFX_NVRAM_LICENSE}
234 };
235
236 __checkReturn efx_rc_t
siena_nvram_type_to_partn(__in efx_nic_t * enp,__in efx_nvram_type_t type,__out uint32_t * partnp)237 siena_nvram_type_to_partn(
238 __in efx_nic_t *enp,
239 __in efx_nvram_type_t type,
240 __out uint32_t *partnp)
241 {
242 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
243 unsigned int i;
244
245 EFSYS_ASSERT3U(type, !=, EFX_NVRAM_INVALID);
246 EFSYS_ASSERT3U(type, <, EFX_NVRAM_NTYPES);
247 EFSYS_ASSERT(partnp != NULL);
248
249 for (i = 0; i < EFX_ARRAY_SIZE(siena_parttbl); i++) {
250 siena_parttbl_entry_t *entry = &siena_parttbl[i];
251
252 if (entry->port == emip->emi_port && entry->nvtype == type) {
253 *partnp = entry->partn;
254 return (0);
255 }
256 }
257
258 return (ENOTSUP);
259 }
260
261
262 #if EFSYS_OPT_DIAG
263
264 __checkReturn efx_rc_t
siena_nvram_test(__in efx_nic_t * enp)265 siena_nvram_test(
266 __in efx_nic_t *enp)
267 {
268 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
269 siena_parttbl_entry_t *entry;
270 unsigned int i;
271 efx_rc_t rc;
272
273 /*
274 * Iterate over the list of supported partition types
275 * applicable to *this* port
276 */
277 for (i = 0; i < EFX_ARRAY_SIZE(siena_parttbl); i++) {
278 entry = &siena_parttbl[i];
279
280 if (entry->port != emip->emi_port ||
281 !(enp->en_u.siena.enu_partn_mask & (1 << entry->partn)))
282 continue;
283
284 if ((rc = efx_mcdi_nvram_test(enp, entry->partn)) != 0) {
285 goto fail1;
286 }
287 }
288
289 return (0);
290
291 fail1:
292 EFSYS_PROBE1(fail1, efx_rc_t, rc);
293
294 return (rc);
295 }
296
297 #endif /* EFSYS_OPT_DIAG */
298
299
300 #define SIENA_DYNAMIC_CFG_SIZE(_nitems) \
301 (sizeof (siena_mc_dynamic_config_hdr_t) + ((_nitems) * \
302 sizeof (((siena_mc_dynamic_config_hdr_t *)NULL)->fw_version[0])))
303
304 __checkReturn efx_rc_t
siena_nvram_get_dynamic_cfg(__in efx_nic_t * enp,__in uint32_t partn,__in boolean_t vpd,__out siena_mc_dynamic_config_hdr_t ** dcfgp,__out size_t * sizep)305 siena_nvram_get_dynamic_cfg(
306 __in efx_nic_t *enp,
307 __in uint32_t partn,
308 __in boolean_t vpd,
309 __out siena_mc_dynamic_config_hdr_t **dcfgp,
310 __out size_t *sizep)
311 {
312 siena_mc_dynamic_config_hdr_t *dcfg = NULL;
313 size_t size;
314 uint8_t cksum;
315 unsigned int vpd_offset;
316 unsigned int vpd_length;
317 unsigned int hdr_length;
318 unsigned int nversions;
319 unsigned int pos;
320 unsigned int region;
321 efx_rc_t rc;
322
323 EFSYS_ASSERT(partn == MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0 ||
324 partn == MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1);
325
326 /*
327 * Allocate sufficient memory for the entire dynamiccfg area, even
328 * if we're not actually going to read in the VPD.
329 */
330 if ((rc = siena_nvram_partn_size(enp, partn, &size)) != 0)
331 goto fail1;
332
333 if (size < SIENA_NVRAM_CHUNK) {
334 rc = EINVAL;
335 goto fail2;
336 }
337
338 EFSYS_KMEM_ALLOC(enp->en_esip, size, dcfg);
339 if (dcfg == NULL) {
340 rc = ENOMEM;
341 goto fail3;
342 }
343
344 if ((rc = siena_nvram_partn_read(enp, partn, 0,
345 (caddr_t)dcfg, SIENA_NVRAM_CHUNK)) != 0)
346 goto fail4;
347
348 /* Verify the magic */
349 if (EFX_DWORD_FIELD(dcfg->magic, EFX_DWORD_0)
350 != SIENA_MC_DYNAMIC_CONFIG_MAGIC)
351 goto invalid1;
352
353 /* All future versions of the structure must be backwards compatible */
354 EFX_STATIC_ASSERT(SIENA_MC_DYNAMIC_CONFIG_VERSION == 0);
355
356 hdr_length = EFX_WORD_FIELD(dcfg->length, EFX_WORD_0);
357 nversions = EFX_DWORD_FIELD(dcfg->num_fw_version_items, EFX_DWORD_0);
358 vpd_offset = EFX_DWORD_FIELD(dcfg->dynamic_vpd_offset, EFX_DWORD_0);
359 vpd_length = EFX_DWORD_FIELD(dcfg->dynamic_vpd_length, EFX_DWORD_0);
360
361 /* Verify the hdr doesn't overflow the partn size */
362 if (hdr_length > size || vpd_offset > size || vpd_length > size ||
363 vpd_length + vpd_offset > size)
364 goto invalid2;
365
366 /* Verify the header has room for all it's versions */
367 if (hdr_length < SIENA_DYNAMIC_CFG_SIZE(0) ||
368 hdr_length < SIENA_DYNAMIC_CFG_SIZE(nversions))
369 goto invalid3;
370
371 /*
372 * Read the remaining portion of the dcfg, either including
373 * the whole of VPD (there is no vpd length in this structure,
374 * so we have to parse each tag), or just the dcfg header itself
375 */
376 region = vpd ? vpd_offset + vpd_length : hdr_length;
377 if (region > SIENA_NVRAM_CHUNK) {
378 if ((rc = siena_nvram_partn_read(enp, partn, SIENA_NVRAM_CHUNK,
379 (caddr_t)dcfg + SIENA_NVRAM_CHUNK,
380 region - SIENA_NVRAM_CHUNK)) != 0)
381 goto fail5;
382 }
383
384 /* Verify checksum */
385 cksum = 0;
386 for (pos = 0; pos < hdr_length; pos++)
387 cksum += ((uint8_t *)dcfg)[pos];
388 if (cksum != 0)
389 goto invalid4;
390
391 goto done;
392
393 invalid4:
394 EFSYS_PROBE(invalid4);
395 invalid3:
396 EFSYS_PROBE(invalid3);
397 invalid2:
398 EFSYS_PROBE(invalid2);
399 invalid1:
400 EFSYS_PROBE(invalid1);
401
402 /*
403 * Construct a new "null" dcfg, with an empty version vector,
404 * and an empty VPD chunk trailing. This has the neat side effect
405 * of testing the exception paths in the write path.
406 */
407 EFX_POPULATE_DWORD_1(dcfg->magic,
408 EFX_DWORD_0, SIENA_MC_DYNAMIC_CONFIG_MAGIC);
409 EFX_POPULATE_WORD_1(dcfg->length, EFX_WORD_0, sizeof (*dcfg));
410 EFX_POPULATE_BYTE_1(dcfg->version, EFX_BYTE_0,
411 SIENA_MC_DYNAMIC_CONFIG_VERSION);
412 EFX_POPULATE_DWORD_1(dcfg->dynamic_vpd_offset,
413 EFX_DWORD_0, sizeof (*dcfg));
414 EFX_POPULATE_DWORD_1(dcfg->dynamic_vpd_length, EFX_DWORD_0, 0);
415 EFX_POPULATE_DWORD_1(dcfg->num_fw_version_items, EFX_DWORD_0, 0);
416
417 done:
418 *dcfgp = dcfg;
419 *sizep = size;
420
421 return (0);
422
423 fail5:
424 EFSYS_PROBE(fail5);
425 fail4:
426 EFSYS_PROBE(fail4);
427
428 EFSYS_KMEM_FREE(enp->en_esip, size, dcfg);
429
430 fail3:
431 EFSYS_PROBE(fail3);
432 fail2:
433 EFSYS_PROBE(fail2);
434 fail1:
435 EFSYS_PROBE1(fail1, efx_rc_t, rc);
436
437 return (rc);
438 }
439
440 __checkReturn efx_rc_t
siena_nvram_get_subtype(__in efx_nic_t * enp,__in uint32_t partn,__out uint32_t * subtypep)441 siena_nvram_get_subtype(
442 __in efx_nic_t *enp,
443 __in uint32_t partn,
444 __out uint32_t *subtypep)
445 {
446 efx_mcdi_req_t req;
447 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_BOARD_CFG_IN_LEN,
448 MC_CMD_GET_BOARD_CFG_OUT_LENMAX);
449 efx_word_t *fw_list;
450 efx_rc_t rc;
451
452 req.emr_cmd = MC_CMD_GET_BOARD_CFG;
453 req.emr_in_buf = payload;
454 req.emr_in_length = MC_CMD_GET_BOARD_CFG_IN_LEN;
455 req.emr_out_buf = payload;
456 req.emr_out_length = MC_CMD_GET_BOARD_CFG_OUT_LENMAX;
457
458 efx_mcdi_execute(enp, &req);
459
460 if (req.emr_rc != 0) {
461 rc = req.emr_rc;
462 goto fail1;
463 }
464
465 if (req.emr_out_length_used < MC_CMD_GET_BOARD_CFG_OUT_LENMIN) {
466 rc = EMSGSIZE;
467 goto fail2;
468 }
469
470 if (req.emr_out_length_used <
471 MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST +
472 (partn + 1) * sizeof (efx_word_t)) {
473 rc = ENOENT;
474 goto fail3;
475 }
476
477 fw_list = MCDI_OUT2(req, efx_word_t,
478 GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST);
479 *subtypep = EFX_WORD_FIELD(fw_list[partn], EFX_WORD_0);
480
481 return (0);
482
483 fail3:
484 EFSYS_PROBE(fail3);
485 fail2:
486 EFSYS_PROBE(fail2);
487 fail1:
488 EFSYS_PROBE1(fail1, efx_rc_t, rc);
489
490 return (rc);
491 }
492
493 __checkReturn efx_rc_t
494 siena_nvram_partn_get_version(
495 __in efx_nic_t *enp,
496 __in uint32_t partn,
497 __out uint32_t *subtypep,
498 __out_ecount(4) uint16_t version[4])
499 {
500 siena_mc_dynamic_config_hdr_t *dcfg;
501 siena_parttbl_entry_t *entry;
502 uint32_t dcfg_partn;
503 unsigned int i;
504 efx_rc_t rc;
505
506 if ((1 << partn) & ~enp->en_u.siena.enu_partn_mask) {
507 rc = ENOTSUP;
508 goto fail1;
509 }
510
511 if ((rc = siena_nvram_get_subtype(enp, partn, subtypep)) != 0)
512 goto fail2;
513
514 /*
515 * Some partitions are accessible from both ports (for instance BOOTROM)
516 * Find the highest version reported by all dcfg structures on ports
517 * that have access to this partition.
518 */
519 version[0] = version[1] = version[2] = version[3] = 0;
520 for (i = 0; i < EFX_ARRAY_SIZE(siena_parttbl); i++) {
521 siena_mc_fw_version_t *verp;
522 unsigned int nitems;
523 uint16_t temp[4];
524 size_t length;
525
526 entry = &siena_parttbl[i];
527 if (entry->partn != partn)
528 continue;
529
530 dcfg_partn = (entry->port == 1)
531 ? MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0
532 : MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1;
533 /*
534 * Ingore missing partitions on port 2, assuming they're due
535 * to to running on a single port part.
536 */
537 if ((1 << dcfg_partn) & ~enp->en_u.siena.enu_partn_mask) {
538 if (entry->port == 2)
539 continue;
540 }
541
542 if ((rc = siena_nvram_get_dynamic_cfg(enp, dcfg_partn,
543 B_FALSE, &dcfg, &length)) != 0)
544 goto fail3;
545
546 nitems = EFX_DWORD_FIELD(dcfg->num_fw_version_items,
547 EFX_DWORD_0);
548 if (nitems < entry->partn)
549 goto done;
550
551 verp = &dcfg->fw_version[partn];
552 temp[0] = EFX_WORD_FIELD(verp->version_w, EFX_WORD_0);
553 temp[1] = EFX_WORD_FIELD(verp->version_x, EFX_WORD_0);
554 temp[2] = EFX_WORD_FIELD(verp->version_y, EFX_WORD_0);
555 temp[3] = EFX_WORD_FIELD(verp->version_z, EFX_WORD_0);
556 if (memcmp(version, temp, sizeof (temp)) < 0)
557 memcpy(version, temp, sizeof (temp));
558
559 done:
560 EFSYS_KMEM_FREE(enp->en_esip, length, dcfg);
561 }
562
563 return (0);
564
565 fail3:
566 EFSYS_PROBE(fail3);
567 fail2:
568 EFSYS_PROBE(fail2);
569 fail1:
570 EFSYS_PROBE1(fail1, efx_rc_t, rc);
571
572 return (rc);
573 }
574
575 __checkReturn efx_rc_t
siena_nvram_partn_rw_start(__in efx_nic_t * enp,__in uint32_t partn,__out size_t * chunk_sizep)576 siena_nvram_partn_rw_start(
577 __in efx_nic_t *enp,
578 __in uint32_t partn,
579 __out size_t *chunk_sizep)
580 {
581 efx_rc_t rc;
582
583 if ((rc = siena_nvram_partn_lock(enp, partn)) != 0)
584 goto fail1;
585
586 if (chunk_sizep != NULL)
587 *chunk_sizep = SIENA_NVRAM_CHUNK;
588
589 return (0);
590
591 fail1:
592 EFSYS_PROBE1(fail1, efx_rc_t, rc);
593
594 return (rc);
595 }
596
597 __checkReturn efx_rc_t
siena_nvram_partn_rw_finish(__in efx_nic_t * enp,__in uint32_t partn,__out_opt uint32_t * verify_resultp)598 siena_nvram_partn_rw_finish(
599 __in efx_nic_t *enp,
600 __in uint32_t partn,
601 __out_opt uint32_t *verify_resultp)
602 {
603 efx_rc_t rc;
604
605 if ((rc = siena_nvram_partn_unlock(enp, partn, verify_resultp)) != 0)
606 goto fail1;
607
608 return (0);
609
610 fail1:
611 EFSYS_PROBE1(fail1, efx_rc_t, rc);
612
613 return (rc);
614 }
615
616 __checkReturn efx_rc_t
617 siena_nvram_partn_set_version(
618 __in efx_nic_t *enp,
619 __in uint32_t partn,
620 __in_ecount(4) uint16_t version[4])
621 {
622 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
623 siena_mc_dynamic_config_hdr_t *dcfg = NULL;
624 siena_mc_fw_version_t *fwverp;
625 uint32_t dcfg_partn;
626 size_t dcfg_size;
627 unsigned int hdr_length;
628 unsigned int vpd_length;
629 unsigned int vpd_offset;
630 unsigned int nitems;
631 unsigned int required_hdr_length;
632 unsigned int pos;
633 uint8_t cksum;
634 uint32_t subtype;
635 size_t length;
636 efx_rc_t rc;
637
638 dcfg_partn = (emip->emi_port == 1)
639 ? MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0
640 : MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1;
641
642 if ((rc = siena_nvram_partn_size(enp, dcfg_partn, &dcfg_size)) != 0)
643 goto fail1;
644
645 if ((rc = siena_nvram_partn_lock(enp, dcfg_partn)) != 0)
646 goto fail2;
647
648 if ((rc = siena_nvram_get_dynamic_cfg(enp, dcfg_partn,
649 B_TRUE, &dcfg, &length)) != 0)
650 goto fail3;
651
652 hdr_length = EFX_WORD_FIELD(dcfg->length, EFX_WORD_0);
653 nitems = EFX_DWORD_FIELD(dcfg->num_fw_version_items, EFX_DWORD_0);
654 vpd_length = EFX_DWORD_FIELD(dcfg->dynamic_vpd_length, EFX_DWORD_0);
655 vpd_offset = EFX_DWORD_FIELD(dcfg->dynamic_vpd_offset, EFX_DWORD_0);
656
657 /*
658 * NOTE: This function will blatt any fields trailing the version
659 * vector, or the VPD chunk.
660 */
661 required_hdr_length = SIENA_DYNAMIC_CFG_SIZE(partn + 1);
662 if (required_hdr_length + vpd_length > length) {
663 rc = ENOSPC;
664 goto fail4;
665 }
666
667 if (vpd_offset < required_hdr_length) {
668 (void) memmove((caddr_t)dcfg + required_hdr_length,
669 (caddr_t)dcfg + vpd_offset, vpd_length);
670 vpd_offset = required_hdr_length;
671 EFX_POPULATE_DWORD_1(dcfg->dynamic_vpd_offset,
672 EFX_DWORD_0, vpd_offset);
673 }
674
675 if (hdr_length < required_hdr_length) {
676 (void) memset((caddr_t)dcfg + hdr_length, 0,
677 required_hdr_length - hdr_length);
678 hdr_length = required_hdr_length;
679 EFX_POPULATE_WORD_1(dcfg->length,
680 EFX_WORD_0, hdr_length);
681 }
682
683 /* Get the subtype to insert into the fw_subtype array */
684 if ((rc = siena_nvram_get_subtype(enp, partn, &subtype)) != 0)
685 goto fail5;
686
687 /* Fill out the new version */
688 fwverp = &dcfg->fw_version[partn];
689 EFX_POPULATE_DWORD_1(fwverp->fw_subtype, EFX_DWORD_0, subtype);
690 EFX_POPULATE_WORD_1(fwverp->version_w, EFX_WORD_0, version[0]);
691 EFX_POPULATE_WORD_1(fwverp->version_x, EFX_WORD_0, version[1]);
692 EFX_POPULATE_WORD_1(fwverp->version_y, EFX_WORD_0, version[2]);
693 EFX_POPULATE_WORD_1(fwverp->version_z, EFX_WORD_0, version[3]);
694
695 /* Update the version count */
696 if (nitems < partn + 1) {
697 nitems = partn + 1;
698 EFX_POPULATE_DWORD_1(dcfg->num_fw_version_items,
699 EFX_DWORD_0, nitems);
700 }
701
702 /* Update the checksum */
703 cksum = 0;
704 for (pos = 0; pos < hdr_length; pos++)
705 cksum += ((uint8_t *)dcfg)[pos];
706 dcfg->csum.eb_u8[0] -= cksum;
707
708 /* Erase and write the new partition */
709 if ((rc = siena_nvram_partn_erase(enp, dcfg_partn, 0, dcfg_size)) != 0)
710 goto fail6;
711
712 /* Write out the new structure to nvram */
713 if ((rc = siena_nvram_partn_write(enp, dcfg_partn, 0,
714 (caddr_t)dcfg, vpd_offset + vpd_length)) != 0)
715 goto fail7;
716
717 EFSYS_KMEM_FREE(enp->en_esip, length, dcfg);
718
719 siena_nvram_partn_unlock(enp, dcfg_partn, NULL);
720
721 return (0);
722
723 fail7:
724 EFSYS_PROBE(fail7);
725 fail6:
726 EFSYS_PROBE(fail6);
727 fail5:
728 EFSYS_PROBE(fail5);
729 fail4:
730 EFSYS_PROBE(fail4);
731
732 EFSYS_KMEM_FREE(enp->en_esip, length, dcfg);
733 fail3:
734 EFSYS_PROBE(fail3);
735 fail2:
736 EFSYS_PROBE(fail2);
737 fail1:
738 EFSYS_PROBE1(fail1, efx_rc_t, rc);
739
740 return (rc);
741 }
742
743 #endif /* EFSYS_OPT_NVRAM */
744
745 #endif /* EFSYS_OPT_SIENA */
746