1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2024 Marvell.
3 */
4
5 #ifndef __CNXK_ESWITCH_H__
6 #define __CNXK_ESWITCH_H__
7
8 #include <sys/socket.h>
9 #include <sys/un.h>
10
11 #include <cnxk_ethdev.h>
12
13 #include "cn10k_tx.h"
14
15 #define CNXK_ESWITCH_CTRL_MSG_SOCK_PATH "/tmp/cxk_rep_ctrl_msg_sock"
16 #define CNXK_ESWITCH_VLAN_TPID ROC_ESWITCH_VLAN_TPID
17 #define CNXK_REP_ESWITCH_DEV_MZ "cnxk_eswitch_dev"
18 #define CNXK_ESWITCH_MAX_TXQ 256
19 #define CNXK_ESWITCH_MAX_RXQ 256
20 #define CNXK_ESWITCH_VFPF_SHIFT 8
21
22 #define CNXK_ESWITCH_QUEUE_STATE_RELEASED 0
23 #define CNXK_ESWITCH_QUEUE_STATE_CONFIGURED 1
24 #define CNXK_ESWITCH_QUEUE_STATE_STARTED 2
25 #define CNXK_ESWITCH_QUEUE_STATE_STOPPED 3
26
27 TAILQ_HEAD(eswitch_flow_list, roc_npc_flow);
28 enum cnxk_esw_da_pattern_type {
29 CNXK_ESW_DA_TYPE_LIST = 0,
30 CNXK_ESW_DA_TYPE_PFVF,
31 };
32
33 struct cnxk_esw_repte_msg {
34 struct roc_eswitch_repte_notify_msg *notify_msg;
35
36 TAILQ_ENTRY(cnxk_esw_repte_msg) next;
37 };
38
39 struct cnxk_esw_repte_msg_proc {
40 bool start_thread;
41 uint8_t msg_avail;
42 rte_thread_t repte_msg_thread;
43 pthread_cond_t repte_msg_cond;
44 pthread_mutex_t mutex;
45
46 TAILQ_HEAD(esw_repte_msg_list, cnxk_esw_repte_msg) msg_list;
47 };
48
49 struct cnxk_esw_repr_hw_info {
50 /* Representee pcifunc value */
51 uint16_t hw_func;
52 /* rep id in sync with kernel */
53 uint16_t rep_id;
54 /* pf or vf id */
55 uint16_t pfvf;
56 /* representor port id assigned to representee */
57 uint16_t port_id;
58 uint16_t num_flow_entries;
59
60 TAILQ_HEAD(flow_list, roc_npc_flow) repr_flow_list;
61 };
62
63 /* Structure representing per devarg information - this can be per representee
64 * or range of representee
65 */
66 struct cnxk_eswitch_devargs {
67 /* Devargs populated */
68 struct rte_eth_devargs da;
69 /* HW info of representee */
70 struct cnxk_esw_repr_hw_info *repr_hw_info;
71 /* No of representor ports */
72 uint16_t nb_repr_ports;
73 /* Devargs pattern type */
74 enum cnxk_esw_da_pattern_type type;
75 };
76
77 struct cnxk_eswitch_repr_cnt {
78 /* Max possible representors */
79 uint16_t max_repr;
80 /* Representors to be created as per devargs passed */
81 uint16_t nb_repr_created;
82 /* Representors probed successfully */
83 uint16_t nb_repr_probed;
84 /* Representors started representing a representee */
85 uint16_t nb_repr_started;
86 };
87
88 struct cnxk_eswitch_switch_domain {
89 uint16_t switch_domain_id;
90 uint16_t pf;
91 };
92
93 struct cnxk_rep_info {
94 struct rte_eth_dev *rep_eth_dev;
95 };
96
97 struct cnxk_eswitch_txq {
98 struct roc_nix_sq sqs;
99 uint8_t state;
100 };
101
102 struct cnxk_eswitch_rxq {
103 struct roc_nix_rq rqs;
104 uint8_t state;
105 };
106
107 struct cnxk_eswitch_cxq {
108 struct roc_nix_cq cqs;
109 uint8_t state;
110 };
111
112 struct cnxk_eswitch_dev {
113 /* Input parameters */
114 struct plt_pci_device *pci_dev;
115 /* ROC NIX */
116 struct roc_nix nix;
117
118 /* ROC NPC */
119 struct roc_npc npc;
120
121 /* ROC NPA */
122 struct rte_mempool *ctrl_chan_pool;
123 const struct plt_memzone *pktmem_mz;
124 uint64_t pkt_aura;
125
126 /* Eswitch RQs, SQs and CQs */
127 struct cnxk_eswitch_txq *txq;
128 struct cnxk_eswitch_rxq *rxq;
129 struct cnxk_eswitch_cxq *cxq;
130
131 /* Configured queue count */
132 uint16_t nb_rxq;
133 uint16_t nb_txq;
134 uint16_t rep_cnt;
135 uint8_t configured;
136
137 /* NPC rxtx rules */
138 struct flow_list esw_flow_list;
139 uint16_t num_entries;
140 bool eswitch_vf_rules_setup;
141 uint16_t esw_pf_entry;
142 uint16_t esw_vf_entry;
143
144 /* Eswitch Representors Devargs */
145 uint16_t nb_esw_da;
146 uint16_t last_probed;
147 struct cnxk_eswitch_devargs esw_da[RTE_MAX_ETHPORTS];
148
149 /* No of representors */
150 struct cnxk_eswitch_repr_cnt repr_cnt;
151
152 /* Representor control channel field */
153 bool start_ctrl_msg_thrd;
154 rte_thread_t rep_ctrl_msg_thread;
155 bool client_connected;
156 int sock_fd;
157
158 /* Representee notification */
159 struct cnxk_esw_repte_msg_proc repte_msg_proc;
160
161 /* Port representor fields */
162 rte_spinlock_t rep_lock;
163 uint16_t nb_switch_domain;
164 struct cnxk_eswitch_switch_domain sw_dom[RTE_MAX_ETHPORTS];
165 uint16_t eswitch_vdev;
166 struct cnxk_rep_info *rep_info;
167 };
168
169 static inline struct cnxk_eswitch_dev *
cnxk_eswitch_pmd_priv(void)170 cnxk_eswitch_pmd_priv(void)
171 {
172 const struct rte_memzone *mz;
173
174 mz = rte_memzone_lookup(CNXK_REP_ESWITCH_DEV_MZ);
175 if (!mz)
176 return NULL;
177
178 return mz->addr;
179 }
180
181 /* HW Resources */
182 int cnxk_eswitch_nix_rsrc_start(struct cnxk_eswitch_dev *eswitch_dev);
183 int cnxk_eswitch_representor_id(struct cnxk_eswitch_dev *eswitch_dev, uint16_t hw_func,
184 uint16_t *rep_id);
185 struct cnxk_esw_repr_hw_info *cnxk_eswitch_representor_hw_info(struct cnxk_eswitch_dev *eswitch_dev,
186 uint16_t hw_func);
187 int cnxk_eswitch_repr_devargs(struct rte_pci_device *pci_dev, struct cnxk_eswitch_dev *eswitch_dev);
188 int cnxk_eswitch_representor_info_get(struct cnxk_eswitch_dev *eswitch_dev,
189 struct rte_eth_representor_info *info);
190 int cnxk_eswitch_txq_setup(struct cnxk_eswitch_dev *eswitch_dev, uint16_t qid, uint16_t nb_desc,
191 const struct rte_eth_txconf *tx_conf);
192 int cnxk_eswitch_txq_release(struct cnxk_eswitch_dev *eswitch_dev, uint16_t qid);
193 int cnxk_eswitch_rxq_setup(struct cnxk_eswitch_dev *eswitch_dev, uint16_t qid, uint16_t nb_desc,
194 const struct rte_eth_rxconf *rx_conf, struct rte_mempool *mp);
195 int cnxk_eswitch_rxq_release(struct cnxk_eswitch_dev *eswitch_dev, uint16_t qid);
196 int cnxk_eswitch_rxq_start(struct cnxk_eswitch_dev *eswitch_dev, uint16_t qid);
197 int cnxk_eswitch_rxq_stop(struct cnxk_eswitch_dev *eswitch_dev, uint16_t qid);
198 int cnxk_eswitch_txq_start(struct cnxk_eswitch_dev *eswitch_dev, uint16_t qid);
199 int cnxk_eswitch_txq_stop(struct cnxk_eswitch_dev *eswitch_dev, uint16_t qid);
200 /* Flow Rules */
201 int cnxk_eswitch_flow_rules_install(struct cnxk_eswitch_dev *eswitch_dev, uint16_t hw_func);
202 int cnxk_eswitch_flow_rules_delete(struct cnxk_eswitch_dev *eswitch_dev, uint16_t hw_func);
203 int cnxk_eswitch_pfvf_flow_rules_install(struct cnxk_eswitch_dev *eswitch_dev, bool is_vf);
204 int cnxk_eswitch_flow_rule_shift(uint16_t hw_func, uint16_t *new_entry);
205 int cnxk_eswitch_flow_rules_remove_list(struct cnxk_eswitch_dev *eswitch_dev,
206 struct flow_list *list, uint16_t hw_func);
207 /* RX TX fastpath routines */
208 uint16_t cnxk_eswitch_dev_tx_burst(struct cnxk_eswitch_dev *eswitch_dev, uint16_t qid,
209 struct rte_mbuf **pkts, uint16_t nb_tx, const uint16_t flags);
210 uint16_t cnxk_eswitch_dev_rx_burst(struct cnxk_eswitch_dev *eswitch_dev, uint16_t qid,
211 struct rte_mbuf **pkts, uint16_t nb_pkts);
212 #endif /* __CNXK_ESWITCH_H__ */
213