1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(C) 2021 Marvell. 3 */ 4 5 #ifndef __REE_HW_H__ 6 #define __REE_HW_H__ 7 8 /* REE instruction queue length */ 9 #define REE_IQ_LEN (1 << 13) 10 11 #define REE_DEFAULT_CMD_QLEN REE_IQ_LEN 12 13 /* Status register bits */ 14 #define REE_STATUS_PMI_EOJ_BIT BIT_ULL(14) 15 #define REE_STATUS_PMI_SOJ_BIT BIT_ULL(13) 16 #define REE_STATUS_MP_CNT_DET_BIT BIT_ULL(7) 17 #define REE_STATUS_MM_CNT_DET_BIT BIT_ULL(6) 18 #define REE_STATUS_ML_CNT_DET_BIT BIT_ULL(5) 19 #define REE_STATUS_MST_CNT_DET_BIT BIT_ULL(4) 20 #define REE_STATUS_MPT_CNT_DET_BIT BIT_ULL(3) 21 22 /* Register offsets */ 23 /* REE LF registers */ 24 #define REE_LF_DONE_INT 0x120ull 25 #define REE_LF_DONE_INT_W1S 0x130ull 26 #define REE_LF_DONE_INT_ENA_W1S 0x138ull 27 #define REE_LF_DONE_INT_ENA_W1C 0x140ull 28 #define REE_LF_MISC_INT 0x300ull 29 #define REE_LF_MISC_INT_W1S 0x310ull 30 #define REE_LF_MISC_INT_ENA_W1S 0x320ull 31 #define REE_LF_MISC_INT_ENA_W1C 0x330ull 32 #define REE_LF_ENA 0x10ull 33 #define REE_LF_SBUF_ADDR 0x20ull 34 #define REE_LF_DONE 0x100ull 35 #define REE_LF_DONE_ACK 0x110ull 36 #define REE_LF_DONE_WAIT 0x148ull 37 #define REE_LF_DOORBELL 0x400ull 38 #define REE_LF_OUTSTAND_JOB 0x410ull 39 40 /* BAR 0 */ 41 #define REE_AF_REEXM_MAX_MATCH (0x80c8ull) 42 #define REE_AF_QUE_SBUF_CTL(a) (0x1200ull | (uint64_t)(a) << 3) 43 #define REE_PRIV_LF_CFG(a) (0x41000ull | (uint64_t)(a) << 3) 44 45 #define REE_AF_QUEX_GMCTL(a) (0x800 | (a) << 3) 46 47 #define REE_AF_INT_VEC_RAS (0x0ull) 48 #define REE_AF_INT_VEC_RVU (0x1ull) 49 #define REE_AF_INT_VEC_QUE_DONE (0x2ull) 50 #define REE_AF_INT_VEC_AQ (0x3ull) 51 52 53 #define REE_LF_INT_VEC_QUE_DONE (0x0ull) 54 #define REE_LF_INT_VEC_MISC (0x1ull) 55 56 #define REE_LF_SBUF_ADDR_OFF_MASK GENMASK_ULL(6, 0) 57 #define REE_LF_SBUF_ADDR_PTR_MASK GENMASK_ULL(52, 7) 58 59 #define REE_LF_ENA_ENA_MASK BIT_ULL(0) 60 61 #define REE_LF_BAR2(vf, q_id) \ 62 ((vf)->dev->bar2 + (((vf)->block_address << 20) | ((q_id) << 12))) 63 64 #define REE_QUEUE_HI_PRIO 0x1 65 66 enum ree_desc_type_e { 67 REE_TYPE_JOB_DESC = 0x0, 68 REE_TYPE_RESULT_DESC = 0x1, 69 REE_TYPE_ENUM_LAST = 0x2 70 }; 71 72 union ree_res_status { 73 uint64_t u; 74 struct { 75 uint64_t job_type : 3; 76 uint64_t mpt_cnt_det : 1; 77 uint64_t mst_cnt_det : 1; 78 uint64_t ml_cnt_det : 1; 79 uint64_t mm_cnt_det : 1; 80 uint64_t mp_cnt_det : 1; 81 uint64_t mode : 2; 82 uint64_t reserved_10_11 : 2; 83 uint64_t reserved_12_12 : 1; 84 uint64_t pmi_soj : 1; 85 uint64_t pmi_eoj : 1; 86 uint64_t reserved_15_15 : 1; 87 uint64_t reserved_16_63 : 48; 88 } s; 89 }; 90 91 union ree_res { 92 uint64_t u[8]; 93 struct ree_res_s_98 { 94 uint64_t done : 1; 95 uint64_t hwjid : 7; 96 uint64_t ree_res_job_id : 24; 97 uint64_t ree_res_status : 16; 98 uint64_t ree_res_dmcnt : 8; 99 uint64_t ree_res_mcnt : 8; 100 uint64_t ree_meta_ptcnt : 16; 101 uint64_t ree_meta_icnt : 16; 102 uint64_t ree_meta_lcnt : 16; 103 uint64_t ree_pmi_min_byte_ptr : 16; 104 uint64_t ree_err : 1; 105 uint64_t reserved_129_190 : 62; 106 uint64_t doneint : 1; 107 uint64_t reserved_192_255 : 64; 108 uint64_t reserved_256_319 : 64; 109 uint64_t reserved_320_383 : 64; 110 uint64_t reserved_384_447 : 64; 111 uint64_t reserved_448_511 : 64; 112 } s; 113 }; 114 115 union ree_match { 116 uint64_t u; 117 struct { 118 uint64_t ree_rule_id : 32; 119 uint64_t start_ptr : 14; 120 uint64_t reserved_46_47 : 2; 121 uint64_t match_length : 15; 122 uint64_t reserved_63_6 : 1; 123 } s; 124 }; 125 126 #endif /* __REE_HW_H__ */ 127