1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(C) 2021 Marvell. 3 */ 4 5 #ifndef _ROC_NPA_PRIV_H_ 6 #define _ROC_NPA_PRIV_H_ 7 8 enum npa_error_status { 9 NPA_ERR_PARAM = -512, 10 NPA_ERR_ALLOC = -513, 11 NPA_ERR_INVALID_BLOCK_SZ = -514, 12 NPA_ERR_AURA_ID_ALLOC = -515, 13 NPA_ERR_AURA_POOL_INIT = -516, 14 NPA_ERR_AURA_POOL_FINI = -517, 15 NPA_ERR_BASE_INVALID = -518, 16 NPA_ERR_DEVICE_NOT_BOUNDED = -519, 17 }; 18 19 struct npa_lf { 20 struct plt_intr_handle *intr_handle; 21 struct npa_aura_attr *aura_attr; 22 struct npa_aura_lim *aura_lim; 23 struct plt_pci_device *pci_dev; 24 struct plt_bitmap *npa_bmp; 25 struct mbox *mbox; 26 uint32_t stack_pg_ptrs; 27 uint32_t stack_pg_bytes; 28 uint16_t npa_msixoff; 29 bool zero_aura_rsvd; 30 void *npa_qint_mem; 31 void *npa_bmp_mem; 32 uint32_t nr_pools; 33 uint16_t pf_func; 34 uint8_t aura_sz; 35 uint32_t qints; 36 uintptr_t base; 37 38 }; 39 40 struct npa_qint { 41 struct npa_lf *lf; 42 uint8_t qintx; 43 }; 44 45 struct npa_aura_lim { 46 uint64_t ptr_start; 47 uint64_t ptr_end; 48 }; 49 50 struct npa_aura_attr { 51 int buf_type[ROC_NPA_BUF_TYPE_END]; 52 uint16_t ref_count; 53 uint64_t nix0_bpid; 54 uint64_t nix1_bpid; 55 uint64_t shift; 56 uint64_t limit; 57 uint8_t bp_ena; 58 uint8_t bp; 59 }; 60 61 struct dev; 62 63 static inline struct npa * roc_npa_to_npa_priv(struct roc_npa * roc_npa)64roc_npa_to_npa_priv(struct roc_npa *roc_npa) 65 { 66 return (struct npa *)&roc_npa->reserved[0]; 67 } 68 69 /* NPA lf */ 70 int npa_lf_init(struct dev *dev, struct plt_pci_device *pci_dev); 71 int npa_lf_fini(void); 72 73 /* IRQ */ 74 int npa_register_irqs(struct npa_lf *lf); 75 void npa_unregister_irqs(struct npa_lf *lf); 76 77 #endif /* _ROC_NPA_PRIV_H_ */ 78