1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * sama7g5.dtsi - Device Tree Include file for SAMA7G5 family SoC 4 * 5 * Copyright (C) 2020 Microchip Technology, Inc. and its subsidiaries 6 * 7 * Author: Eugen Hristev <eugen.hristev@microchip.com> 8 * Author: Claudiu Beznea <claudiu.beznea@microchip.com> 9 * 10 */ 11 12#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/clock/at91.h> 15#include <dt-bindings/dma/at91.h> 16#include <dt-bindings/gpio/gpio.h> 17 18/ { 19 model = "Microchip SAMA7G5 family SoC"; 20 compatible = "microchip,sama7g5"; 21 #address-cells = <1>; 22 #size-cells = <1>; 23 interrupt-parent = <&gic>; 24 25 cpus { 26 #address-cells = <1>; 27 #size-cells = <0>; 28 29 cpu0: cpu@0 { 30 device_type = "cpu"; 31 compatible = "arm,cortex-a7"; 32 reg = <0x0>; 33 }; 34 }; 35 36 clocks { 37 slow_xtal: slow_xtal { 38 compatible = "fixed-clock"; 39 #clock-cells = <0>; 40 }; 41 42 main_xtal: main_xtal { 43 compatible = "fixed-clock"; 44 #clock-cells = <0>; 45 }; 46 47 usb_clk: usb_clk { 48 compatible = "fixed-clock"; 49 #clock-cells = <0>; 50 clock-frequency = <48000000>; 51 }; 52 }; 53 54 vddout25: fixed-regulator-vddout25 { 55 compatible = "regulator-fixed"; 56 57 regulator-name = "VDDOUT25"; 58 regulator-min-microvolt = <2500000>; 59 regulator-max-microvolt = <2500000>; 60 regulator-boot-on; 61 status = "disabled"; 62 }; 63 64 ns_sram: sram@100000 { 65 compatible = "mmio-sram"; 66 #address-cells = <1>; 67 #size-cells = <1>; 68 reg = <0x100000 0x20000>; 69 ranges; 70 }; 71 72 soc { 73 compatible = "simple-bus"; 74 #address-cells = <1>; 75 #size-cells = <1>; 76 ranges; 77 78 securam: securam@e0000000 { 79 compatible = "microchip,sama7g5-securam", "atmel,sama5d2-securam", "mmio-sram"; 80 reg = <0xe0000000 0x4000>; 81 clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; 82 #address-cells = <1>; 83 #size-cells = <1>; 84 ranges = <0 0xe0000000 0x4000>; 85 no-memory-wc; 86 status = "okay"; 87 }; 88 89 secumod: secumod@e0004000 { 90 compatible = "microchip,sama7g5-secumod", "atmel,sama5d2-secumod", "syscon"; 91 reg = <0xe0004000 0x4000>; 92 gpio-controller; 93 #gpio-cells = <2>; 94 }; 95 96 sfrbu: sfr@e0008000 { 97 compatible = "microchip,sama7g5-sfrbu", "atmel,sama5d2-sfrbu", "syscon"; 98 reg = <0xe0008000 0x20>; 99 }; 100 101 pioA: pinctrl@e0014000 { 102 compatible = "microchip,sama7g5-pinctrl"; 103 reg = <0xe0014000 0x800>; 104 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 108 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 109 interrupt-controller; 110 #interrupt-cells = <2>; 111 gpio-controller; 112 #gpio-cells = <2>; 113 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; 114 }; 115 116 pmc: pmc@e0018000 { 117 compatible = "microchip,sama7g5-pmc", "syscon"; 118 reg = <0xe0018000 0x200>; 119 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 120 #clock-cells = <2>; 121 clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>; 122 clock-names = "td_slck", "md_slck", "main_xtal"; 123 }; 124 125 shdwc: shdwc@e001d010 { 126 compatible = "microchip,sama7g5-shdwc", "syscon"; 127 reg = <0xe001d010 0x10>; 128 clocks = <&clk32k 0>; 129 #address-cells = <1>; 130 #size-cells = <0>; 131 atmel,wakeup-rtc-timer; 132 atmel,wakeup-rtt-timer; 133 status = "disabled"; 134 }; 135 136 rtt: rtt@e001d020 { 137 compatible = "microchip,sama7g5-rtt", "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt"; 138 reg = <0xe001d020 0x30>; 139 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 140 clocks = <&clk32k 0>; 141 }; 142 143 clk32k: clock-controller@e001d050 { 144 compatible = "microchip,sama7g5-sckc", "microchip,sam9x60-sckc"; 145 reg = <0xe001d050 0x4>; 146 clocks = <&slow_xtal>; 147 #clock-cells = <1>; 148 }; 149 150 gpbr: gpbr@e001d060 { 151 compatible = "microchip,sama7g5-gpbr", "syscon"; 152 reg = <0xe001d060 0x48>; 153 }; 154 155 ps_wdt: watchdog@e001d180 { 156 compatible = "microchip,sama7g5-wdt"; 157 reg = <0xe001d180 0x24>; 158 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 159 clocks = <&clk32k 0>; 160 }; 161 162 chipid@e0020000 { 163 compatible = "microchip,sama7g5-chipid"; 164 reg = <0xe0020000 0x8>; 165 }; 166 167 sdmmc0: mmc@e1204000 { 168 compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci"; 169 reg = <0xe1204000 0x4000>; 170 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 171 clocks = <&pmc PMC_TYPE_PERIPHERAL 80>, <&pmc PMC_TYPE_GCK 80>; 172 clock-names = "hclock", "multclk"; 173 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; 174 assigned-clocks = <&pmc PMC_TYPE_GCK 80>; 175 assigned-clock-rates = <200000000>; 176 microchip,sdcal-inverted; 177 status = "disabled"; 178 }; 179 180 sdmmc1: mmc@e1208000 { 181 compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci"; 182 reg = <0xe1208000 0x4000>; 183 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 184 clocks = <&pmc PMC_TYPE_PERIPHERAL 81>, <&pmc PMC_TYPE_GCK 81>; 185 clock-names = "hclock", "multclk"; 186 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; 187 assigned-clocks = <&pmc PMC_TYPE_GCK 81>; 188 assigned-clock-rates = <200000000>; 189 microchip,sdcal-inverted; 190 status = "disabled"; 191 }; 192 193 sdmmc2: mmc@e120c000 { 194 compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci"; 195 reg = <0xe120c000 0x4000>; 196 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 197 clocks = <&pmc PMC_TYPE_PERIPHERAL 82>, <&pmc PMC_TYPE_GCK 82>; 198 clock-names = "hclock", "multclk"; 199 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; 200 assigned-clocks = <&pmc PMC_TYPE_GCK 82>; 201 assigned-clock-rates = <200000000>; 202 microchip,sdcal-inverted; 203 status = "disabled"; 204 }; 205 206 pwm: pwm@e1604000 { 207 compatible = "microchip,sama7g5-pwm", "atmel,sama5d2-pwm"; 208 reg = <0xe1604000 0x4000>; 209 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 210 #pwm-cells = <3>; 211 clocks = <&pmc PMC_TYPE_PERIPHERAL 77>; 212 status = "disabled"; 213 }; 214 215 spdifrx: spdifrx@e1614000 { 216 #sound-dai-cells = <0>; 217 compatible = "microchip,sama7g5-spdifrx"; 218 reg = <0xe1614000 0x4000>; 219 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 220 dmas = <&dma0 AT91_XDMAC_DT_PERID(49)>; 221 dma-names = "rx"; 222 clocks = <&pmc PMC_TYPE_PERIPHERAL 84>, <&pmc PMC_TYPE_GCK 84>; 223 clock-names = "pclk", "gclk"; 224 status = "disabled"; 225 }; 226 227 spdiftx: spdiftx@e1618000 { 228 #sound-dai-cells = <0>; 229 compatible = "microchip,sama7g5-spdiftx"; 230 reg = <0xe1618000 0x4000>; 231 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 232 dmas = <&dma0 AT91_XDMAC_DT_PERID(50)>; 233 dma-names = "tx"; 234 clocks = <&pmc PMC_TYPE_PERIPHERAL 85>, <&pmc PMC_TYPE_GCK 85>; 235 clock-names = "pclk", "gclk"; 236 }; 237 238 i2s0: i2s@e161c000 { 239 compatible = "microchip,sama7g5-i2smcc"; 240 #sound-dai-cells = <0>; 241 reg = <0xe161c000 0x4000>; 242 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 243 dmas = <&dma0 AT91_XDMAC_DT_PERID(34)>, <&dma0 AT91_XDMAC_DT_PERID(33)>; 244 dma-names = "tx", "rx"; 245 clocks = <&pmc PMC_TYPE_PERIPHERAL 57>, <&pmc PMC_TYPE_GCK 57>; 246 clock-names = "pclk", "gclk"; 247 status = "disabled"; 248 }; 249 250 i2s1: i2s@e1620000 { 251 compatible = "microchip,sama7g5-i2smcc"; 252 #sound-dai-cells = <0>; 253 reg = <0xe1620000 0x4000>; 254 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 255 dmas = <&dma0 AT91_XDMAC_DT_PERID(36)>, <&dma0 AT91_XDMAC_DT_PERID(35)>; 256 dma-names = "tx", "rx"; 257 clocks = <&pmc PMC_TYPE_PERIPHERAL 58>, <&pmc PMC_TYPE_GCK 58>; 258 clock-names = "pclk", "gclk"; 259 status = "disabled"; 260 }; 261 262 pit64b0: timer@e1800000 { 263 compatible = "microchip,sama7g5-pit64b", "microchip,sam9x60-pit64b"; 264 reg = <0xe1800000 0x4000>; 265 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 266 clocks = <&pmc PMC_TYPE_PERIPHERAL 70>, <&pmc PMC_TYPE_GCK 70>; 267 clock-names = "pclk", "gclk"; 268 }; 269 270 pit64b1: timer@e1804000 { 271 compatible = "microchip,sama7g5-pit64b", "microchip,sam9x60-pit64b"; 272 reg = <0xe1804000 0x4000>; 273 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 274 clocks = <&pmc PMC_TYPE_PERIPHERAL 71>, <&pmc PMC_TYPE_GCK 71>; 275 clock-names = "pclk", "gclk"; 276 }; 277 278 flx0: flexcom@e1818000 { 279 compatible = "atmel,sama5d2-flexcom"; 280 reg = <0xe1818000 0x200>; 281 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; 282 #address-cells = <1>; 283 #size-cells = <1>; 284 ranges = <0x0 0xe1818000 0x800>; 285 status = "disabled"; 286 287 uart0: serial@200 { 288 compatible = "atmel,at91sam9260-usart"; 289 reg = <0x200 0x200>; 290 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 291 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; 292 clock-names = "usart"; 293 dmas = <&dma1 AT91_XDMAC_DT_PERID(6)>, 294 <&dma1 AT91_XDMAC_DT_PERID(5)>; 295 dma-names = "tx", "rx"; 296 atmel,use-dma-rx; 297 atmel,use-dma-tx; 298 status = "disabled"; 299 }; 300 }; 301 302 flx1: flexcom@e181c000 { 303 compatible = "atmel,sama5d2-flexcom"; 304 reg = <0xe181c000 0x200>; 305 clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; 306 #address-cells = <1>; 307 #size-cells = <1>; 308 ranges = <0x0 0xe181c000 0x800>; 309 status = "disabled"; 310 311 i2c1: i2c@600 { 312 compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c"; 313 reg = <0x600 0x200>; 314 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 315 #address-cells = <1>; 316 #size-cells = <0>; 317 clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; 318 atmel,fifo-size = <32>; 319 dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>, 320 <&dma0 AT91_XDMAC_DT_PERID(8)>; 321 dma-names = "rx", "tx"; 322 atmel,use-dma-rx; 323 atmel,use-dma-tx; 324 status = "disabled"; 325 }; 326 }; 327 328 flx3: flexcom@e1824000 { 329 compatible = "atmel,sama5d2-flexcom"; 330 reg = <0xe1824000 0x200>; 331 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; 332 #address-cells = <1>; 333 #size-cells = <1>; 334 ranges = <0x0 0xe1824000 0x800>; 335 status = "disabled"; 336 337 uart3: serial@200 { 338 compatible = "atmel,at91sam9260-usart"; 339 reg = <0x200 0x200>; 340 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 341 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; 342 clock-names = "usart"; 343 dmas = <&dma1 AT91_XDMAC_DT_PERID(12)>, 344 <&dma1 AT91_XDMAC_DT_PERID(11)>; 345 dma-names = "tx", "rx"; 346 atmel,use-dma-rx; 347 atmel,use-dma-tx; 348 status = "disabled"; 349 }; 350 }; 351 352 trng: rng@e2010000 { 353 compatible = "microchip,sama7g5-trng", "atmel,at91sam9g45-trng"; 354 reg = <0xe2010000 0x100>; 355 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 356 clocks = <&pmc PMC_TYPE_PERIPHERAL 97>; 357 status = "disabled"; 358 }; 359 360 flx4: flexcom@e2018000 { 361 compatible = "atmel,sama5d2-flexcom"; 362 reg = <0xe2018000 0x200>; 363 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; 364 #address-cells = <1>; 365 #size-cells = <1>; 366 ranges = <0x0 0xe2018000 0x800>; 367 status = "disabled"; 368 369 uart4: serial@200 { 370 compatible = "atmel,at91sam9260-usart"; 371 reg = <0x200 0x200>; 372 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 373 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; 374 clock-names = "usart"; 375 dmas = <&dma1 AT91_XDMAC_DT_PERID(14)>, 376 <&dma1 AT91_XDMAC_DT_PERID(13)>; 377 dma-names = "tx", "rx"; 378 atmel,use-dma-rx; 379 atmel,use-dma-tx; 380 atmel,fifo-size = <16>; 381 status = "disabled"; 382 }; 383 }; 384 385 flx7: flexcom@e2024000 { 386 compatible = "atmel,sama5d2-flexcom"; 387 reg = <0xe2024000 0x200>; 388 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>; 389 #address-cells = <1>; 390 #size-cells = <1>; 391 ranges = <0x0 0xe2024000 0x800>; 392 status = "disabled"; 393 394 uart7: serial@200 { 395 compatible = "atmel,at91sam9260-usart"; 396 reg = <0x200 0x200>; 397 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 398 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>; 399 clock-names = "usart"; 400 dmas = <&dma1 AT91_XDMAC_DT_PERID(20)>, 401 <&dma1 AT91_XDMAC_DT_PERID(19)>; 402 dma-names = "tx", "rx"; 403 atmel,use-dma-rx; 404 atmel,use-dma-tx; 405 atmel,fifo-size = <16>; 406 status = "disabled"; 407 }; 408 }; 409 410 gmac0: ethernet@e2800000 { 411 compatible = "microchip,sama7g5-gem"; 412 reg = <0xe2800000 0x1000>; 413 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 414 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 415 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 416 GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 417 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 418 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 419 clocks = <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_GCK 51>, <&pmc PMC_TYPE_GCK 53>; 420 clock-names = "pclk", "hclk", "tx_clk", "tsu_clk"; 421 assigned-clocks = <&pmc PMC_TYPE_GCK 51>; 422 assigned-clock-rates = <125000000>; 423 status = "disabled"; 424 }; 425 426 gmac1: ethernet@e2804000 { 427 compatible = "microchip,sama7g5-emac"; 428 reg = <0xe2804000 0x1000>; 429 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 430 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 431 clocks = <&pmc PMC_TYPE_PERIPHERAL 52>, <&pmc PMC_TYPE_PERIPHERAL 52>; 432 clock-names = "pclk", "hclk"; 433 status = "disabled"; 434 }; 435 436 dma0: dma-controller@e2808000 { 437 compatible = "microchip,sama7g5-dma"; 438 reg = <0xe2808000 0x1000>; 439 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 440 #dma-cells = <1>; 441 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 442 clock-names = "dma_clk"; 443 status = "disabled"; 444 }; 445 446 dma1: dma-controller@e280c000 { 447 compatible = "microchip,sama7g5-dma"; 448 reg = <0xe280c000 0x1000>; 449 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 450 #dma-cells = <1>; 451 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 452 clock-names = "dma_clk"; 453 status = "disabled"; 454 }; 455 456 /* Place dma2 here despite it's address */ 457 dma2: dma-controller@e1200000 { 458 compatible = "microchip,sama7g5-dma"; 459 reg = <0xe1200000 0x1000>; 460 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 461 #dma-cells = <1>; 462 clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; 463 clock-names = "dma_clk"; 464 dma-requests = <0>; 465 status = "disabled"; 466 }; 467 468 flx8: flexcom@e2818000 { 469 compatible = "atmel,sama5d2-flexcom"; 470 reg = <0xe2818000 0x200>; 471 clocks = <&pmc PMC_TYPE_PERIPHERAL 46>; 472 #address-cells = <1>; 473 #size-cells = <1>; 474 ranges = <0x0 0xe2818000 0x800>; 475 status = "disabled"; 476 477 i2c8: i2c@600 { 478 compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c"; 479 reg = <0x600 0x200>; 480 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 481 #address-cells = <1>; 482 #size-cells = <0>; 483 clocks = <&pmc PMC_TYPE_PERIPHERAL 46>; 484 atmel,fifo-size = <32>; 485 dmas = <&dma0 AT91_XDMAC_DT_PERID(21)>, 486 <&dma0 AT91_XDMAC_DT_PERID(22)>; 487 dma-names = "rx", "tx"; 488 atmel,use-dma-rx; 489 atmel,use-dma-tx; 490 status = "disabled"; 491 }; 492 }; 493 494 flx9: flexcom@e281c000 { 495 compatible = "atmel,sama5d2-flexcom"; 496 reg = <0xe281c000 0x200>; 497 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; 498 #address-cells = <1>; 499 #size-cells = <1>; 500 ranges = <0x0 0xe281c000 0x800>; 501 status = "disabled"; 502 503 i2c9: i2c@600 { 504 compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c"; 505 reg = <0x600 0x200>; 506 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 507 #address-cells = <1>; 508 #size-cells = <0>; 509 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; 510 atmel,fifo-size = <32>; 511 dmas = <&dma0 AT91_XDMAC_DT_PERID(23)>, 512 <&dma0 AT91_XDMAC_DT_PERID(24)>; 513 dma-names = "rx", "tx"; 514 atmel,use-dma-rx; 515 atmel,use-dma-tx; 516 status = "disabled"; 517 }; 518 }; 519 520 flx11: flexcom@e2824000 { 521 compatible = "atmel,sama5d2-flexcom"; 522 reg = <0xe2824000 0x200>; 523 clocks = <&pmc PMC_TYPE_PERIPHERAL 49>; 524 #address-cells = <1>; 525 #size-cells = <1>; 526 ranges = <0x0 0xe2824000 0x800>; 527 status = "disabled"; 528 529 spi11: spi@400 { 530 compatible = "atmel,at91rm9200-spi"; 531 reg = <0x400 0x200>; 532 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 533 clocks = <&pmc PMC_TYPE_PERIPHERAL 49>; 534 clock-names = "spi_clk"; 535 #address-cells = <1>; 536 #size-cells = <0>; 537 atmel,fifo-size = <32>; 538 dmas = <&dma0 AT91_XDMAC_DT_PERID(27)>, 539 <&dma0 AT91_XDMAC_DT_PERID(28)>; 540 dma-names = "rx", "tx"; 541 status = "disabled"; 542 }; 543 }; 544 545 uddrc: uddrc@e3800000 { 546 compatible = "microchip,sama7g5-uddrc"; 547 reg = <0xe3800000 0x4000>; 548 status = "okay"; 549 }; 550 551 ddr3phy: ddr3phy@e3804000 { 552 compatible = "microchip,sama7g5-ddr3phy"; 553 reg = <0xe3804000 0x1000>; 554 status = "okay"; 555 }; 556 557 gic: interrupt-controller@e8c11000 { 558 compatible = "arm,cortex-a7-gic"; 559 #interrupt-cells = <3>; 560 #address-cells = <0>; 561 interrupt-controller; 562 interrupt-parent; 563 reg = <0xe8c11000 0x1000>, 564 <0xe8c12000 0x2000>; 565 }; 566 }; 567}; 568