1 /* $NetBSD: amdgpu_smu_v11_0_i2c.c,v 1.3 2021/12/19 12:21:29 riastradh Exp $ */
2
3 /*
4 * Copyright 2019 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25
26 #include <sys/cdefs.h>
27 __KERNEL_RCSID(0, "$NetBSD: amdgpu_smu_v11_0_i2c.c,v 1.3 2021/12/19 12:21:29 riastradh Exp $");
28
29 #include "smuio/smuio_11_0_0_offset.h"
30 #include "smuio/smuio_11_0_0_sh_mask.h"
31
32 #include "smu_v11_0_i2c.h"
33 #include "amdgpu.h"
34 #include "soc15_common.h"
35 #include <drm/drm_fixed.h>
36 #include <drm/drm_drv.h>
37 #include "amdgpu_amdkfd.h"
38 #include <linux/i2c.h>
39 #include <linux/pci.h>
40 #include "amdgpu_ras.h"
41
42 /* error codes */
43 #define I2C_OK 0
44 #define I2C_NAK_7B_ADDR_NOACK 1
45 #define I2C_NAK_TXDATA_NOACK 2
46 #define I2C_TIMEOUT 4
47 #define I2C_SW_TIMEOUT 8
48 #define I2C_ABORT 0x10
49
50 /* I2C transaction flags */
51 #define I2C_NO_STOP 1
52 #define I2C_RESTART 2
53
54 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_ras, eeprom_control.eeprom_accessor))->adev
55 #define to_eeprom_control(x) container_of(x, struct amdgpu_ras_eeprom_control, eeprom_accessor)
56
smu_v11_0_i2c_set_clock_gating(struct i2c_adapter * control,bool en)57 static void smu_v11_0_i2c_set_clock_gating(struct i2c_adapter *control, bool en)
58 {
59 struct amdgpu_device *adev = to_amdgpu_device(control);
60 uint32_t reg = RREG32_SOC15(SMUIO, 0, mmSMUIO_PWRMGT);
61
62 reg = REG_SET_FIELD(reg, SMUIO_PWRMGT, i2c_clk_gate_en, en ? 1 : 0);
63 WREG32_SOC15(SMUIO, 0, mmSMUIO_PWRMGT, reg);
64 }
65
66
smu_v11_0_i2c_enable(struct i2c_adapter * control,bool enable)67 static void smu_v11_0_i2c_enable(struct i2c_adapter *control, bool enable)
68 {
69 struct amdgpu_device *adev = to_amdgpu_device(control);
70
71 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE, enable ? 1 : 0);
72 }
73
smu_v11_0_i2c_clear_status(struct i2c_adapter * control)74 static void smu_v11_0_i2c_clear_status(struct i2c_adapter *control)
75 {
76 struct amdgpu_device *adev = to_amdgpu_device(control);
77 /* do */
78 {
79 RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_CLR_INTR);
80
81 } /* while (reg_CKSVII2C_ic_clr_intr == 0) */
82 }
83
smu_v11_0_i2c_configure(struct i2c_adapter * control)84 static void smu_v11_0_i2c_configure(struct i2c_adapter *control)
85 {
86 struct amdgpu_device *adev = to_amdgpu_device(control);
87 uint32_t reg = 0;
88
89 reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_SLAVE_DISABLE, 1);
90 reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_RESTART_EN, 1);
91 reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_10BITADDR_MASTER, 0);
92 reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_10BITADDR_SLAVE, 0);
93 /* Standard mode */
94 reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_MAX_SPEED_MODE, 2);
95 reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_MASTER_MODE, 1);
96
97 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_CON, reg);
98 }
99
smu_v11_0_i2c_set_clock(struct i2c_adapter * control)100 static void smu_v11_0_i2c_set_clock(struct i2c_adapter *control)
101 {
102 struct amdgpu_device *adev = to_amdgpu_device(control);
103
104 /*
105 * Standard mode speed, These values are taken from SMUIO MAS,
106 * but are different from what is given is
107 * Synopsys spec. The values here are based on assumption
108 * that refclock is 100MHz
109 *
110 * Configuration for standard mode; Speed = 100kbps
111 * Scale linearly, for now only support standard speed clock
112 * This will work only with 100M ref clock
113 *
114 * TBD:Change the calculation to take into account ref clock values also.
115 */
116
117 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_FS_SPKLEN, 2);
118 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_SS_SCL_HCNT, 120);
119 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_SS_SCL_LCNT, 130);
120 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_SDA_HOLD, 20);
121 }
122
smu_v11_0_i2c_set_address(struct i2c_adapter * control,uint8_t address)123 static void smu_v11_0_i2c_set_address(struct i2c_adapter *control, uint8_t address)
124 {
125 struct amdgpu_device *adev = to_amdgpu_device(control);
126
127 /* Convert fromr 8-bit to 7-bit address */
128 address >>= 1;
129 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_TAR, (address & 0xFF));
130 }
131
smu_v11_0_i2c_poll_tx_status(struct i2c_adapter * control)132 static uint32_t smu_v11_0_i2c_poll_tx_status(struct i2c_adapter *control)
133 {
134 struct amdgpu_device *adev = to_amdgpu_device(control);
135 uint32_t ret = I2C_OK;
136 uint32_t reg, reg_c_tx_abrt_source;
137
138 /*Check if transmission is completed */
139 unsigned long timeout_counter = jiffies + msecs_to_jiffies(20);
140
141 do {
142 if (time_after(jiffies, timeout_counter)) {
143 ret |= I2C_SW_TIMEOUT;
144 break;
145 }
146
147 reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS);
148
149 } while (REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFE) == 0);
150
151 if (ret != I2C_OK)
152 return ret;
153
154 /* This only checks if NAK is received and transaction got aborted */
155 reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_INTR_STAT);
156
157 if (REG_GET_FIELD(reg, CKSVII2C_IC_INTR_STAT, R_TX_ABRT) == 1) {
158 reg_c_tx_abrt_source = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_TX_ABRT_SOURCE);
159 DRM_INFO("TX was terminated, IC_TX_ABRT_SOURCE val is:%x", reg_c_tx_abrt_source);
160
161 /* Check for stop due to NACK */
162 if (REG_GET_FIELD(reg_c_tx_abrt_source,
163 CKSVII2C_IC_TX_ABRT_SOURCE,
164 ABRT_TXDATA_NOACK) == 1) {
165
166 ret |= I2C_NAK_TXDATA_NOACK;
167
168 } else if (REG_GET_FIELD(reg_c_tx_abrt_source,
169 CKSVII2C_IC_TX_ABRT_SOURCE,
170 ABRT_7B_ADDR_NOACK) == 1) {
171
172 ret |= I2C_NAK_7B_ADDR_NOACK;
173 } else {
174 ret |= I2C_ABORT;
175 }
176
177 smu_v11_0_i2c_clear_status(control);
178 }
179
180 return ret;
181 }
182
smu_v11_0_i2c_poll_rx_status(struct i2c_adapter * control)183 static uint32_t smu_v11_0_i2c_poll_rx_status(struct i2c_adapter *control)
184 {
185 struct amdgpu_device *adev = to_amdgpu_device(control);
186 uint32_t ret = I2C_OK;
187 uint32_t reg_ic_status, reg_c_tx_abrt_source;
188
189 reg_c_tx_abrt_source = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_TX_ABRT_SOURCE);
190
191 /* If slave is not present */
192 if (REG_GET_FIELD(reg_c_tx_abrt_source,
193 CKSVII2C_IC_TX_ABRT_SOURCE,
194 ABRT_7B_ADDR_NOACK) == 1) {
195 ret |= I2C_NAK_7B_ADDR_NOACK;
196
197 smu_v11_0_i2c_clear_status(control);
198 } else { /* wait till some data is there in RXFIFO */
199 /* Poll for some byte in RXFIFO */
200 unsigned long timeout_counter = jiffies + msecs_to_jiffies(20);
201
202 do {
203 if (time_after(jiffies, timeout_counter)) {
204 ret |= I2C_SW_TIMEOUT;
205 break;
206 }
207
208 reg_ic_status = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS);
209
210 } while (REG_GET_FIELD(reg_ic_status, CKSVII2C_IC_STATUS, RFNE) == 0);
211 }
212
213 return ret;
214 }
215
216
217
218
219 /**
220 * smu_v11_0_i2c_transmit - Send a block of data over the I2C bus to a slave device.
221 *
222 * @address: The I2C address of the slave device.
223 * @data: The data to transmit over the bus.
224 * @numbytes: The amount of data to transmit.
225 * @i2c_flag: Flags for transmission
226 *
227 * Returns 0 on success or error.
228 */
smu_v11_0_i2c_transmit(struct i2c_adapter * control,uint8_t address,uint8_t * data,uint32_t numbytes,uint32_t i2c_flag)229 static uint32_t smu_v11_0_i2c_transmit(struct i2c_adapter *control,
230 uint8_t address, uint8_t *data,
231 uint32_t numbytes, uint32_t i2c_flag)
232 {
233 struct amdgpu_device *adev = to_amdgpu_device(control);
234 uint32_t bytes_sent, reg, ret = 0;
235 unsigned long timeout_counter;
236
237 bytes_sent = 0;
238
239 DRM_DEBUG_DRIVER("I2C_Transmit(), address = %x, bytes = %d , data: ",
240 (uint16_t)address, numbytes);
241
242 if (drm_debug_enabled(DRM_UT_DRIVER)) {
243 print_hex_dump(KERN_INFO, "data: ", DUMP_PREFIX_NONE,
244 16, 1, data, numbytes, false);
245 }
246
247 /* Set the I2C slave address */
248 smu_v11_0_i2c_set_address(control, address);
249 /* Enable I2C */
250 smu_v11_0_i2c_enable(control, true);
251
252 /* Clear status bits */
253 smu_v11_0_i2c_clear_status(control);
254
255
256 timeout_counter = jiffies + msecs_to_jiffies(20);
257
258 while (numbytes > 0) {
259 reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS);
260 if (REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFNF)) {
261 do {
262 reg = 0;
263 /*
264 * Prepare transaction, no need to set RESTART. I2C engine will send
265 * START as soon as it sees data in TXFIFO
266 */
267 if (bytes_sent == 0)
268 reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, RESTART,
269 (i2c_flag & I2C_RESTART) ? 1 : 0);
270 reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, DAT, data[bytes_sent]);
271
272 /* determine if we need to send STOP bit or not */
273 if (numbytes == 1)
274 /* Final transaction, so send stop unless I2C_NO_STOP */
275 reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, STOP,
276 (i2c_flag & I2C_NO_STOP) ? 0 : 1);
277 /* Write */
278 reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, CMD, 0);
279 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_DATA_CMD, reg);
280
281 /* Record that the bytes were transmitted */
282 bytes_sent++;
283 numbytes--;
284
285 reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS);
286
287 } while (numbytes && REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFNF));
288 }
289
290 /*
291 * We waited too long for the transmission FIFO to become not-full.
292 * Exit the loop with error.
293 */
294 if (time_after(jiffies, timeout_counter)) {
295 ret |= I2C_SW_TIMEOUT;
296 goto Err;
297 }
298 }
299
300 ret = smu_v11_0_i2c_poll_tx_status(control);
301
302 Err:
303 /* Any error, no point in proceeding */
304 if (ret != I2C_OK) {
305 if (ret & I2C_SW_TIMEOUT)
306 DRM_ERROR("TIMEOUT ERROR !!!");
307
308 if (ret & I2C_NAK_7B_ADDR_NOACK)
309 DRM_ERROR("Received I2C_NAK_7B_ADDR_NOACK !!!");
310
311
312 if (ret & I2C_NAK_TXDATA_NOACK)
313 DRM_ERROR("Received I2C_NAK_TXDATA_NOACK !!!");
314 }
315
316 return ret;
317 }
318
319
320 /**
321 * smu_v11_0_i2c_receive - Receive a block of data over the I2C bus from a slave device.
322 *
323 * @address: The I2C address of the slave device.
324 * @numbytes: The amount of data to transmit.
325 * @i2c_flag: Flags for transmission
326 *
327 * Returns 0 on success or error.
328 */
smu_v11_0_i2c_receive(struct i2c_adapter * control,uint8_t address,uint8_t * data,uint32_t numbytes,uint8_t i2c_flag)329 static uint32_t smu_v11_0_i2c_receive(struct i2c_adapter *control,
330 uint8_t address, uint8_t *data,
331 uint32_t numbytes, uint8_t i2c_flag)
332 {
333 struct amdgpu_device *adev = to_amdgpu_device(control);
334 uint32_t bytes_received, ret = I2C_OK;
335
336 bytes_received = 0;
337
338 /* Set the I2C slave address */
339 smu_v11_0_i2c_set_address(control, address);
340
341 /* Enable I2C */
342 smu_v11_0_i2c_enable(control, true);
343
344 while (numbytes > 0) {
345 uint32_t reg = 0;
346
347 smu_v11_0_i2c_clear_status(control);
348
349
350 /* Prepare transaction */
351
352 /* Each time we disable I2C, so this is not a restart */
353 if (bytes_received == 0)
354 reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, RESTART,
355 (i2c_flag & I2C_RESTART) ? 1 : 0);
356
357 reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, DAT, 0);
358 /* Read */
359 reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, CMD, 1);
360
361 /* Transmitting last byte */
362 if (numbytes == 1)
363 /* Final transaction, so send stop if requested */
364 reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, STOP,
365 (i2c_flag & I2C_NO_STOP) ? 0 : 1);
366
367 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_DATA_CMD, reg);
368
369 ret = smu_v11_0_i2c_poll_rx_status(control);
370
371 /* Any error, no point in proceeding */
372 if (ret != I2C_OK) {
373 if (ret & I2C_SW_TIMEOUT)
374 DRM_ERROR("TIMEOUT ERROR !!!");
375
376 if (ret & I2C_NAK_7B_ADDR_NOACK)
377 DRM_ERROR("Received I2C_NAK_7B_ADDR_NOACK !!!");
378
379 if (ret & I2C_NAK_TXDATA_NOACK)
380 DRM_ERROR("Received I2C_NAK_TXDATA_NOACK !!!");
381
382 break;
383 }
384
385 reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_DATA_CMD);
386 data[bytes_received] = REG_GET_FIELD(reg, CKSVII2C_IC_DATA_CMD, DAT);
387
388 /* Record that the bytes were received */
389 bytes_received++;
390 numbytes--;
391 }
392
393 DRM_DEBUG_DRIVER("I2C_Receive(), address = %x, bytes = %d, data :",
394 (uint16_t)address, bytes_received);
395
396 if (drm_debug_enabled(DRM_UT_DRIVER)) {
397 print_hex_dump(KERN_INFO, "data: ", DUMP_PREFIX_NONE,
398 16, 1, data, bytes_received, false);
399 }
400
401 return ret;
402 }
403
smu_v11_0_i2c_abort(struct i2c_adapter * control)404 static void smu_v11_0_i2c_abort(struct i2c_adapter *control)
405 {
406 struct amdgpu_device *adev = to_amdgpu_device(control);
407 uint32_t reg = 0;
408
409 /* Enable I2C engine; */
410 reg = REG_SET_FIELD(reg, CKSVII2C_IC_ENABLE, ENABLE, 1);
411 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE, reg);
412
413 /* Abort previous transaction */
414 reg = REG_SET_FIELD(reg, CKSVII2C_IC_ENABLE, ABORT, 1);
415 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE, reg);
416
417 DRM_DEBUG_DRIVER("I2C_Abort() Done.");
418 }
419
420
smu_v11_0_i2c_activity_done(struct i2c_adapter * control)421 static bool smu_v11_0_i2c_activity_done(struct i2c_adapter *control)
422 {
423 struct amdgpu_device *adev = to_amdgpu_device(control);
424
425 const uint32_t IDLE_TIMEOUT = 1024;
426 uint32_t timeout_count = 0;
427 uint32_t reg_ic_enable, reg_ic_enable_status, reg_ic_clr_activity;
428
429 reg_ic_enable_status = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE_STATUS);
430 reg_ic_enable = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE);
431
432
433 if ((REG_GET_FIELD(reg_ic_enable, CKSVII2C_IC_ENABLE, ENABLE) == 0) &&
434 (REG_GET_FIELD(reg_ic_enable_status, CKSVII2C_IC_ENABLE_STATUS, IC_EN) == 1)) {
435 /*
436 * Nobody is using I2C engine, but engine remains active because
437 * someone missed to send STOP
438 */
439 smu_v11_0_i2c_abort(control);
440 } else if (REG_GET_FIELD(reg_ic_enable, CKSVII2C_IC_ENABLE, ENABLE) == 0) {
441 /* Nobody is using I2C engine */
442 return true;
443 }
444
445 /* Keep reading activity bit until it's cleared */
446 do {
447 reg_ic_clr_activity = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_CLR_ACTIVITY);
448
449 if (REG_GET_FIELD(reg_ic_clr_activity,
450 CKSVII2C_IC_CLR_ACTIVITY, CLR_ACTIVITY) == 0)
451 return true;
452
453 ++timeout_count;
454
455 } while (timeout_count < IDLE_TIMEOUT);
456
457 return false;
458 }
459
smu_v11_0_i2c_init(struct i2c_adapter * control)460 static void smu_v11_0_i2c_init(struct i2c_adapter *control)
461 {
462 /* Disable clock gating */
463 smu_v11_0_i2c_set_clock_gating(control, false);
464
465 if (!smu_v11_0_i2c_activity_done(control))
466 DRM_WARN("I2C busy !");
467
468 /* Disable I2C */
469 smu_v11_0_i2c_enable(control, false);
470
471 /* Configure I2C to operate as master and in standard mode */
472 smu_v11_0_i2c_configure(control);
473
474 /* Initialize the clock to 50 kHz default */
475 smu_v11_0_i2c_set_clock(control);
476
477 }
478
smu_v11_0_i2c_fini(struct i2c_adapter * control)479 static void smu_v11_0_i2c_fini(struct i2c_adapter *control)
480 {
481 struct amdgpu_device *adev = to_amdgpu_device(control);
482 uint32_t reg_ic_enable_status, reg_ic_enable;
483
484 smu_v11_0_i2c_enable(control, false);
485
486 /* Double check if disabled, else force abort */
487 reg_ic_enable_status = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE_STATUS);
488 reg_ic_enable = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE);
489
490 if ((REG_GET_FIELD(reg_ic_enable, CKSVII2C_IC_ENABLE, ENABLE) == 0) &&
491 (REG_GET_FIELD(reg_ic_enable_status,
492 CKSVII2C_IC_ENABLE_STATUS, IC_EN) == 1)) {
493 /*
494 * Nobody is using I2C engine, but engine remains active because
495 * someone missed to send STOP
496 */
497 smu_v11_0_i2c_abort(control);
498 }
499
500 /* Restore clock gating */
501
502 /*
503 * TODO Reenabling clock gating seems to break subsequent SMU operation
504 * on the I2C bus. My guess is that SMU doesn't disable clock gating like
505 * we do here before working with the bus. So for now just don't restore
506 * it but later work with SMU to see if they have this issue and can
507 * update their code appropriately
508 */
509 /* smu_v11_0_i2c_set_clock_gating(control, true); */
510
511 }
512
smu_v11_0_i2c_bus_lock(struct i2c_adapter * control)513 static bool smu_v11_0_i2c_bus_lock(struct i2c_adapter *control)
514 {
515 struct amdgpu_device *adev = to_amdgpu_device(control);
516
517 /* Send PPSMC_MSG_RequestI2CBus */
518 if (!adev->powerplay.pp_funcs->smu_i2c_bus_access)
519 goto Fail;
520
521
522 if (!adev->powerplay.pp_funcs->smu_i2c_bus_access(adev->powerplay.pp_handle, true))
523 return true;
524
525 Fail:
526 return false;
527 }
528
smu_v11_0_i2c_bus_unlock(struct i2c_adapter * control)529 static bool smu_v11_0_i2c_bus_unlock(struct i2c_adapter *control)
530 {
531 struct amdgpu_device *adev = to_amdgpu_device(control);
532
533 /* Send PPSMC_MSG_RequestI2CBus */
534 if (!adev->powerplay.pp_funcs->smu_i2c_bus_access)
535 goto Fail;
536
537 /* Send PPSMC_MSG_ReleaseI2CBus */
538 if (!adev->powerplay.pp_funcs->smu_i2c_bus_access(adev->powerplay.pp_handle,
539 false))
540 return true;
541
542 Fail:
543 return false;
544 }
545
546 /***************************** EEPROM I2C GLUE ****************************/
547
smu_v11_0_i2c_eeprom_read_data(struct i2c_adapter * control,uint8_t address,uint8_t * data,uint32_t numbytes)548 static uint32_t smu_v11_0_i2c_eeprom_read_data(struct i2c_adapter *control,
549 uint8_t address,
550 uint8_t *data,
551 uint32_t numbytes)
552 {
553 uint32_t ret = 0;
554
555 /* First 2 bytes are dummy write to set EEPROM address */
556 ret = smu_v11_0_i2c_transmit(control, address, data, 2, I2C_NO_STOP);
557 if (ret != I2C_OK)
558 goto Fail;
559
560 /* Now read data starting with that address */
561 ret = smu_v11_0_i2c_receive(control, address, data + 2, numbytes - 2,
562 I2C_RESTART);
563
564 Fail:
565 if (ret != I2C_OK)
566 DRM_ERROR("ReadData() - I2C error occurred :%x", ret);
567
568 return ret;
569 }
570
smu_v11_0_i2c_eeprom_write_data(struct i2c_adapter * control,uint8_t address,uint8_t * data,uint32_t numbytes)571 static uint32_t smu_v11_0_i2c_eeprom_write_data(struct i2c_adapter *control,
572 uint8_t address,
573 uint8_t *data,
574 uint32_t numbytes)
575 {
576 uint32_t ret;
577
578 ret = smu_v11_0_i2c_transmit(control, address, data, numbytes, 0);
579
580 if (ret != I2C_OK)
581 DRM_ERROR("WriteI2CData() - I2C error occurred :%x", ret);
582 else
583 /*
584 * According to EEPROM spec there is a MAX of 10 ms required for
585 * EEPROM to flush internal RX buffer after STOP was issued at the
586 * end of write transaction. During this time the EEPROM will not be
587 * responsive to any more commands - so wait a bit more.
588 *
589 * TODO Improve to wait for first ACK for slave address after
590 * internal write cycle done.
591 */
592 msleep(10);
593
594 return ret;
595
596 }
597
lock_bus(struct i2c_adapter * i2c,unsigned int flags)598 static void lock_bus(struct i2c_adapter *i2c, unsigned int flags)
599 {
600 struct amdgpu_ras_eeprom_control *control = to_eeprom_control(i2c);
601
602 if (!smu_v11_0_i2c_bus_lock(i2c)) {
603 DRM_ERROR("Failed to lock the bus from SMU");
604 return;
605 }
606
607 control->bus_locked = true;
608 }
609
trylock_bus(struct i2c_adapter * i2c,unsigned int flags)610 static int trylock_bus(struct i2c_adapter *i2c, unsigned int flags)
611 {
612 WARN_ONCE(1, "This operation not supposed to run in atomic context!");
613 return false;
614 }
615
unlock_bus(struct i2c_adapter * i2c,unsigned int flags)616 static void unlock_bus(struct i2c_adapter *i2c, unsigned int flags)
617 {
618 struct amdgpu_ras_eeprom_control *control = to_eeprom_control(i2c);
619
620 if (!smu_v11_0_i2c_bus_unlock(i2c)) {
621 DRM_ERROR("Failed to unlock the bus from SMU");
622 return;
623 }
624
625 control->bus_locked = false;
626 }
627
628 static const struct i2c_lock_operations smu_v11_0_i2c_i2c_lock_ops = {
629 .lock_bus = lock_bus,
630 .trylock_bus = trylock_bus,
631 .unlock_bus = unlock_bus,
632 };
633
smu_v11_0_i2c_eeprom_i2c_xfer(struct i2c_adapter * i2c_adap,struct i2c_msg * msgs,int num)634 static int smu_v11_0_i2c_eeprom_i2c_xfer(struct i2c_adapter *i2c_adap,
635 struct i2c_msg *msgs, int num)
636 {
637 int i, ret;
638 struct amdgpu_ras_eeprom_control *control = to_eeprom_control(i2c_adap);
639
640 if (!control->bus_locked) {
641 DRM_ERROR("I2C bus unlocked, stopping transaction!");
642 return -EIO;
643 }
644
645 smu_v11_0_i2c_init(i2c_adap);
646
647 for (i = 0; i < num; i++) {
648 if (msgs[i].flags & I2C_M_RD)
649 ret = smu_v11_0_i2c_eeprom_read_data(i2c_adap,
650 (uint8_t)msgs[i].addr,
651 msgs[i].buf, msgs[i].len);
652 else
653 ret = smu_v11_0_i2c_eeprom_write_data(i2c_adap,
654 (uint8_t)msgs[i].addr,
655 msgs[i].buf, msgs[i].len);
656
657 if (ret != I2C_OK) {
658 num = -EIO;
659 break;
660 }
661 }
662
663 smu_v11_0_i2c_fini(i2c_adap);
664 return num;
665 }
666
smu_v11_0_i2c_eeprom_i2c_func(struct i2c_adapter * adap)667 static u32 smu_v11_0_i2c_eeprom_i2c_func(struct i2c_adapter *adap)
668 {
669 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
670 }
671
672
673 static const struct i2c_algorithm smu_v11_0_i2c_eeprom_i2c_algo = {
674 .master_xfer = smu_v11_0_i2c_eeprom_i2c_xfer,
675 .functionality = smu_v11_0_i2c_eeprom_i2c_func,
676 };
677
smu_v11_0_i2c_eeprom_control_init(struct i2c_adapter * control)678 int smu_v11_0_i2c_eeprom_control_init(struct i2c_adapter *control)
679 {
680 struct amdgpu_device *adev = to_amdgpu_device(control);
681 int res;
682
683 control->owner = THIS_MODULE;
684 control->class = I2C_CLASS_SPD;
685 control->dev.parent = pci_dev_dev(adev->pdev);
686 control->algo = &smu_v11_0_i2c_eeprom_i2c_algo;
687 snprintf(control->name, sizeof(control->name), "RAS EEPROM");
688 control->lock_ops = &smu_v11_0_i2c_i2c_lock_ops;
689
690 res = i2c_add_adapter(control);
691 if (res)
692 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
693
694 return res;
695 }
696
smu_v11_0_i2c_eeprom_control_fini(struct i2c_adapter * control)697 void smu_v11_0_i2c_eeprom_control_fini(struct i2c_adapter *control)
698 {
699 i2c_del_adapter(control);
700 }
701
702 /*
703 * Keep this for future unit test if bugs arise
704 */
705 #if 0
706 #define I2C_TARGET_ADDR 0xA0
707
708 bool smu_v11_0_i2c_test_bus(struct i2c_adapter *control)
709 {
710
711 uint32_t ret = I2C_OK;
712 uint8_t data[6] = {0xf, 0, 0xde, 0xad, 0xbe, 0xef};
713
714
715 DRM_INFO("Begin");
716
717 if (!smu_v11_0_i2c_bus_lock(control)) {
718 DRM_ERROR("Failed to lock the bus!.");
719 return false;
720 }
721
722 smu_v11_0_i2c_init(control);
723
724 /* Write 0xde to address 0x0000 on the EEPROM */
725 ret = smu_v11_0_i2c_eeprom_write_data(control, I2C_TARGET_ADDR, data, 6);
726
727 ret = smu_v11_0_i2c_eeprom_read_data(control, I2C_TARGET_ADDR, data, 6);
728
729 smu_v11_0_i2c_fini(control);
730
731 smu_v11_0_i2c_bus_unlock(control);
732
733
734 DRM_INFO("End");
735 return true;
736 }
737 #endif
738