xref: /netbsd-src/sys/arch/i386/pci/sis85c503.c (revision f5b064ee385650bff4906d7abf18d635e842b8ee)
1 /*	$NetBSD: sis85c503.c,v 1.10 2011/07/01 17:37:27 dyoung Exp $	*/
2 
3 /*-
4  * Copyright (c) 1999 The NetBSD Foundation, Inc.
5  * All rights reserved.
6  *
7  * This code is derived from software contributed to The NetBSD Foundation
8  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
9  * NASA Ames Research Center.
10  *
11  * Redistribution and use in source and binary forms, with or without
12  * modification, are permitted provided that the following conditions
13  * are met:
14  * 1. Redistributions of source code must retain the above copyright
15  *    notice, this list of conditions and the following disclaimer.
16  * 2. Redistributions in binary form must reproduce the above copyright
17  *    notice, this list of conditions and the following disclaimer in the
18  *    documentation and/or other materials provided with the distribution.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
21  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30  * POSSIBILITY OF SUCH DAMAGE.
31  */
32 
33 /*
34  * Copyright (c) 1999, by UCHIYAMA Yasushi
35  * All rights reserved.
36  *
37  * Redistribution and use in source and binary forms, with or without
38  * modification, are permitted provided that the following conditions
39  * are met:
40  * 1. Redistributions of source code must retain the above copyright
41  *    notice, this list of conditions and the following disclaimer.
42  * 2. The name of the developer may NOT be used to endorse or promote products
43  *    derived from this software without specific prior written permission.
44  *
45  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
46  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
47  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
48  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
49  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
50  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
51  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
52  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
53  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
54  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
55  * SUCH DAMAGE.
56  */
57 
58 /*
59  * Support for the SiS 85c503 PCI-ISA bridge interrupt controller.
60  */
61 
62 #include <sys/cdefs.h>
63 __KERNEL_RCSID(0, "$NetBSD: sis85c503.c,v 1.10 2011/07/01 17:37:27 dyoung Exp $");
64 
65 #include <sys/param.h>
66 #include <sys/systm.h>
67 #include <sys/device.h>
68 
69 #include <machine/intr.h>
70 #include <sys/bus.h>
71 
72 #include <dev/pci/pcivar.h>
73 #include <dev/pci/pcireg.h>
74 #include <dev/pci/pcidevs.h>
75 
76 #include <i386/pci/pci_intr_fixup.h>
77 #include <i386/pci/sis85c503reg.h>
78 #include <i386/pci/piixvar.h>
79 
80 int	sis85c503_getclink(pciintr_icu_handle_t, int, int *);
81 int	sis85c503_get_intr(pciintr_icu_handle_t, int, int *);
82 int	sis85c503_set_intr(pciintr_icu_handle_t, int, int);
83 
84 const struct pciintr_icu sis85c503_pci_icu = {
85 	sis85c503_getclink,
86 	sis85c503_get_intr,
87 	sis85c503_set_intr,
88 	piix_get_trigger,
89 	piix_set_trigger,
90 };
91 
92 int
sis85c503_init(pci_chipset_tag_t pc,bus_space_tag_t iot,pcitag_t tag,pciintr_icu_tag_t * ptagp,pciintr_icu_handle_t * phandp)93 sis85c503_init(pci_chipset_tag_t pc, bus_space_tag_t iot, pcitag_t tag,
94     pciintr_icu_tag_t *ptagp, pciintr_icu_handle_t *phandp)
95 {
96 
97 	if (piix_init(pc, iot, tag, ptagp, phandp) == 0) {
98 		*ptagp = &sis85c503_pci_icu;
99 		return (0);
100 	}
101 
102 	return (1);
103 }
104 
105 int
sis85c503_getclink(pciintr_icu_handle_t v,int link,int * clinkp)106 sis85c503_getclink(pciintr_icu_handle_t v, int link, int *clinkp)
107 {
108 
109 	/* Pattern 1: simple. */
110 	if (link >= 1 && link <= 4) {
111 		*clinkp = SIS85C503_CFG_PIRQ_REGSTART + link - 1;
112 		return (0);
113 	}
114 
115 	/* Pattern 2: configuration register offset */
116 	if (link >= SIS85C503_CFG_PIRQ_REGSTART &&
117 	    link <= SIS85C503_CFG_PIRQ_REGEND) {
118 		*clinkp = link;
119 		return (0);
120 	}
121 
122 	return (1);
123 }
124 
125 int
sis85c503_get_intr(pciintr_icu_handle_t v,int clink,int * irqp)126 sis85c503_get_intr(pciintr_icu_handle_t v, int clink, int *irqp)
127 {
128 	struct piix_handle *ph = v;
129 	pcireg_t reg;
130 
131 	if (SIS85C503_LEGAL_LINK(clink) == 0)
132 		return (1);
133 
134 	reg = pci_conf_read(ph->ph_pc, ph->ph_tag,
135 	    SIS85C503_CFG_PIRQ_REGOFS(clink));
136 	reg = SIS85C503_CFG_PIRQ_REG(reg, clink);
137 
138 	if (reg & SIS85C503_CFG_PIRQ_ROUTE_DISABLE)
139 		*irqp = X86_PCI_INTERRUPT_LINE_NO_CONNECTION;
140 	else
141 		*irqp = reg & SIS85C503_CFG_PIRQ_INTR_MASK;
142 
143 	return (0);
144 }
145 
146 int
sis85c503_set_intr(pciintr_icu_handle_t v,int clink,int irq)147 sis85c503_set_intr(pciintr_icu_handle_t v, int clink, int irq)
148 {
149 	struct piix_handle *ph = v;
150 	int shift;
151 	pcireg_t reg;
152 
153 	if (SIS85C503_LEGAL_LINK(clink) == 0 || SIS85C503_LEGAL_IRQ(irq) == 0)
154 		return (1);
155 
156 	reg = pci_conf_read(ph->ph_pc, ph->ph_tag,
157 	    SIS85C503_CFG_PIRQ_REGOFS(clink));
158 	shift = SIS85C503_CFG_PIRQ_SHIFT(clink);
159 	reg &= ~((SIS85C503_CFG_PIRQ_ROUTE_DISABLE |
160 	    SIS85C503_CFG_PIRQ_INTR_MASK) << shift);
161 	reg |= (irq << shift);
162 	pci_conf_write(ph->ph_pc, ph->ph_tag, SIS85C503_CFG_PIRQ_REGOFS(clink),
163 	    reg);
164 
165 	return (0);
166 }
167