xref: /netbsd-src/sys/dev/pci/siop_pci_common.c (revision 13d4bb4cc874de96add7fc4227d38a1d656b03d1) 
1 /*	$NetBSD: siop_pci_common.c,v 1.38 2022/09/25 17:52:25 thorpej Exp $	*/
2 
3 /*
4  * Copyright (c) 2000 Manuel Bouyer.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25  */
26 
27 /* SYM53c8xx PCI-SCSI I/O Processors driver: PCI front-end */
28 
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: siop_pci_common.c,v 1.38 2022/09/25 17:52:25 thorpej Exp $");
31 
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/device.h>
35 #include <sys/buf.h>
36 #include <sys/kernel.h>
37 
38 #include <machine/endian.h>
39 
40 #include <dev/pci/pcireg.h>
41 #include <dev/pci/pcivar.h>
42 #include <dev/pci/pcidevs.h>
43 
44 #include <dev/scsipi/scsipi_all.h>
45 #include <dev/scsipi/scsipiconf.h>
46 
47 #include <dev/ic/siopreg.h>
48 #include <dev/ic/siopvar_common.h>
49 #include <dev/pci/siop_pci_common.h>
50 
51 /* List (array, really :) of chips we know how to handle */
52 static const struct siop_product_desc siop_products[] = {
53 	{ PCI_PRODUCT_SYMBIOS_810,
54 	0x00,
55 	"Symbios Logic 53c810 (fast scsi)",
56 	SF_PCI_RL | SF_CHIP_LS,
57 	4, 8, 3, 250, 0
58 	},
59 	{ PCI_PRODUCT_SYMBIOS_810,
60 	0x10,
61 	"Symbios Logic 53c810a (fast scsi)",
62 	SF_PCI_RL | SF_PCI_BOF | SF_CHIP_PF | SF_CHIP_LS,
63 	4, 8, 3, 250, 0
64 	},
65 	{ PCI_PRODUCT_SYMBIOS_810AP,
66 	0x00,
67 	"Symbios Logic 53c810ap (fast scsi)",
68 	SF_PCI_RL | SF_PCI_BOF | SF_CHIP_PF | SF_CHIP_LS,
69 	4, 8, 3, 250, 0
70 	},
71 	{ PCI_PRODUCT_SYMBIOS_815,
72 	0x00,
73 	"Symbios Logic 53c815 (fast scsi)",
74 	SF_PCI_RL | SF_PCI_BOF,
75 	4, 8, 3, 250, 0
76 	},
77 	{ PCI_PRODUCT_SYMBIOS_820,
78 	0x00,
79 	"Symbios Logic 53c820 (fast wide scsi)",
80 	SF_PCI_RL | SF_CHIP_LS | SF_BUS_WIDE,
81 	4, 8, 3, 250, 0
82 	},
83 	{ PCI_PRODUCT_SYMBIOS_825,
84 	0x00,
85 	"Symbios Logic 53c825 (fast wide scsi)",
86 	SF_PCI_RL | SF_PCI_BOF | SF_BUS_WIDE,
87 	4, 8, 3, 250, 0
88 	},
89 	{ PCI_PRODUCT_SYMBIOS_825,
90 	0x10,
91 	"Symbios Logic 53c825a (fast wide scsi)",
92 	SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
93 	SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_LS | SF_CHIP_10REGS |
94 	SF_BUS_WIDE,
95 	7, 8, 3, 250, 4096
96 	},
97 	{ PCI_PRODUCT_SYMBIOS_860,
98 	0x00,
99 	"Symbios Logic 53c860 (ultra scsi)",
100 	SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
101 	SF_CHIP_PF | SF_CHIP_LS |
102 	SF_BUS_ULTRA,
103 	4, 8, 5, 125, 0
104 	},
105 	{ PCI_PRODUCT_SYMBIOS_875,
106 	0x00,
107 	"Symbios Logic 53c875 (ultra-wide scsi)",
108 	SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
109 	SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_LS | SF_CHIP_10REGS |
110 	SF_BUS_ULTRA | SF_BUS_WIDE,
111 	7, 16, 5, 125, 4096
112 	},
113 	{ PCI_PRODUCT_SYMBIOS_875,
114 	0x02,
115 	"Symbios Logic 53c875 (ultra-wide scsi)",
116 	SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
117 	SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR |
118 	SF_CHIP_LS | SF_CHIP_10REGS |
119 	SF_BUS_ULTRA | SF_BUS_WIDE,
120 	7, 16, 5, 125, 4096
121 	},
122 	{ PCI_PRODUCT_SYMBIOS_875J,
123 	0x00,
124 	"Symbios Logic 53c875j (ultra-wide scsi)",
125 	SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
126 	SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR |
127 	SF_CHIP_LS | SF_CHIP_10REGS |
128 	SF_BUS_ULTRA | SF_BUS_WIDE,
129 	7, 16, 5, 125, 4096
130 	},
131 	{ PCI_PRODUCT_SYMBIOS_885,
132 	0x00,
133 	"Symbios Logic 53c885 (ultra-wide scsi)",
134 	SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
135 	SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR |
136 	SF_CHIP_LS | SF_CHIP_10REGS |
137 	SF_BUS_ULTRA | SF_BUS_WIDE,
138 	7, 16, 5, 125, 4096
139 	},
140 	{ PCI_PRODUCT_SYMBIOS_895,
141 	0x00,
142 	"Symbios Logic 53c895 (ultra2-wide scsi)",
143 	SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
144 	SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD |
145 	SF_CHIP_LS | SF_CHIP_10REGS |
146 	SF_BUS_ULTRA2 | SF_BUS_WIDE,
147 	7, 31, 7, 62, 4096
148 	},
149 	{ PCI_PRODUCT_SYMBIOS_896,
150 	0x00,
151 	"Symbios Logic 53c896 (ultra2-wide scsi)",
152 	SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
153 	SF_CHIP_LEDC | SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD |
154 	SF_CHIP_LS | SF_CHIP_10REGS |
155 	SF_BUS_ULTRA2 | SF_BUS_WIDE,
156 	7, 31, 7, 62, 8192
157 	},
158 	{ PCI_PRODUCT_SYMBIOS_895A,
159 	0x00,
160 	"Symbios Logic 53c895a (ultra2-wide scsi)",
161 	SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
162 	SF_CHIP_LEDC | SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD |
163 	SF_CHIP_LS | SF_CHIP_10REGS |
164 	SF_BUS_ULTRA2 | SF_BUS_WIDE,
165 	7, 31, 7, 62, 8192
166 	},
167 	{ PCI_PRODUCT_SYMBIOS_1010,
168 	0x00,
169 	"Symbios Logic 53c1010-33 rev 0 (ultra3-wide scsi)",
170 	SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
171 	SF_CHIP_LEDC | SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM |
172 	SF_CHIP_LS | SF_CHIP_10REGS | SF_CHIP_DFBC | SF_CHIP_DBLR |
173 	SF_CHIP_GEBUG |
174 	SF_BUS_ULTRA3 | SF_BUS_WIDE,
175 	7, 31, 0, 62, 8192
176 	},
177 	{ PCI_PRODUCT_SYMBIOS_1010,
178 	0x01,
179 	"Symbios Logic 53c1010-33 (ultra3-wide scsi)",
180 	SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
181 	SF_CHIP_LEDC | SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM |
182 	SF_CHIP_LS | SF_CHIP_10REGS | SF_CHIP_DFBC | SF_CHIP_DBLR | SF_CHIP_DT |
183 	SF_CHIP_GEBUG |
184 	SF_BUS_ULTRA3 | SF_BUS_WIDE,
185 	7, 62, 0, 62, 8192
186 	},
187 	{ PCI_PRODUCT_SYMBIOS_1010_2,
188 	0x00,
189 	"Symbios Logic 53c1010-66 (ultra3-wide scsi)",
190 	SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
191 	SF_CHIP_LEDC | SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM |
192 	SF_CHIP_LS | SF_CHIP_10REGS | SF_CHIP_DFBC | SF_CHIP_DBLR | SF_CHIP_DT |
193 	SF_CHIP_AAIP |
194 	SF_BUS_ULTRA3 | SF_BUS_WIDE,
195 	7, 62, 0, 62, 8192
196 	},
197 	{ PCI_PRODUCT_SYMBIOS_1510D,
198 	0x00,
199 	"Symbios Logic 53c1510d (ultra2-wide scsi)",
200 	SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
201 	SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD |
202 	SF_CHIP_LS | SF_CHIP_10REGS |
203 	SF_BUS_ULTRA2 | SF_BUS_WIDE,
204 	7, 31, 7, 62, 4096
205 	},
206 	{ 0,
207 	0x00,
208 	NULL,
209 	0x00,
210 	0, 0, 0, 0, 0
211 	},
212 };
213 
214 const struct siop_product_desc *
siop_lookup_product(uint32_t id,int rev)215 siop_lookup_product(uint32_t id, int rev)
216 {
217 	const struct siop_product_desc *pp;
218 	const struct siop_product_desc *rp = NULL;
219 
220 	if (PCI_VENDOR(id) != PCI_VENDOR_SYMBIOS)
221 		return NULL;
222 
223 	for (pp = siop_products; pp->name != NULL; pp++) {
224 		if (PCI_PRODUCT(id) == pp->product && pp->revision <= rev)
225 			if (rp == NULL || pp->revision > rp->revision)
226 				rp = pp;
227 	}
228 	return rp;
229 }
230 
231 int
siop_pci_attach_common(struct siop_pci_common_softc * pci_sc,struct siop_common_softc * siop_sc,struct pci_attach_args * pa,int (* intr)(void *))232 siop_pci_attach_common(struct siop_pci_common_softc *pci_sc,
233     struct siop_common_softc *siop_sc, struct pci_attach_args *pa,
234     int (*intr)(void *))
235 {
236 	pci_chipset_tag_t pc = pa->pa_pc;
237 	pcitag_t tag = pa->pa_tag;
238 	const char *intrstr;
239 	pci_intr_handle_t intrhandle;
240 	bus_space_tag_t iot, memt;
241 	bus_space_handle_t ioh, memh;
242 	pcireg_t memtype;
243 	prop_dictionary_t dict;
244 	int memh_valid, ioh_valid;
245 	bus_addr_t ioaddr, memaddr;
246 	bool use_pciclock;
247 	char intrbuf[PCI_INTRSTR_LEN];
248 
249 	aprint_naive(": SCSI controller\n");
250 
251 	pci_sc->sc_pp =
252 	    siop_lookup_product(pa->pa_id, PCI_REVISION(pa->pa_class));
253 	if (pci_sc->sc_pp == NULL) {
254 		aprint_error("sym: broken match/attach!!\n");
255 		return 0;
256 	}
257 	/* copy interesting infos about the chip */
258 	siop_sc->features = pci_sc->sc_pp->features;
259 #ifdef SIOP_SYMLED    /* XXX Should be a devprop! */
260 	siop_sc->features |= SF_CHIP_LED0;
261 #endif
262 	dict = device_properties(siop_sc->sc_dev);
263 	if (prop_dictionary_get_bool(dict, "use_pciclock", &use_pciclock))
264 		if (use_pciclock)
265 			siop_sc->features |= SF_CHIP_USEPCIC;
266 	siop_sc->maxburst = pci_sc->sc_pp->maxburst;
267 	siop_sc->maxoff = pci_sc->sc_pp->maxoff;
268 	siop_sc->clock_div = pci_sc->sc_pp->clock_div;
269 	siop_sc->clock_period = pci_sc->sc_pp->clock_period;
270 	siop_sc->ram_size = pci_sc->sc_pp->ram_size;
271 
272 	siop_sc->sc_reset = siop_pci_reset;
273 	aprint_normal(": %s\n", pci_sc->sc_pp->name);
274 	pci_sc->sc_pc = pc;
275 	pci_sc->sc_tag = tag;
276 	siop_sc->sc_dmat = pa->pa_dmat;
277 
278 	memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 0x14);
279 	switch (memtype) {
280 	case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
281 	case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
282 		memh_valid = (pci_mapreg_map(pa, 0x14, memtype, 0,
283 		    &memt, &memh, &memaddr, NULL) == 0);
284 		break;
285 	default:
286 		memh_valid = 0;
287 	}
288 
289 	ioh_valid = (pci_mapreg_map(pa, 0x10, PCI_MAPREG_TYPE_IO, 0,
290 	    &iot, &ioh, &ioaddr, NULL) == 0);
291 
292 	if (memh_valid) {
293 		siop_sc->sc_rt = memt;
294 		siop_sc->sc_rh = memh;
295 		siop_sc->sc_raddr = memaddr;
296 	} else if (ioh_valid) {
297 		siop_sc->sc_rt = iot;
298 		siop_sc->sc_rh = ioh;
299 		siop_sc->sc_raddr = ioaddr;
300 	} else {
301 		aprint_error_dev(siop_sc->sc_dev,
302 		    "unable to map device registers\n");
303 		return 0;
304 	}
305 
306 	if (siop_sc->features & SF_CHIP_RAM) {
307 		int bar;
308 		switch (memtype) {
309 		case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
310 			bar = 0x18;
311 			break;
312 		case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
313 			bar = 0x1c;
314 			break;
315 		default:
316 			aprint_error_dev(siop_sc->sc_dev,
317 			    "invalid memory type %d\n",
318 			    memtype);
319 			return 0;
320 		}
321 		if (pci_mapreg_map(pa, bar, memtype, 0,
322                     &siop_sc->sc_ramt, &siop_sc->sc_ramh,
323 		    &siop_sc->sc_scriptaddr, NULL) == 0) {
324 			aprint_normal_dev(siop_sc->sc_dev,
325 			    "using on-board RAM\n");
326 		} else {
327 			aprint_error_dev(siop_sc->sc_dev,
328 			    "can't map on-board RAM\n");
329 			siop_sc->features &= ~SF_CHIP_RAM;
330 		}
331 	}
332 
333 	if (pci_intr_map(pa, &intrhandle) != 0) {
334 		aprint_error_dev(siop_sc->sc_dev, "couldn't map interrupt\n");
335 		return 0;
336 	}
337 	intrstr = pci_intr_string(pa->pa_pc, intrhandle, intrbuf, sizeof(intrbuf));
338 	pci_sc->sc_ih = pci_intr_establish_xname(pa->pa_pc, intrhandle, IPL_BIO,
339 	    intr, siop_sc, device_xname(siop_sc->sc_dev));
340 	if (pci_sc->sc_ih != NULL) {
341 		aprint_normal_dev(siop_sc->sc_dev, "interrupting at %s\n",
342 		    intrstr ? intrstr : "unknown interrupt");
343 	} else {
344 		aprint_error_dev(siop_sc->sc_dev,
345 		    "couldn't establish interrupt");
346 		if (intrstr != NULL)
347 			aprint_error(" at %s", intrstr);
348 		aprint_error("\n");
349 		return 0;
350 	}
351 	pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
352 	    pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) |
353 	    PCI_COMMAND_MASTER_ENABLE);
354 	return 1;
355 }
356 
357 void
siop_pci_reset(struct siop_common_softc * sc)358 siop_pci_reset(struct siop_common_softc *sc)
359 {
360 	int dmode;
361 
362 	dmode = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DMODE);
363 	if (sc->features & SF_PCI_RL)
364 		dmode |= DMODE_ERL;
365 	if (sc->features & SF_PCI_RM)
366 		dmode |= DMODE_ERMP;
367 	if (sc->features & SF_PCI_BOF)
368 		dmode |= DMODE_BOF;
369 	if (sc->features & SF_PCI_CLS)
370 		bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DCNTL,
371 		    bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DCNTL) |
372 		    DCNTL_CLSE);
373 	if (sc->features & SF_PCI_WRI)
374 		bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3,
375 		    bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3) |
376 		    CTEST3_WRIE);
377 	if (sc->maxburst) {
378 		int ctest5 = bus_space_read_1(sc->sc_rt, sc->sc_rh,
379 		    SIOP_CTEST5);
380 		bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4,
381 		    bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4) &
382 		    ~CTEST4_BDIS);
383 		dmode &= ~DMODE_BL_MASK;
384 		dmode |= ((sc->maxburst - 1) << DMODE_BL_SHIFT) & DMODE_BL_MASK;
385 		ctest5 &= ~CTEST5_BBCK;
386 		ctest5 |= (sc->maxburst - 1) & CTEST5_BBCK;
387 		bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5, ctest5);
388 	} else {
389 		bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4,
390 		    bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4) |
391 		    CTEST4_BDIS);
392 	}
393 	bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DMODE, dmode);
394 }
395