1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) 2 * Copyright(c) 2015-2018 Intel Corporation 3 */ 4 #ifndef _ICP_QAT_FW_H_ 5 #define _ICP_QAT_FW_H_ 6 #include <sys/types.h> 7 8 #define QAT_FIELD_SET(flags, val, bitpos, mask) \ 9 { (flags) = (((flags) & (~((mask) << (bitpos)))) | \ 10 (((val) & (mask)) << (bitpos))) ; } 11 12 #define QAT_FIELD_GET(flags, bitpos, mask) \ 13 (((flags) >> (bitpos)) & (mask)) 14 15 #define ICP_QAT_FW_REQ_DEFAULT_SZ 128 16 #define ICP_QAT_FW_RESP_DEFAULT_SZ 32 17 #define ICP_QAT_FW_COMN_ONE_BYTE_SHIFT 8 18 #define ICP_QAT_FW_COMN_SINGLE_BYTE_MASK 0xFF 19 #define ICP_QAT_FW_NUM_LONGWORDS_1 1 20 #define ICP_QAT_FW_NUM_LONGWORDS_2 2 21 #define ICP_QAT_FW_NUM_LONGWORDS_3 3 22 #define ICP_QAT_FW_NUM_LONGWORDS_4 4 23 #define ICP_QAT_FW_NUM_LONGWORDS_5 5 24 #define ICP_QAT_FW_NUM_LONGWORDS_6 6 25 #define ICP_QAT_FW_NUM_LONGWORDS_7 7 26 #define ICP_QAT_FW_NUM_LONGWORDS_10 10 27 #define ICP_QAT_FW_NUM_LONGWORDS_13 13 28 #define ICP_QAT_FW_NULL_REQ_SERV_ID 1 29 30 enum icp_qat_fw_comn_resp_serv_id { 31 ICP_QAT_FW_COMN_RESP_SERV_NULL, 32 ICP_QAT_FW_COMN_RESP_SERV_CPM_FW, 33 ICP_QAT_FW_COMN_RESP_SERV_DELIMITER 34 }; 35 36 enum icp_qat_fw_comn_request_id { 37 ICP_QAT_FW_COMN_REQ_NULL = 0, 38 ICP_QAT_FW_COMN_REQ_CPM_FW_PKE = 3, 39 ICP_QAT_FW_COMN_REQ_CPM_FW_LA = 4, 40 ICP_QAT_FW_COMN_REQ_CPM_FW_DMA = 7, 41 ICP_QAT_FW_COMN_REQ_CPM_FW_COMP = 9, 42 ICP_QAT_FW_COMN_REQ_DELIMITER 43 }; 44 45 struct icp_qat_fw_comn_req_hdr_cd_pars { 46 union { 47 struct { 48 uint64_t content_desc_addr; 49 uint16_t content_desc_resrvd1; 50 uint8_t content_desc_params_sz; 51 uint8_t content_desc_hdr_resrvd2; 52 uint32_t content_desc_resrvd3; 53 } s; 54 struct { 55 uint32_t serv_specif_fields[4]; 56 } s1; 57 } u; 58 }; 59 60 struct lce_key_buff_desc { 61 uint64_t keybuff; 62 uint32_t keybuff_resrvd1; 63 uint32_t keybuff_resrvd2; 64 }; 65 66 struct icp_qat_fw_comn_req_mid { 67 uint64_t opaque_data; 68 uint64_t src_data_addr; 69 uint64_t dest_data_addr; 70 uint32_t src_length; 71 uint32_t dst_length; 72 }; 73 74 struct icp_qat_fw_comn_req_cd_ctrl { 75 uint32_t content_desc_ctrl_lw[ICP_QAT_FW_NUM_LONGWORDS_5]; 76 }; 77 78 struct icp_qat_fw_comn_req_hdr { 79 uint8_t resrvd1; 80 uint8_t service_cmd_id; 81 uint8_t service_type; 82 uint8_t hdr_flags; 83 uint16_t serv_specif_flags; 84 uint8_t comn_req_flags; 85 uint8_t ext_flags; 86 }; 87 88 struct icp_qat_fw_comn_req_rqpars { 89 uint32_t serv_specif_rqpars_lw[ICP_QAT_FW_NUM_LONGWORDS_13]; 90 }; 91 92 struct icp_qat_fw_comn_req { 93 struct icp_qat_fw_comn_req_hdr comn_hdr; 94 struct icp_qat_fw_comn_req_hdr_cd_pars cd_pars; 95 struct icp_qat_fw_comn_req_mid comn_mid; 96 struct icp_qat_fw_comn_req_rqpars serv_specif_rqpars; 97 struct icp_qat_fw_comn_req_cd_ctrl cd_ctrl; 98 }; 99 100 struct icp_qat_fw_comn_error { 101 uint8_t xlat_err_code; 102 uint8_t cmp_err_code; 103 }; 104 105 struct icp_qat_fw_comn_resp_hdr { 106 uint8_t resrvd1; 107 uint8_t service_id; 108 uint8_t response_type; 109 uint8_t hdr_flags; 110 struct icp_qat_fw_comn_error comn_error; 111 uint8_t comn_status; 112 uint8_t cmd_id; 113 }; 114 115 struct icp_qat_fw_comn_resp { 116 struct icp_qat_fw_comn_resp_hdr comn_hdr; 117 uint64_t opaque_data; 118 uint32_t resrvd[ICP_QAT_FW_NUM_LONGWORDS_4]; 119 }; 120 121 #define ICP_QAT_FW_COMN_REQ_FLAG_SET 1 122 #define ICP_QAT_FW_COMN_REQ_FLAG_CLR 0 123 #define ICP_QAT_FW_COMN_VALID_FLAG_BITPOS 7 124 #define ICP_QAT_FW_COMN_VALID_FLAG_MASK 0x1 125 #define ICP_QAT_FW_COMN_HDR_RESRVD_FLD_MASK 0x7F 126 #define ICP_QAT_FW_COMN_CNV_FLAG_BITPOS 6 127 #define ICP_QAT_FW_COMN_CNV_FLAG_MASK 0x1 128 #define ICP_QAT_FW_COMN_CNVNR_FLAG_BITPOS 5 129 #define ICP_QAT_FW_COMN_CNVNR_FLAG_MASK 0x1 130 #define ICP_QAT_FW_COMN_NULL_VERSION_FLAG_BITPOS 0 131 #define ICP_QAT_FW_COMN_NULL_VERSION_FLAG_MASK 0x1 132 133 /* GEN_LCE specific Common Header fields */ 134 #define ICP_QAT_FW_COMN_DESC_LAYOUT_BITPOS 5 135 #define ICP_QAT_FW_COMN_DESC_LAYOUT_MASK 0x3 136 #define ICP_QAT_FW_COMN_GEN_LCE_DESC_LAYOUT 3 137 #define ICP_QAT_FW_COMN_GEN_LCE_STATUS_FLAG_ERROR 0 138 139 #define ICP_QAT_FW_COMN_OV_SRV_TYPE_GET(icp_qat_fw_comn_req_hdr_t) \ 140 icp_qat_fw_comn_req_hdr_t.service_type 141 142 #define ICP_QAT_FW_COMN_OV_SRV_TYPE_SET(icp_qat_fw_comn_req_hdr_t, val) \ 143 icp_qat_fw_comn_req_hdr_t.service_type = val 144 145 #define ICP_QAT_FW_COMN_OV_SRV_CMD_ID_GET(icp_qat_fw_comn_req_hdr_t) \ 146 icp_qat_fw_comn_req_hdr_t.service_cmd_id 147 148 #define ICP_QAT_FW_COMN_OV_SRV_CMD_ID_SET(icp_qat_fw_comn_req_hdr_t, val) \ 149 icp_qat_fw_comn_req_hdr_t.service_cmd_id = val 150 151 #define ICP_QAT_FW_COMN_HDR_VALID_FLAG_GET(hdr_t) \ 152 ICP_QAT_FW_COMN_VALID_FLAG_GET(hdr_t.hdr_flags) 153 154 #define ICP_QAT_FW_COMN_HDR_CNVNR_FLAG_GET(hdr_flags) \ 155 QAT_FIELD_GET(hdr_flags, \ 156 ICP_QAT_FW_COMN_CNVNR_FLAG_BITPOS, \ 157 ICP_QAT_FW_COMN_CNVNR_FLAG_MASK) 158 159 #define ICP_QAT_FW_COMN_HDR_CNV_FLAG_GET(hdr_flags) \ 160 QAT_FIELD_GET(hdr_flags, \ 161 ICP_QAT_FW_COMN_CNV_FLAG_BITPOS, \ 162 ICP_QAT_FW_COMN_CNV_FLAG_MASK) 163 164 #define ICP_QAT_FW_COMN_HDR_VALID_FLAG_SET(hdr_t, val) \ 165 ICP_QAT_FW_COMN_VALID_FLAG_SET(hdr_t, val) 166 167 #define ICP_QAT_FW_COMN_VALID_FLAG_GET(hdr_flags) \ 168 QAT_FIELD_GET(hdr_flags, \ 169 ICP_QAT_FW_COMN_VALID_FLAG_BITPOS, \ 170 ICP_QAT_FW_COMN_VALID_FLAG_MASK) 171 172 #define ICP_QAT_FW_COMN_HDR_RESRVD_FLD_GET(hdr_flags) \ 173 (hdr_flags & ICP_QAT_FW_COMN_HDR_RESRVD_FLD_MASK) 174 175 #define ICP_QAT_FW_COMN_VALID_FLAG_SET(hdr_t, val) \ 176 QAT_FIELD_SET((hdr_t.hdr_flags), (val), \ 177 ICP_QAT_FW_COMN_VALID_FLAG_BITPOS, \ 178 ICP_QAT_FW_COMN_VALID_FLAG_MASK) 179 180 #define ICP_QAT_FW_COMN_HDR_FLAGS_BUILD(valid) \ 181 (((valid) & ICP_QAT_FW_COMN_VALID_FLAG_MASK) << \ 182 ICP_QAT_FW_COMN_VALID_FLAG_BITPOS) 183 184 #define ICP_QAT_FW_COMN_HDR_FLAGS_BUILD_GEN_LCE(valid, desc_layout) \ 185 ((((valid) & ICP_QAT_FW_COMN_VALID_FLAG_MASK) << \ 186 ICP_QAT_FW_COMN_VALID_FLAG_BITPOS) | \ 187 (((desc_layout) & ICP_QAT_FW_COMN_DESC_LAYOUT_MASK) << \ 188 ICP_QAT_FW_COMN_DESC_LAYOUT_BITPOS)) 189 190 #define QAT_COMN_PTR_TYPE_BITPOS 0 191 #define QAT_COMN_PTR_TYPE_MASK 0x1 192 #define QAT_COMN_CD_FLD_TYPE_BITPOS 1 193 #define QAT_COMN_CD_FLD_TYPE_MASK 0x1 194 #define QAT_COMN_PTR_TYPE_FLAT 0x0 195 #define QAT_COMN_PTR_TYPE_SGL 0x1 196 #define QAT_COMN_CD_FLD_TYPE_64BIT_ADR 0x0 197 #define QAT_COMN_CD_FLD_TYPE_16BYTE_DATA 0x1 198 199 /* GEN_LCE specific Common Request Flags fields */ 200 #define QAT_COMN_KEYBUF_USAGE_BITPOS 1 201 #define QAT_COMN_KEYBUF_USAGE_MASK 0x1 202 #define QAT_COMN_KEY_BUFFER_USED 1 203 204 #define ICP_QAT_FW_COMN_FLAGS_BUILD(cdt, ptr) \ 205 ((((cdt) & QAT_COMN_CD_FLD_TYPE_MASK) << QAT_COMN_CD_FLD_TYPE_BITPOS) \ 206 | (((ptr) & QAT_COMN_PTR_TYPE_MASK) << QAT_COMN_PTR_TYPE_BITPOS)) 207 208 #define ICP_QAT_FW_COMN_FLAGS_BUILD_GEN_LCE(ptr, keybuf) \ 209 ((((ptr) & QAT_COMN_PTR_TYPE_MASK) << QAT_COMN_PTR_TYPE_BITPOS) | \ 210 (((keybuf) & QAT_COMN_PTR_TYPE_MASK) << \ 211 QAT_COMN_KEYBUF_USAGE_BITPOS)) 212 213 #define ICP_QAT_FW_COMN_PTR_TYPE_GET(flags) \ 214 QAT_FIELD_GET(flags, QAT_COMN_PTR_TYPE_BITPOS, QAT_COMN_PTR_TYPE_MASK) 215 216 #define ICP_QAT_FW_COMN_CD_FLD_TYPE_GET(flags) \ 217 QAT_FIELD_GET(flags, QAT_COMN_CD_FLD_TYPE_BITPOS, \ 218 QAT_COMN_CD_FLD_TYPE_MASK) 219 220 #define ICP_QAT_FW_COMN_PTR_TYPE_SET(flags, val) \ 221 QAT_FIELD_SET(flags, val, QAT_COMN_PTR_TYPE_BITPOS, \ 222 QAT_COMN_PTR_TYPE_MASK) 223 224 #define ICP_QAT_FW_COMN_CD_FLD_TYPE_SET(flags, val) \ 225 QAT_FIELD_SET(flags, val, QAT_COMN_CD_FLD_TYPE_BITPOS, \ 226 QAT_COMN_CD_FLD_TYPE_MASK) 227 228 #define ICP_QAT_FW_COMN_NEXT_ID_BITPOS 4 229 #define ICP_QAT_FW_COMN_NEXT_ID_MASK 0xF0 230 #define ICP_QAT_FW_COMN_CURR_ID_BITPOS 0 231 #define ICP_QAT_FW_COMN_CURR_ID_MASK 0x0F 232 233 #define ICP_QAT_FW_COMN_NEXT_ID_GET(cd_ctrl_hdr_t) \ 234 ((((cd_ctrl_hdr_t)->next_curr_id) & ICP_QAT_FW_COMN_NEXT_ID_MASK) \ 235 >> (ICP_QAT_FW_COMN_NEXT_ID_BITPOS)) 236 237 #define ICP_QAT_FW_COMN_NEXT_ID_SET(cd_ctrl_hdr_t, val) \ 238 { ((cd_ctrl_hdr_t)->next_curr_id) = ((((cd_ctrl_hdr_t)->next_curr_id) \ 239 & ICP_QAT_FW_COMN_CURR_ID_MASK) | \ 240 ((val << ICP_QAT_FW_COMN_NEXT_ID_BITPOS) \ 241 & ICP_QAT_FW_COMN_NEXT_ID_MASK)); } 242 243 #define ICP_QAT_FW_COMN_CURR_ID_GET(cd_ctrl_hdr_t) \ 244 (((cd_ctrl_hdr_t)->next_curr_id) & ICP_QAT_FW_COMN_CURR_ID_MASK) 245 246 #define ICP_QAT_FW_COMN_CURR_ID_SET(cd_ctrl_hdr_t, val) \ 247 { ((cd_ctrl_hdr_t)->next_curr_id) = ((((cd_ctrl_hdr_t)->next_curr_id) \ 248 & ICP_QAT_FW_COMN_NEXT_ID_MASK) | \ 249 ((val) & ICP_QAT_FW_COMN_CURR_ID_MASK)); } 250 251 #define ICP_QAT_FW_COMN_NEXT_ID_SET_2(next_curr_id, val) \ 252 do { \ 253 (next_curr_id) = \ 254 (((next_curr_id) & ICP_QAT_FW_COMN_CURR_ID_MASK) | \ 255 (((val) << ICP_QAT_FW_COMN_NEXT_ID_BITPOS) & \ 256 ICP_QAT_FW_COMN_NEXT_ID_MASK)) \ 257 } while (0) 258 259 #define ICP_QAT_FW_COMN_CURR_ID_SET_2(next_curr_id, val) \ 260 do { \ 261 (next_curr_id) = \ 262 (((next_curr_id) & ICP_QAT_FW_COMN_NEXT_ID_MASK) | \ 263 ((val) & ICP_QAT_FW_COMN_CURR_ID_MASK)) \ 264 } while (0) 265 266 #define QAT_COMN_RESP_CRYPTO_STATUS_BITPOS 7 267 #define QAT_COMN_RESP_CRYPTO_STATUS_MASK 0x1 268 #define QAT_COMN_RESP_PKE_STATUS_BITPOS 6 269 #define QAT_COMN_RESP_PKE_STATUS_MASK 0x1 270 #define QAT_COMN_RESP_CMP_STATUS_BITPOS 5 271 #define QAT_COMN_RESP_CMP_STATUS_MASK 0x1 272 #define QAT_COMN_RESP_XLAT_STATUS_BITPOS 4 273 #define QAT_COMN_RESP_XLAT_STATUS_MASK 0x1 274 #define QAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS 3 275 #define QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK 0x1 276 #define QAT_COMN_RESP_UNSUPPORTED_REQUEST_BITPOS 2 277 #define QAT_COMN_RESP_UNSUPPORTED_REQUEST_MASK 0x1 278 #define QAT_COMN_RESP_INVALID_PARAM_BITPOS 1 279 #define QAT_COMN_RESP_INVALID_PARAM_MASK 0x1 280 #define QAT_COMN_RESP_XLT_WA_APPLIED_BITPOS 0 281 #define QAT_COMN_RESP_XLT_WA_APPLIED_MASK 0x1 282 283 #define ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(status) \ 284 QAT_FIELD_GET(status, QAT_COMN_RESP_CRYPTO_STATUS_BITPOS, \ 285 QAT_COMN_RESP_CRYPTO_STATUS_MASK) 286 287 #define ICP_QAT_FW_COMN_RESP_PKE_STAT_GET(status) \ 288 QAT_FIELD_GET(status, QAT_COMN_RESP_PKE_STATUS_BITPOS, \ 289 QAT_COMN_RESP_PKE_STATUS_MASK) 290 291 #define ICP_QAT_FW_COMN_RESP_CMP_STAT_GET(status) \ 292 QAT_FIELD_GET(status, QAT_COMN_RESP_CMP_STATUS_BITPOS, \ 293 QAT_COMN_RESP_CMP_STATUS_MASK) 294 295 #define ICP_QAT_FW_COMN_RESP_XLAT_STAT_GET(status) \ 296 QAT_FIELD_GET(status, QAT_COMN_RESP_XLAT_STATUS_BITPOS, \ 297 QAT_COMN_RESP_XLAT_STATUS_MASK) 298 299 #define ICP_QAT_FW_COMN_RESP_XLT_WA_APPLIED_GET(status) \ 300 QAT_FIELD_GET(status, QAT_COMN_RESP_XLT_WA_APPLIED_BITPOS, \ 301 QAT_COMN_RESP_XLT_WA_APPLIED_MASK) 302 303 #define ICP_QAT_FW_COMN_RESP_CMP_END_OF_LAST_BLK_FLAG_GET(status) \ 304 QAT_FIELD_GET(status, QAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS, \ 305 QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK) 306 307 #define ICP_QAT_FW_COMN_RESP_UNSUPPORTED_REQUEST_STAT_GET(status) \ 308 QAT_FIELD_GET(status, QAT_COMN_RESP_UNSUPPORTED_REQUEST_BITPOS, \ 309 QAT_COMN_RESP_UNSUPPORTED_REQUEST_MASK) 310 311 #define ICP_QAT_FW_COMN_RESP_INVALID_PARAM_STAT_GET(status) \ 312 QAT_FIELD_GET(status, QAT_COMN_RESP_INVALID_PARAM_BITPOS, \ 313 QAT_COMN_RESP_INVALID_PARAM_MASK) 314 315 #define ICP_QAT_FW_COMN_STATUS_FLAG_OK 0 316 #define ICP_QAT_FW_COMN_STATUS_FLAG_ERROR 1 317 #define ICP_QAT_FW_COMN_STATUS_CMP_END_OF_LAST_BLK_FLAG_CLR 0 318 #define ICP_QAT_FW_COMN_STATUS_CMP_END_OF_LAST_BLK_FLAG_SET 1 319 #define ERR_CODE_NO_ERROR 0 320 #define ERR_CODE_INVALID_BLOCK_TYPE -1 321 #define ERR_CODE_NO_MATCH_ONES_COMP -2 322 #define ERR_CODE_TOO_MANY_LEN_OR_DIS -3 323 #define ERR_CODE_INCOMPLETE_LEN -4 324 #define ERR_CODE_RPT_LEN_NO_FIRST_LEN -5 325 #define ERR_CODE_RPT_GT_SPEC_LEN -6 326 #define ERR_CODE_INV_LIT_LEN_CODE_LEN -7 327 #define ERR_CODE_INV_DIS_CODE_LEN -8 328 #define ERR_CODE_INV_LIT_LEN_DIS_IN_BLK -9 329 #define ERR_CODE_DIS_TOO_FAR_BACK -10 330 #define ERR_CODE_OVERFLOW_ERROR -11 331 #define ERR_CODE_SOFT_ERROR -12 332 #define ERR_CODE_FATAL_ERROR -13 333 #define ERR_CODE_COMP_OUTPUT_CORRUPTION -14 334 #define ERR_CODE_HW_INCOMPLETE_FILE -15 335 #define ERR_CODE_SSM_ERROR -16 336 #define ERR_CODE_ENDPOINT_ERROR -17 337 #define ERR_CODE_CNV_ERROR -18 338 #define ERR_CODE_EMPTY_DYM_BLOCK -19 339 #define ERR_CODE_KPT_CRYPTO_SERVICE_FAIL_INVALID_HANDLE -20 340 #define ERR_CODE_KPT_CRYPTO_SERVICE_FAIL_HMAC_FAILED -21 341 #define ERR_CODE_KPT_CRYPTO_SERVICE_FAIL_INVALID_WRAPPING_ALGO -22 342 #define ERR_CODE_KPT_DRNG_SEED_NOT_LOAD -23 343 344 enum icp_qat_fw_slice { 345 ICP_QAT_FW_SLICE_NULL = 0, 346 ICP_QAT_FW_SLICE_CIPHER = 1, 347 ICP_QAT_FW_SLICE_AUTH = 2, 348 ICP_QAT_FW_SLICE_DRAM_RD = 3, 349 ICP_QAT_FW_SLICE_DRAM_WR = 4, 350 ICP_QAT_FW_SLICE_COMP = 5, 351 ICP_QAT_FW_SLICE_XLAT = 6, 352 ICP_QAT_FW_SLICE_DELIMITER 353 }; 354 #endif 355