1 /* $NetBSD: sdhc_pci.c,v 1.21 2023/01/05 14:50:14 msaitoh Exp $ */
2 /* $OpenBSD: sdhc_pci.c,v 1.7 2007/10/30 18:13:45 chl Exp $ */
3
4 /*
5 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
6 *
7 * Permission to use, copy, modify, and distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20 #include <sys/cdefs.h>
21 __KERNEL_RCSID(0, "$NetBSD: sdhc_pci.c,v 1.21 2023/01/05 14:50:14 msaitoh Exp $");
22
23 #ifdef _KERNEL_OPT
24 #include "opt_sdmmc.h"
25 #endif
26
27 #include <sys/param.h>
28 #include <sys/device.h>
29 #include <sys/systm.h>
30 #include <sys/malloc.h>
31 #include <sys/pmf.h>
32
33 #include <dev/pci/pcivar.h>
34 #include <dev/pci/pcidevs.h>
35
36 #include <dev/sdmmc/sdhcreg.h>
37 #include <dev/sdmmc/sdhcvar.h>
38 #include <dev/sdmmc/sdmmcvar.h>
39
40 /* PCI base address registers */
41 #define SDHC_PCI_BAR_START PCI_MAPREG_START
42 #define SDHC_PCI_BAR_END PCI_MAPREG_END
43
44 /* PCI interface classes */
45 #define SDHC_PCI_INTERFACE_NO_DMA 0x00
46 #define SDHC_PCI_INTERFACE_DMA 0x01
47 #define SDHC_PCI_INTERFACE_VENDOR 0x02
48
49 /*
50 * 8-bit PCI configuration register that tells us how many slots there
51 * are and which BAR entry corresponds to the first slot.
52 */
53 #define SDHC_PCI_CONF_SLOT_INFO 0x40
54 #define SDHC_PCI_NUM_SLOTS(info) ((((info) >> 4) & 0x7) + 1)
55 #define SDHC_PCI_FIRST_BAR(info) ((info) & 0x7)
56
57 struct sdhc_pci_softc {
58 struct sdhc_softc sc;
59 pci_chipset_tag_t sc_pc;
60 void *sc_ih;
61 };
62
63 static int sdhc_pci_match(device_t, cfdata_t, void *);
64 static void sdhc_pci_attach(device_t, device_t, void *);
65 static int sdhc_pci_detach(device_t, int);
66
67 CFATTACH_DECL_NEW(sdhc_pci, sizeof(struct sdhc_pci_softc),
68 sdhc_pci_match, sdhc_pci_attach, sdhc_pci_detach, NULL);
69
70 #ifdef SDHC_DEBUG
71 #define DPRINTF(s) printf s
72 #else
73 #define DPRINTF(s) /**/
74 #endif
75
76 static const struct sdhc_pci_quirk {
77 pci_vendor_id_t vendor;
78 pci_product_id_t product;
79 pci_vendor_id_t subvendor;
80 pci_product_id_t subproduct;
81 u_int function;
82
83 uint32_t flags;
84 #define SDHC_PCI_QUIRK_FORCE_DMA __BIT(0)
85 #define SDHC_PCI_QUIRK_TI_HACK __BIT(1)
86 #define SDHC_PCI_QUIRK_NO_PWR0 __BIT(2)
87 #define SDHC_PCI_QUIRK_RICOH_LOWER_FREQ_HACK __BIT(3)
88 #define SDHC_PCI_QUIRK_RICOH_SLOW_SDR50_HACK __BIT(4)
89 #define SDHC_PCI_QUIRK_INTEL_EMMC_HW_RESET __BIT(5)
90 #define SDHC_PCI_QUIRK_SINGLE_POWER_WRITE __BIT(6)
91 #define SDHC_PCI_QUIRK_BROKEN_ADMA __BIT(7)
92 } sdhc_pci_quirk_table[] = {
93 {
94 PCI_VENDOR_TI,
95 PCI_PRODUCT_TI_PCI72111SD,
96 0xffff,
97 0xffff,
98 4,
99 SDHC_PCI_QUIRK_TI_HACK
100 },
101
102 {
103 PCI_VENDOR_TI,
104 PCI_PRODUCT_TI_PCIXX12SD,
105 0xffff,
106 0xffff,
107 3,
108 SDHC_PCI_QUIRK_TI_HACK
109 },
110
111 {
112 PCI_VENDOR_ENE,
113 PCI_PRODUCT_ENE_CB712,
114 0xffff,
115 0xffff,
116 0,
117 SDHC_PCI_QUIRK_NO_PWR0
118 },
119 {
120 PCI_VENDOR_RICOH,
121 PCI_PRODUCT_RICOH_Rx5U823,
122 0xffff,
123 0xffff,
124 0,
125 SDHC_PCI_QUIRK_RICOH_SLOW_SDR50_HACK
126 | SDHC_PCI_QUIRK_SINGLE_POWER_WRITE
127 | SDHC_PCI_QUIRK_BROKEN_ADMA
128 },
129 {
130 PCI_VENDOR_RICOH,
131 PCI_PRODUCT_RICOH_Rx5C822,
132 0xffff,
133 0xffff,
134 ~0,
135 SDHC_PCI_QUIRK_FORCE_DMA
136 | SDHC_PCI_QUIRK_BROKEN_ADMA
137 },
138
139 {
140 PCI_VENDOR_RICOH,
141 PCI_PRODUCT_RICOH_Rx5U822,
142 0xffff,
143 0xffff,
144 ~0,
145 SDHC_PCI_QUIRK_FORCE_DMA
146 | SDHC_PCI_QUIRK_BROKEN_ADMA
147 },
148
149 {
150 PCI_VENDOR_INTEL,
151 PCI_PRODUCT_INTEL_BAYTRAIL_SCC_MMC,
152 0xffff,
153 0xffff,
154 ~0,
155 SDHC_PCI_QUIRK_INTEL_EMMC_HW_RESET
156 },
157
158 {
159 PCI_VENDOR_INTEL,
160 PCI_PRODUCT_INTEL_BSW_SCC_MMC,
161 0xffff,
162 0xffff,
163 ~0,
164 SDHC_PCI_QUIRK_INTEL_EMMC_HW_RESET |
165 SDHC_PCI_QUIRK_NO_PWR0
166 },
167
168 {
169 PCI_VENDOR_INTEL,
170 PCI_PRODUCT_INTEL_100SERIES_LP_EMMC,
171 0xffff,
172 0xffff,
173 ~0,
174 SDHC_PCI_QUIRK_INTEL_EMMC_HW_RESET
175 },
176
177 {
178 PCI_VENDOR_INTEL,
179 PCI_PRODUCT_INTEL_C3K_EMMC,
180 0xffff,
181 0xffff,
182 ~0,
183 SDHC_PCI_QUIRK_INTEL_EMMC_HW_RESET |
184 SDHC_PCI_QUIRK_NO_PWR0
185 },
186 {
187 PCI_VENDOR_INTEL,
188 PCI_PRODUCT_INTEL_BAYTRAIL_SCC_MMC,
189 0xffff,
190 0xffff,
191 ~0,
192 SDHC_PCI_QUIRK_INTEL_EMMC_HW_RESET |
193 SDHC_PCI_QUIRK_NO_PWR0
194 },
195 {
196 PCI_VENDOR_INTEL,
197 PCI_PRODUCT_INTEL_BAYTRAIL_SCC_MMC2,
198 0xffff,
199 0xffff,
200 ~0,
201 SDHC_PCI_QUIRK_INTEL_EMMC_HW_RESET |
202 SDHC_PCI_QUIRK_NO_PWR0
203 },
204 {
205 PCI_VENDOR_INTEL,
206 PCI_PRODUCT_INTEL_APL_EMMC,
207 0xffff,
208 0xffff,
209 ~0,
210 SDHC_PCI_QUIRK_INTEL_EMMC_HW_RESET |
211 SDHC_PCI_QUIRK_NO_PWR0
212 },
213 {
214 PCI_VENDOR_INTEL,
215 PCI_PRODUCT_INTEL_GLK_EMMC,
216 0xffff,
217 0xffff,
218 ~0,
219 SDHC_PCI_QUIRK_INTEL_EMMC_HW_RESET |
220 SDHC_PCI_QUIRK_NO_PWR0
221 },
222 {
223 PCI_VENDOR_INTEL,
224 PCI_PRODUCT_INTEL_3HS_U_EMMC,
225 0xffff,
226 0xffff,
227 ~0,
228 SDHC_PCI_QUIRK_INTEL_EMMC_HW_RESET |
229 SDHC_PCI_QUIRK_NO_PWR0
230 },
231 {
232 PCI_VENDOR_INTEL,
233 PCI_PRODUCT_INTEL_495_YU_PCIE_EMMC,
234 0xffff,
235 0xffff,
236 ~0,
237 SDHC_PCI_QUIRK_INTEL_EMMC_HW_RESET |
238 SDHC_PCI_QUIRK_NO_PWR0
239 },
240 {
241 PCI_VENDOR_INTEL,
242 PCI_PRODUCT_INTEL_CMTLK_EMMC,
243 0xffff,
244 0xffff,
245 ~0,
246 SDHC_PCI_QUIRK_INTEL_EMMC_HW_RESET |
247 SDHC_PCI_QUIRK_NO_PWR0
248 },
249 {
250 PCI_VENDOR_INTEL,
251 PCI_PRODUCT_INTEL_JSL_EMMC,
252 0xffff,
253 0xffff,
254 ~0,
255 SDHC_PCI_QUIRK_INTEL_EMMC_HW_RESET |
256 SDHC_PCI_QUIRK_NO_PWR0
257 },
258 {
259 PCI_VENDOR_INTEL,
260 PCI_PRODUCT_INTEL_EHL_EMMC,
261 0xffff,
262 0xffff,
263 ~0,
264 SDHC_PCI_QUIRK_INTEL_EMMC_HW_RESET |
265 SDHC_PCI_QUIRK_NO_PWR0
266 },
267 };
268
269 static void sdhc_pci_quirk_ti_hack(struct pci_attach_args *);
270 static void sdhc_pci_quirk_ricoh_lower_freq_hack(struct pci_attach_args *);
271 static void sdhc_pci_intel_emmc_hw_reset(struct sdhc_softc *,
272 struct sdhc_host *);
273
274 static uint32_t
sdhc_pci_lookup_quirk_flags(struct pci_attach_args * pa)275 sdhc_pci_lookup_quirk_flags(struct pci_attach_args *pa)
276 {
277 const struct sdhc_pci_quirk *q;
278 pcireg_t id;
279 pci_vendor_id_t vendor;
280 pci_product_id_t product;
281 int i;
282
283 for (i = 0; i < __arraycount(sdhc_pci_quirk_table); i++) {
284 q = &sdhc_pci_quirk_table[i];
285
286 if ((PCI_VENDOR(pa->pa_id) == q->vendor)
287 && (PCI_PRODUCT(pa->pa_id) == q->product)) {
288 if ((q->function != ~0)
289 && (pa->pa_function != q->function))
290 continue;
291
292 if ((q->subvendor == 0xffff)
293 && (q->subproduct == 0xffff))
294 return (q->flags);
295
296 id = pci_conf_read(pa->pa_pc, pa->pa_tag,
297 PCI_SUBSYS_ID_REG);
298 vendor = PCI_VENDOR(id);
299 product = PCI_PRODUCT(id);
300
301 if ((q->subvendor != 0xffff)
302 && (q->subproduct != 0xffff)) {
303 if ((vendor == q->subvendor)
304 && (product == q->subproduct))
305 return (q->flags);
306 } else if (q->subvendor != 0xffff) {
307 if (product == q->subproduct)
308 return (q->flags);
309 } else {
310 if (vendor == q->subvendor)
311 return (q->flags);
312 }
313 }
314 }
315 return (0);
316 }
317
318 static int
sdhc_pci_match(device_t parent,cfdata_t cf,void * aux)319 sdhc_pci_match(device_t parent, cfdata_t cf, void *aux)
320 {
321 struct pci_attach_args *pa = aux;
322
323 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_SYSTEM &&
324 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SYSTEM_SDHC)
325 return (1);
326 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_RICOH &&
327 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_RICOH_Rx5U822 ||
328 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_RICOH_Rx5U823))
329 return (1);
330 return (0);
331 }
332
333 static void
sdhc_pci_attach(device_t parent,device_t self,void * aux)334 sdhc_pci_attach(device_t parent, device_t self, void *aux)
335 {
336 struct sdhc_pci_softc *sc = device_private(self);
337 struct pci_attach_args *pa = (struct pci_attach_args *)aux;
338 pci_chipset_tag_t pc = pa->pa_pc;
339 pcitag_t tag = pa->pa_tag;
340 pci_intr_handle_t ih;
341 pcireg_t csr;
342 pcireg_t slotinfo;
343 char const *intrstr;
344 int nslots;
345 int reg;
346 int cnt;
347 bus_space_tag_t iot;
348 bus_space_handle_t ioh;
349 bus_size_t size;
350 uint32_t flags;
351 int width;
352 char intrbuf[PCI_INTRSTR_LEN];
353
354 sc->sc.sc_dev = self;
355 sc->sc.sc_dmat = pa->pa_dmat;
356 sc->sc.sc_host = NULL;
357
358 sc->sc_pc = pc;
359
360 pci_aprint_devinfo(pa, NULL);
361
362 /* Some controllers needs special treatment. */
363 flags = sdhc_pci_lookup_quirk_flags(pa);
364 if (ISSET(flags, SDHC_PCI_QUIRK_TI_HACK))
365 sdhc_pci_quirk_ti_hack(pa);
366 if (ISSET(flags, SDHC_PCI_QUIRK_FORCE_DMA))
367 SET(sc->sc.sc_flags, SDHC_FLAG_FORCE_DMA);
368 if (ISSET(flags, SDHC_PCI_QUIRK_SINGLE_POWER_WRITE))
369 SET(sc->sc.sc_flags, SDHC_FLAG_SINGLE_POWER_WRITE);
370 if (ISSET(flags, SDHC_PCI_QUIRK_NO_PWR0))
371 SET(sc->sc.sc_flags, SDHC_FLAG_NO_PWR0);
372 if (ISSET(flags, SDHC_PCI_QUIRK_BROKEN_ADMA))
373 SET(sc->sc.sc_flags, SDHC_FLAG_BROKEN_ADMA);
374 if (ISSET(flags, SDHC_PCI_QUIRK_RICOH_LOWER_FREQ_HACK))
375 sdhc_pci_quirk_ricoh_lower_freq_hack(pa);
376 if (ISSET(flags, SDHC_PCI_QUIRK_RICOH_SLOW_SDR50_HACK))
377 SET(sc->sc.sc_flags, SDHC_FLAG_SLOW_SDR50);
378 if (ISSET(flags, SDHC_PCI_QUIRK_INTEL_EMMC_HW_RESET))
379 sc->sc.sc_vendor_hw_reset = sdhc_pci_intel_emmc_hw_reset;
380
381 /*
382 * Map and attach all hosts supported by the host controller.
383 */
384 slotinfo = pci_conf_read(pc, tag, SDHC_PCI_CONF_SLOT_INFO);
385 nslots = SDHC_PCI_NUM_SLOTS(slotinfo);
386
387 /* Allocate an array big enough to hold all the possible hosts */
388 sc->sc.sc_host = malloc(sizeof(struct sdhc_host *) * nslots,
389 M_DEVBUF, M_WAITOK | M_ZERO);
390
391 /* Enable the device. */
392 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
393 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG,
394 csr | PCI_COMMAND_MASTER_ENABLE);
395
396 /* Map and establish the interrupt. */
397 if (pci_intr_map(pa, &ih)) {
398 aprint_error_dev(self, "couldn't map interrupt\n");
399 goto err;
400 }
401
402 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf));
403 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_SDMMC, sdhc_intr,
404 &sc->sc, device_xname(self));
405 if (sc->sc_ih == NULL) {
406 aprint_error_dev(self, "couldn't establish interrupt\n");
407 goto err;
408 }
409 aprint_normal_dev(self, "interrupting at %s\n", intrstr);
410
411 /* Enable use of DMA if supported by the interface. */
412 if ((PCI_INTERFACE(pa->pa_class) == SDHC_PCI_INTERFACE_DMA))
413 SET(sc->sc.sc_flags, SDHC_FLAG_USE_DMA);
414
415 cnt = 0;
416 for (reg = SDHC_PCI_BAR_START + SDHC_PCI_FIRST_BAR(slotinfo) *
417 sizeof(uint32_t);
418 reg < SDHC_PCI_BAR_END && nslots > 0;
419 reg += width, nslots--) {
420 pcireg_t type;
421
422 type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, reg);
423 if (type == PCI_MAPREG_TYPE_IO)
424 break;
425 else if (PCI_MAPREG_MEM_TYPE(type)
426 == PCI_MAPREG_MEM_TYPE_64BIT)
427 width = 8;
428 else
429 width = 4;
430
431 if (pci_mapreg_map(pa, reg, type, 0,
432 &iot, &ioh, NULL, &size)) {
433 continue;
434 }
435
436 cnt++;
437 if (sdhc_host_found(&sc->sc, iot, ioh, size) != 0) {
438 /* XXX: sc->sc_host leak */
439 aprint_error_dev(self,
440 "couldn't initialize host (0x%x)\n", reg);
441 }
442 }
443 if (cnt == 0) {
444 aprint_error_dev(self, "couldn't map register\n");
445 goto err;
446 }
447
448 if (!pmf_device_register1(self, sdhc_suspend, sdhc_resume,
449 sdhc_shutdown)) {
450 aprint_error_dev(self, "couldn't establish powerhook\n");
451 }
452
453 return;
454
455 err:
456 if (sc->sc.sc_host != NULL) {
457 free(sc->sc.sc_host, M_DEVBUF);
458 sc->sc.sc_host = NULL;
459 }
460 }
461
462 static int
sdhc_pci_detach(device_t self,int flags)463 sdhc_pci_detach(device_t self, int flags)
464 {
465 struct sdhc_pci_softc * const sc = device_private(self);
466 int rv;
467
468 rv = sdhc_detach(&sc->sc, flags);
469 if (rv)
470 return rv;
471
472 if (sc->sc_ih != NULL) {
473 pci_intr_disestablish(sc->sc_pc, sc->sc_ih);
474 sc->sc_ih = NULL;
475 }
476
477 if (sc->sc.sc_host != NULL) {
478 free(sc->sc.sc_host, M_DEVBUF);
479 sc->sc.sc_host = NULL;
480 }
481
482 return rv;
483 }
484
485 static void
sdhc_pci_conf_write(struct pci_attach_args * pa,int reg,uint8_t val)486 sdhc_pci_conf_write(struct pci_attach_args *pa, int reg, uint8_t val)
487 {
488 pcireg_t r;
489
490 r = pci_conf_read(pa->pa_pc, pa->pa_tag, reg & ~0x3);
491 r &= ~(0xff << ((reg & 0x3) * 8));
492 r |= (val << ((reg & 0x3) * 8));
493 pci_conf_write(pa->pa_pc, pa->pa_tag, reg & ~0x3, r);
494 }
495
496 /* TI specific register */
497 #define SDHC_PCI_GENERAL_CTL 0x4c
498 #define MMC_SD_DIS 0x02
499
500 static void
sdhc_pci_quirk_ti_hack(struct pci_attach_args * pa)501 sdhc_pci_quirk_ti_hack(struct pci_attach_args *pa)
502 {
503 pci_chipset_tag_t pc = pa->pa_pc;
504 pcitag_t tag;
505 pcireg_t id, reg;
506
507 /* Look at func - 1 for the flash device */
508 tag = pci_make_tag(pc, pa->pa_bus, pa->pa_device, pa->pa_function - 1);
509 id = pci_conf_read(pc, tag, PCI_ID_REG);
510 if (PCI_VENDOR(id) != PCI_VENDOR_TI) {
511 return;
512 }
513 switch (PCI_PRODUCT(id)) {
514 case PCI_PRODUCT_TI_PCI72111FM:
515 case PCI_PRODUCT_TI_PCIXX12FM:
516 break;
517 default:
518 return;
519 }
520
521 /*
522 * Disable MMC/SD on the flash media controller so the
523 * SD host takes over.
524 */
525 reg = pci_conf_read(pc, tag, SDHC_PCI_GENERAL_CTL);
526 reg |= MMC_SD_DIS;
527 pci_conf_write(pc, tag, SDHC_PCI_GENERAL_CTL, reg);
528 }
529
530 /* Ricoh specific register */
531 #define SDHC_PCI_MODE_KEY 0xf9
532 #define SDHC_PCI_MODE 0x150
533 #define SDHC_PCI_MODE_SD20 0x10
534 #define SDHC_PCI_BASE_FREQ_KEY 0xfc
535 #define SDHC_PCI_BASE_FREQ 0xe1
536
537 /* Some RICOH controllers need to be bumped into the right mode. */
538 static void
sdhc_pci_quirk_ricoh_lower_freq_hack(struct pci_attach_args * pa)539 sdhc_pci_quirk_ricoh_lower_freq_hack(struct pci_attach_args *pa)
540 {
541 /* Enable SD2.0 mode. */
542 sdhc_pci_conf_write(pa, SDHC_PCI_MODE_KEY, 0xfc);
543 sdhc_pci_conf_write(pa, SDHC_PCI_MODE, SDHC_PCI_MODE_SD20);
544 sdhc_pci_conf_write(pa, SDHC_PCI_MODE_KEY, 0x00);
545
546 /*
547 * Some SD/MMC cards don't work with the default base
548 * clock frequency of 200MHz. Lower it to 50MHz.
549 */
550 sdhc_pci_conf_write(pa, SDHC_PCI_BASE_FREQ_KEY, 0x01);
551 sdhc_pci_conf_write(pa, SDHC_PCI_BASE_FREQ, 50);
552 sdhc_pci_conf_write(pa, SDHC_PCI_BASE_FREQ_KEY, 0x00);
553 }
554
555 static void
sdhc_pci_intel_emmc_hw_reset(struct sdhc_softc * sc,struct sdhc_host * hp)556 sdhc_pci_intel_emmc_hw_reset(struct sdhc_softc *sc, struct sdhc_host *hp)
557 {
558 kmutex_t *plock = sdhc_host_lock(hp);
559 uint8_t reg;
560
561 mutex_enter(plock);
562
563 reg = sdhc_host_read_1(hp, SDHC_POWER_CTL);
564 reg |= 0x10;
565 sdhc_host_write_1(hp, SDHC_POWER_CTL, reg);
566
567 sdmmc_delay(10);
568
569 reg &= ~0x10;
570 sdhc_host_write_1(hp, SDHC_POWER_CTL, reg);
571
572 sdmmc_delay(1000);
573
574 mutex_exit(plock);
575 }
576