1 /* $NetBSD: if_vge.c,v 1.89 2024/07/05 04:31:51 rin Exp $ */
2
3 /*-
4 * Copyright (c) 2004
5 * Bill Paul <wpaul@windriver.com>. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 * FreeBSD: src/sys/dev/vge/if_vge.c,v 1.5 2005/02/07 19:39:29 glebius Exp
35 */
36
37 #include <sys/cdefs.h>
38 __KERNEL_RCSID(0, "$NetBSD: if_vge.c,v 1.89 2024/07/05 04:31:51 rin Exp $");
39
40 /*
41 * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver.
42 *
43 * Written by Bill Paul <wpaul@windriver.com>
44 * Senior Networking Software Engineer
45 * Wind River Systems
46 */
47
48 /*
49 * The VIA Networking VT6122 is a 32bit, 33/66 MHz PCI device that
50 * combines a tri-speed ethernet MAC and PHY, with the following
51 * features:
52 *
53 * o Jumbo frame support up to 16K
54 * o Transmit and receive flow control
55 * o IPv4 checksum offload
56 * o VLAN tag insertion and stripping
57 * o TCP large send
58 * o 64-bit multicast hash table filter
59 * o 64 entry CAM filter
60 * o 16K RX FIFO and 48K TX FIFO memory
61 * o Interrupt moderation
62 *
63 * The VT6122 supports up to four transmit DMA queues. The descriptors
64 * in the transmit ring can address up to 7 data fragments; frames which
65 * span more than 7 data buffers must be coalesced, but in general the
66 * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments
67 * long. The receive descriptors address only a single buffer.
68 *
69 * There are two peculiar design issues with the VT6122. One is that
70 * receive data buffers must be aligned on a 32-bit boundary. This is
71 * not a problem where the VT6122 is used as a LOM device in x86-based
72 * systems, but on architectures that generate unaligned access traps, we
73 * have to do some copying.
74 *
75 * The other issue has to do with the way 64-bit addresses are handled.
76 * The DMA descriptors only allow you to specify 48 bits of addressing
77 * information. The remaining 16 bits are specified using one of the
78 * I/O registers (VGE_DATABUF_HIADDR). If you only have a 32-bit system,
79 * then this isn't an issue, but if you have a 64-bit system and more than
80 * 4GB of memory, you must have to make sure your network data buffers reside
81 * in the same 48-bit 'segment.'
82 *
83 * Furthermore, the descriptors must also all reside within the same 32-bit
84 * 'segment' (see VGE_TXDESC_HIADDR).
85 *
86 * Special thanks to Ryan Fu at VIA Networking for providing documentation
87 * and sample NICs for testing.
88 */
89
90
91 #include <sys/param.h>
92 #include <sys/endian.h>
93 #include <sys/systm.h>
94 #include <sys/device.h>
95 #include <sys/sockio.h>
96 #include <sys/mbuf.h>
97 #include <sys/kernel.h>
98 #include <sys/socket.h>
99
100 #include <net/if.h>
101 #include <net/if_arp.h>
102 #include <net/if_ether.h>
103 #include <net/if_dl.h>
104 #include <net/if_media.h>
105
106 #include <net/bpf.h>
107
108 #include <sys/bus.h>
109
110 #include <dev/mii/mii.h>
111 #include <dev/mii/miivar.h>
112
113 #include <dev/pci/pcireg.h>
114 #include <dev/pci/pcivar.h>
115 #include <dev/pci/pcidevs.h>
116
117 #include <dev/pci/if_vgereg.h>
118
119 #define VGE_IFQ_MAXLEN 64
120
121 #define VGE_RING_ALIGN 256
122
123 #define VGE_NTXDESC 256
124 #define VGE_NTXDESC_MASK (VGE_NTXDESC - 1)
125 #define VGE_NEXT_TXDESC(x) ((x + 1) & VGE_NTXDESC_MASK)
126 #define VGE_PREV_TXDESC(x) ((x - 1) & VGE_NTXDESC_MASK)
127
128 #define VGE_NRXDESC 256 /* Must be a multiple of 4!! */
129 #define VGE_NRXDESC_MASK (VGE_NRXDESC - 1)
130 #define VGE_NEXT_RXDESC(x) ((x + 1) & VGE_NRXDESC_MASK)
131 #define VGE_PREV_RXDESC(x) ((x - 1) & VGE_NRXDESC_MASK)
132
133 #define VGE_ADDR_LO(y) BUS_ADDR_LO32(y)
134 #define VGE_ADDR_HI(y) BUS_ADDR_HI32(y)
135 #define VGE_BUFLEN(y) ((y) & 0x7FFF)
136 #define ETHER_PAD_LEN (ETHER_MIN_LEN - ETHER_CRC_LEN)
137
138 #define VGE_POWER_MANAGEMENT 0 /* disabled for now */
139
140 /*
141 * Mbuf adjust factor to force 32-bit alignment of IP header.
142 * Drivers should pad ETHER_ALIGN bytes when setting up a
143 * RX mbuf so the upper layers get the IP header properly aligned
144 * past the 14-byte Ethernet header.
145 *
146 * See also comment in vge_encap().
147 */
148
149 #ifdef __NO_STRICT_ALIGNMENT
150 #define VGE_RX_BUFSIZE MCLBYTES
151 #else
152 #define VGE_RX_PAD sizeof(uint32_t)
153 #define VGE_RX_BUFSIZE (MCLBYTES - VGE_RX_PAD)
154 #endif
155
156 /*
157 * Control structures are DMA'd to the vge chip. We allocate them in
158 * a single clump that maps to a single DMA segment to make several things
159 * easier.
160 */
161 struct vge_control_data {
162 /* TX descriptors */
163 struct vge_txdesc vcd_txdescs[VGE_NTXDESC];
164 /* RX descriptors */
165 struct vge_rxdesc vcd_rxdescs[VGE_NRXDESC];
166 /* dummy data for TX padding */
167 uint8_t vcd_pad[ETHER_PAD_LEN];
168 };
169
170 #define VGE_CDOFF(x) offsetof(struct vge_control_data, x)
171 #define VGE_CDTXOFF(x) VGE_CDOFF(vcd_txdescs[(x)])
172 #define VGE_CDRXOFF(x) VGE_CDOFF(vcd_rxdescs[(x)])
173 #define VGE_CDPADOFF() VGE_CDOFF(vcd_pad[0])
174
175 /*
176 * Software state for TX jobs.
177 */
178 struct vge_txsoft {
179 struct mbuf *txs_mbuf; /* head of our mbuf chain */
180 bus_dmamap_t txs_dmamap; /* our DMA map */
181 };
182
183 /*
184 * Software state for RX jobs.
185 */
186 struct vge_rxsoft {
187 struct mbuf *rxs_mbuf; /* head of our mbuf chain */
188 bus_dmamap_t rxs_dmamap; /* our DMA map */
189 };
190
191
192 struct vge_softc {
193 device_t sc_dev;
194
195 bus_space_tag_t sc_bst; /* bus space tag */
196 bus_space_handle_t sc_bsh; /* bus space handle */
197 bus_dma_tag_t sc_dmat;
198
199 struct ethercom sc_ethercom; /* interface info */
200 uint8_t sc_eaddr[ETHER_ADDR_LEN];
201
202 void *sc_intrhand;
203 struct mii_data sc_mii;
204 uint8_t sc_type;
205 u_short sc_if_flags;
206 int sc_link;
207 int sc_camidx;
208 callout_t sc_timeout;
209
210 bus_dmamap_t sc_cddmamap;
211 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr
212
213 struct vge_txsoft sc_txsoft[VGE_NTXDESC];
214 struct vge_rxsoft sc_rxsoft[VGE_NRXDESC];
215 struct vge_control_data *sc_control_data;
216 #define sc_txdescs sc_control_data->vcd_txdescs
217 #define sc_rxdescs sc_control_data->vcd_rxdescs
218
219 int sc_tx_prodidx;
220 int sc_tx_considx;
221 int sc_tx_free;
222
223 struct mbuf *sc_rx_mhead;
224 struct mbuf *sc_rx_mtail;
225 int sc_rx_prodidx;
226 int sc_rx_consumed;
227
228 int sc_suspended; /* 0 = normal 1 = suspended */
229 uint32_t sc_saved_maps[5]; /* pci data */
230 uint32_t sc_saved_biosaddr;
231 uint8_t sc_saved_intline;
232 uint8_t sc_saved_cachelnsz;
233 uint8_t sc_saved_lattimer;
234 };
235
236 #define VGE_CDTXADDR(sc, x) ((sc)->sc_cddma + VGE_CDTXOFF(x))
237 #define VGE_CDRXADDR(sc, x) ((sc)->sc_cddma + VGE_CDRXOFF(x))
238 #define VGE_CDPADADDR(sc) ((sc)->sc_cddma + VGE_CDPADOFF())
239
240 #define VGE_TXDESCSYNC(sc, idx, ops) \
241 bus_dmamap_sync((sc)->sc_dmat,(sc)->sc_cddmamap, \
242 VGE_CDTXOFF(idx), \
243 offsetof(struct vge_txdesc, td_frag[0]), \
244 (ops))
245 #define VGE_TXFRAGSYNC(sc, idx, nsegs, ops) \
246 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \
247 VGE_CDTXOFF(idx) + \
248 offsetof(struct vge_txdesc, td_frag[0]), \
249 sizeof(struct vge_txfrag) * (nsegs), \
250 (ops))
251 #define VGE_RXDESCSYNC(sc, idx, ops) \
252 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \
253 VGE_CDRXOFF(idx), \
254 sizeof(struct vge_rxdesc), \
255 (ops))
256
257 /*
258 * register space access macros
259 */
260 #define CSR_WRITE_4(sc, reg, val) \
261 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
262 #define CSR_WRITE_2(sc, reg, val) \
263 bus_space_write_2((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
264 #define CSR_WRITE_1(sc, reg, val) \
265 bus_space_write_1((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
266
267 #define CSR_READ_4(sc, reg) \
268 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
269 #define CSR_READ_2(sc, reg) \
270 bus_space_read_2((sc)->sc_bst, (sc)->sc_bsh, (reg))
271 #define CSR_READ_1(sc, reg) \
272 bus_space_read_1((sc)->sc_bst, (sc)->sc_bsh, (reg))
273
274 #define CSR_SETBIT_1(sc, reg, x) \
275 CSR_WRITE_1((sc), (reg), CSR_READ_1((sc), (reg)) | (x))
276 #define CSR_SETBIT_2(sc, reg, x) \
277 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (x))
278 #define CSR_SETBIT_4(sc, reg, x) \
279 CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) | (x))
280
281 #define CSR_CLRBIT_1(sc, reg, x) \
282 CSR_WRITE_1((sc), (reg), CSR_READ_1((sc), (reg)) & ~(x))
283 #define CSR_CLRBIT_2(sc, reg, x) \
284 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & ~(x))
285 #define CSR_CLRBIT_4(sc, reg, x) \
286 CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) & ~(x))
287
288 #define VGE_TIMEOUT 10000
289
290 #define VGE_PCI_LOIO 0x10
291 #define VGE_PCI_LOMEM 0x14
292
293 static inline void vge_set_txaddr(struct vge_txfrag *, bus_addr_t);
294 static inline void vge_set_rxaddr(struct vge_rxdesc *, bus_addr_t);
295
296 static int vge_ifflags_cb(struct ethercom *);
297
298 static int vge_match(device_t, cfdata_t, void *);
299 static void vge_attach(device_t, device_t, void *);
300
301 static int vge_encap(struct vge_softc *, struct mbuf *, int);
302
303 static int vge_allocmem(struct vge_softc *);
304 static int vge_newbuf(struct vge_softc *, int, struct mbuf *);
305 #ifndef __NO_STRICT_ALIGNMENT
306 static inline void vge_fixup_rx(struct mbuf *);
307 #endif
308 static void vge_rxeof(struct vge_softc *);
309 static void vge_txeof(struct vge_softc *);
310 static int vge_intr(void *);
311 static void vge_tick(void *);
312 static void vge_start(struct ifnet *);
313 static int vge_ioctl(struct ifnet *, u_long, void *);
314 static int vge_init(struct ifnet *);
315 static void vge_stop(struct ifnet *, int);
316 static void vge_watchdog(struct ifnet *);
317 #if VGE_POWER_MANAGEMENT
318 static int vge_suspend(device_t);
319 static int vge_resume(device_t);
320 #endif
321 static bool vge_shutdown(device_t, int);
322
323 static uint16_t vge_read_eeprom(struct vge_softc *, int);
324
325 static void vge_miipoll_start(struct vge_softc *);
326 static void vge_miipoll_stop(struct vge_softc *);
327 static int vge_miibus_readreg(device_t, int, int, uint16_t *);
328 static int vge_miibus_writereg(device_t, int, int, uint16_t);
329 static void vge_miibus_statchg(struct ifnet *);
330
331 static void vge_cam_clear(struct vge_softc *);
332 static int vge_cam_set(struct vge_softc *, uint8_t *);
333 static void vge_clrwol(struct vge_softc *);
334 static void vge_setmulti(struct vge_softc *);
335 static void vge_reset(struct vge_softc *);
336
337 CFATTACH_DECL_NEW(vge, sizeof(struct vge_softc),
338 vge_match, vge_attach, NULL, NULL);
339
340 static inline void
vge_set_txaddr(struct vge_txfrag * f,bus_addr_t daddr)341 vge_set_txaddr(struct vge_txfrag *f, bus_addr_t daddr)
342 {
343
344 f->tf_addrlo = htole32((uint32_t)daddr);
345 if (sizeof(bus_addr_t) == sizeof(uint64_t))
346 f->tf_addrhi = htole16(((uint64_t)daddr >> 32) & 0xFFFF);
347 else
348 f->tf_addrhi = 0;
349 }
350
351 static inline void
vge_set_rxaddr(struct vge_rxdesc * rxd,bus_addr_t daddr)352 vge_set_rxaddr(struct vge_rxdesc *rxd, bus_addr_t daddr)
353 {
354
355 rxd->rd_addrlo = htole32((uint32_t)daddr);
356 if (sizeof(bus_addr_t) == sizeof(uint64_t))
357 rxd->rd_addrhi = htole16(((uint64_t)daddr >> 32) & 0xFFFF);
358 else
359 rxd->rd_addrhi = 0;
360 }
361
362 /*
363 * Read a word of data stored in the EEPROM at address 'addr.'
364 */
365 static uint16_t
vge_read_eeprom(struct vge_softc * sc,int addr)366 vge_read_eeprom(struct vge_softc *sc, int addr)
367 {
368 int i;
369 uint16_t word = 0;
370
371 /*
372 * Enter EEPROM embedded programming mode. In order to
373 * access the EEPROM at all, we first have to set the
374 * EELOAD bit in the CHIPCFG2 register.
375 */
376 CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD);
377 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*| VGE_EECSR_ECS*/);
378
379 /* Select the address of the word we want to read */
380 CSR_WRITE_1(sc, VGE_EEADDR, addr);
381
382 /* Issue read command */
383 CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD);
384
385 /* Wait for the done bit to be set. */
386 for (i = 0; i < VGE_TIMEOUT; i++) {
387 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE)
388 break;
389 }
390
391 if (i == VGE_TIMEOUT) {
392 printf("%s: EEPROM read timed out\n", device_xname(sc->sc_dev));
393 return 0;
394 }
395
396 /* Read the result */
397 word = CSR_READ_2(sc, VGE_EERDDAT);
398
399 /* Turn off EEPROM access mode. */
400 CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*| VGE_EECSR_ECS*/);
401 CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD);
402
403 return word;
404 }
405
406 static void
vge_miipoll_stop(struct vge_softc * sc)407 vge_miipoll_stop(struct vge_softc *sc)
408 {
409 int i;
410
411 CSR_WRITE_1(sc, VGE_MIICMD, 0);
412
413 for (i = 0; i < VGE_TIMEOUT; i++) {
414 DELAY(1);
415 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL)
416 break;
417 }
418
419 if (i == VGE_TIMEOUT) {
420 printf("%s: failed to idle MII autopoll\n",
421 device_xname(sc->sc_dev));
422 }
423 }
424
425 static void
vge_miipoll_start(struct vge_softc * sc)426 vge_miipoll_start(struct vge_softc *sc)
427 {
428 int i;
429
430 /* First, make sure we're idle. */
431
432 CSR_WRITE_1(sc, VGE_MIICMD, 0);
433 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL);
434
435 for (i = 0; i < VGE_TIMEOUT; i++) {
436 DELAY(1);
437 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL)
438 break;
439 }
440
441 if (i == VGE_TIMEOUT) {
442 printf("%s: failed to idle MII autopoll\n",
443 device_xname(sc->sc_dev));
444 return;
445 }
446
447 /* Now enable auto poll mode. */
448
449 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO);
450
451 /* And make sure it started. */
452
453 for (i = 0; i < VGE_TIMEOUT; i++) {
454 DELAY(1);
455 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0)
456 break;
457 }
458
459 if (i == VGE_TIMEOUT) {
460 printf("%s: failed to start MII autopoll\n",
461 device_xname(sc->sc_dev));
462 }
463 }
464
465 static int
vge_miibus_readreg(device_t dev,int phy,int reg,uint16_t * val)466 vge_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val)
467 {
468 struct vge_softc *sc;
469 int i, s;
470 int rv = 0;
471
472 sc = device_private(dev);
473 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F))
474 return -1;
475
476 s = splnet();
477 vge_miipoll_stop(sc);
478
479 /* Specify the register we want to read. */
480 CSR_WRITE_1(sc, VGE_MIIADDR, reg);
481
482 /* Issue read command. */
483 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD);
484
485 /* Wait for the read command bit to self-clear. */
486 for (i = 0; i < VGE_TIMEOUT; i++) {
487 DELAY(1);
488 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0)
489 break;
490 }
491
492 if (i == VGE_TIMEOUT) {
493 printf("%s: MII read timed out\n", device_xname(sc->sc_dev));
494 rv = ETIMEDOUT;
495 } else
496 *val = CSR_READ_2(sc, VGE_MIIDATA);
497
498 vge_miipoll_start(sc);
499 splx(s);
500
501 return rv;
502 }
503
504 static int
vge_miibus_writereg(device_t dev,int phy,int reg,uint16_t val)505 vge_miibus_writereg(device_t dev, int phy, int reg, uint16_t val)
506 {
507 struct vge_softc *sc;
508 int i, s, rv = 0;
509
510 sc = device_private(dev);
511 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F))
512 return -1;
513
514 s = splnet();
515 vge_miipoll_stop(sc);
516
517 /* Specify the register we want to write. */
518 CSR_WRITE_1(sc, VGE_MIIADDR, reg);
519
520 /* Specify the data we want to write. */
521 CSR_WRITE_2(sc, VGE_MIIDATA, val);
522
523 /* Issue write command. */
524 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD);
525
526 /* Wait for the write command bit to self-clear. */
527 for (i = 0; i < VGE_TIMEOUT; i++) {
528 DELAY(1);
529 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0)
530 break;
531 }
532
533 if (i == VGE_TIMEOUT) {
534 printf("%s: MII write timed out\n", device_xname(sc->sc_dev));
535 rv = ETIMEDOUT;
536 }
537
538 vge_miipoll_start(sc);
539 splx(s);
540
541 return rv;
542 }
543
544 static void
vge_cam_clear(struct vge_softc * sc)545 vge_cam_clear(struct vge_softc *sc)
546 {
547 int i;
548
549 /*
550 * Turn off all the mask bits. This tells the chip
551 * that none of the entries in the CAM filter are valid.
552 * desired entries will be enabled as we fill the filter in.
553 */
554
555 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
556 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK);
557 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE);
558 for (i = 0; i < 8; i++)
559 CSR_WRITE_1(sc, VGE_CAM0 + i, 0);
560
561 /* Clear the VLAN filter too. */
562
563 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE | VGE_CAMADDR_AVSEL);
564 for (i = 0; i < 8; i++)
565 CSR_WRITE_1(sc, VGE_CAM0 + i, 0);
566
567 CSR_WRITE_1(sc, VGE_CAMADDR, 0);
568 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
569 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR);
570
571 sc->sc_camidx = 0;
572 }
573
574 static int
vge_cam_set(struct vge_softc * sc,uint8_t * addr)575 vge_cam_set(struct vge_softc *sc, uint8_t *addr)
576 {
577 int i, error;
578
579 error = 0;
580
581 if (sc->sc_camidx == VGE_CAM_MAXADDRS)
582 return ENOSPC;
583
584 /* Select the CAM data page. */
585 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
586 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA);
587
588 /* Set the filter entry we want to update and enable writing. */
589 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE | sc->sc_camidx);
590
591 /* Write the address to the CAM registers */
592 for (i = 0; i < ETHER_ADDR_LEN; i++)
593 CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]);
594
595 /* Issue a write command. */
596 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE);
597
598 /* Wake for it to clear. */
599 for (i = 0; i < VGE_TIMEOUT; i++) {
600 DELAY(1);
601 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0)
602 break;
603 }
604
605 if (i == VGE_TIMEOUT) {
606 printf("%s: setting CAM filter failed\n",
607 device_xname(sc->sc_dev));
608 error = EIO;
609 goto fail;
610 }
611
612 /* Select the CAM mask page. */
613 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
614 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK);
615
616 /* Set the mask bit that enables this filter. */
617 CSR_SETBIT_1(sc, VGE_CAM0 + (sc->sc_camidx / 8),
618 1 << (sc->sc_camidx & 7));
619
620 sc->sc_camidx++;
621
622 fail:
623 /* Turn off access to CAM. */
624 CSR_WRITE_1(sc, VGE_CAMADDR, 0);
625 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
626 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR);
627
628 return error;
629 }
630
631 /*
632 * Program the multicast filter. We use the 64-entry CAM filter
633 * for perfect filtering. If there's more than 64 multicast addresses,
634 * we use the hash filter instead.
635 */
636 static void
vge_setmulti(struct vge_softc * sc)637 vge_setmulti(struct vge_softc *sc)
638 {
639 struct ethercom *ec = &sc->sc_ethercom;
640 struct ifnet *ifp = &ec->ec_if;
641 int error;
642 uint32_t h, hashes[2] = { 0, 0 };
643 struct ether_multi *enm;
644 struct ether_multistep step;
645
646 error = 0;
647
648 /* First, zot all the multicast entries. */
649 vge_cam_clear(sc);
650 CSR_WRITE_4(sc, VGE_MAR0, 0);
651 CSR_WRITE_4(sc, VGE_MAR1, 0);
652 ifp->if_flags &= ~IFF_ALLMULTI;
653
654 /*
655 * If the user wants allmulti or promisc mode, enable reception
656 * of all multicast frames.
657 */
658 if (ifp->if_flags & IFF_PROMISC) {
659 allmulti:
660 CSR_WRITE_4(sc, VGE_MAR0, 0xFFFFFFFF);
661 CSR_WRITE_4(sc, VGE_MAR1, 0xFFFFFFFF);
662 ifp->if_flags |= IFF_ALLMULTI;
663 return;
664 }
665
666 /* Now program new ones */
667 ETHER_LOCK(ec);
668 ETHER_FIRST_MULTI(step, ec, enm);
669 while (enm != NULL) {
670 /*
671 * If multicast range, fall back to ALLMULTI.
672 */
673 if (memcmp(enm->enm_addrlo, enm->enm_addrhi,
674 ETHER_ADDR_LEN) != 0) {
675 ETHER_UNLOCK(ec);
676 goto allmulti;
677 }
678
679 error = vge_cam_set(sc, enm->enm_addrlo);
680 if (error)
681 break;
682
683 ETHER_NEXT_MULTI(step, enm);
684 }
685 ETHER_UNLOCK(ec);
686
687 /* If there were too many addresses, use the hash filter. */
688 if (error) {
689 vge_cam_clear(sc);
690
691 ETHER_LOCK(ec);
692 ETHER_FIRST_MULTI(step, ec, enm);
693 while (enm != NULL) {
694 /*
695 * If multicast range, fall back to ALLMULTI.
696 */
697 if (memcmp(enm->enm_addrlo, enm->enm_addrhi,
698 ETHER_ADDR_LEN) != 0) {
699 ETHER_UNLOCK(ec);
700 goto allmulti;
701 }
702
703 h = ether_crc32_be(enm->enm_addrlo,
704 ETHER_ADDR_LEN) >> 26;
705 hashes[h >> 5] |= 1 << (h & 0x1f);
706
707 ETHER_NEXT_MULTI(step, enm);
708 }
709 ETHER_UNLOCK(ec);
710
711 CSR_WRITE_4(sc, VGE_MAR0, hashes[0]);
712 CSR_WRITE_4(sc, VGE_MAR1, hashes[1]);
713 }
714 }
715
716 static void
vge_reset(struct vge_softc * sc)717 vge_reset(struct vge_softc *sc)
718 {
719 int i;
720
721 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET);
722
723 for (i = 0; i < VGE_TIMEOUT; i++) {
724 DELAY(5);
725 if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0)
726 break;
727 }
728
729 if (i == VGE_TIMEOUT) {
730 printf("%s: soft reset timed out", device_xname(sc->sc_dev));
731 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE);
732 DELAY(2000);
733 }
734
735 DELAY(5000);
736
737 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_RELOAD);
738
739 for (i = 0; i < VGE_TIMEOUT; i++) {
740 DELAY(5);
741 if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0)
742 break;
743 }
744
745 if (i == VGE_TIMEOUT) {
746 printf("%s: EEPROM reload timed out\n",
747 device_xname(sc->sc_dev));
748 return;
749 }
750
751 /*
752 * On some machine, the first read data from EEPROM could be
753 * messed up, so read one dummy data here to avoid the mess.
754 */
755 (void)vge_read_eeprom(sc, 0);
756
757 CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI);
758 }
759
760 /*
761 * Probe for a VIA gigabit chip. Check the PCI vendor and device
762 * IDs against our list and return a device name if we find a match.
763 */
764 static int
vge_match(device_t parent,cfdata_t match,void * aux)765 vge_match(device_t parent, cfdata_t match, void *aux)
766 {
767 struct pci_attach_args *pa = aux;
768
769 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH
770 && PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_VIATECH_VT612X)
771 return 1;
772
773 return 0;
774 }
775
776 static int
vge_allocmem(struct vge_softc * sc)777 vge_allocmem(struct vge_softc *sc)
778 {
779 int error;
780 int nseg;
781 int i;
782 bus_dma_segment_t seg;
783
784 /*
785 * Allocate memory for control data.
786 *
787 * NOTE: This must all fit within the same 4GB segment. The
788 * "boundary" argument to bus_dmamem_alloc() will end up as
789 * 4GB on 64-bit platforms and 0 ("no boundary constraint") on
790 * 32-bit platformds.
791 */
792
793 error = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct vge_control_data),
794 VGE_RING_ALIGN,
795 (bus_size_t)(1ULL << 32),
796 &seg, 1, &nseg, BUS_DMA_NOWAIT);
797 if (error) {
798 aprint_error_dev(sc->sc_dev,
799 "could not allocate control data dma memory\n");
800 goto fail_1;
801 }
802
803 /* Map the memory to kernel VA space */
804
805 error = bus_dmamem_map(sc->sc_dmat, &seg, nseg,
806 sizeof(struct vge_control_data), (void **)&sc->sc_control_data,
807 BUS_DMA_NOWAIT);
808 if (error) {
809 aprint_error_dev(sc->sc_dev,
810 "could not map control data dma memory\n");
811 goto fail_2;
812 }
813 memset(sc->sc_control_data, 0, sizeof(struct vge_control_data));
814
815 /*
816 * Create map for control data.
817 */
818 error = bus_dmamap_create(sc->sc_dmat,
819 sizeof(struct vge_control_data), 1,
820 sizeof(struct vge_control_data), 0, BUS_DMA_NOWAIT,
821 &sc->sc_cddmamap);
822 if (error) {
823 aprint_error_dev(sc->sc_dev,
824 "could not create control data dmamap\n");
825 goto fail_3;
826 }
827
828 /* Load the map for the control data. */
829 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap,
830 sc->sc_control_data, sizeof(struct vge_control_data), NULL,
831 BUS_DMA_NOWAIT);
832 if (error) {
833 aprint_error_dev(sc->sc_dev,
834 "could not load control data dma memory\n");
835 goto fail_4;
836 }
837
838 /* Create DMA maps for TX buffers */
839
840 for (i = 0; i < VGE_NTXDESC; i++) {
841 error = bus_dmamap_create(sc->sc_dmat, VGE_TX_MAXLEN,
842 VGE_TX_FRAGS, VGE_TX_MAXLEN, 0, BUS_DMA_NOWAIT,
843 &sc->sc_txsoft[i].txs_dmamap);
844 if (error) {
845 aprint_error_dev(sc->sc_dev,
846 "can't create DMA map for TX descs\n");
847 goto fail_5;
848 }
849 }
850
851 /* Create DMA maps for RX buffers */
852
853 for (i = 0; i < VGE_NRXDESC; i++) {
854 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES,
855 1, MCLBYTES, 0, BUS_DMA_NOWAIT,
856 &sc->sc_rxsoft[i].rxs_dmamap);
857 if (error) {
858 aprint_error_dev(sc->sc_dev,
859 "can't create DMA map for RX descs\n");
860 goto fail_6;
861 }
862 sc->sc_rxsoft[i].rxs_mbuf = NULL;
863 }
864
865 return 0;
866
867 fail_6:
868 for (i = 0; i < VGE_NRXDESC; i++) {
869 if (sc->sc_rxsoft[i].rxs_dmamap != NULL)
870 bus_dmamap_destroy(sc->sc_dmat,
871 sc->sc_rxsoft[i].rxs_dmamap);
872 }
873 fail_5:
874 for (i = 0; i < VGE_NTXDESC; i++) {
875 if (sc->sc_txsoft[i].txs_dmamap != NULL)
876 bus_dmamap_destroy(sc->sc_dmat,
877 sc->sc_txsoft[i].txs_dmamap);
878 }
879 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap);
880 fail_4:
881 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap);
882 fail_3:
883 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data,
884 sizeof(struct vge_control_data));
885 fail_2:
886 bus_dmamem_free(sc->sc_dmat, &seg, nseg);
887 fail_1:
888 return ENOMEM;
889 }
890
891 /*
892 * Attach the interface. Allocate softc structures, do ifmedia
893 * setup and ethernet/BPF attach.
894 */
895 static void
vge_attach(device_t parent,device_t self,void * aux)896 vge_attach(device_t parent, device_t self, void *aux)
897 {
898 uint8_t *eaddr;
899 struct vge_softc *sc = device_private(self);
900 struct ifnet *ifp;
901 struct mii_data * const mii = &sc->sc_mii;
902 struct pci_attach_args *pa = aux;
903 pci_chipset_tag_t pc = pa->pa_pc;
904 const char *intrstr;
905 pci_intr_handle_t ih;
906 uint16_t val;
907 char intrbuf[PCI_INTRSTR_LEN];
908
909 sc->sc_dev = self;
910
911 pci_aprint_devinfo_fancy(pa, NULL, "VIA VT612X Gigabit Ethernet", 1);
912
913 /* Make sure bus-mastering is enabled */
914 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
915 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) |
916 PCI_COMMAND_MASTER_ENABLE);
917
918 /*
919 * Map control/status registers.
920 */
921 if (pci_mapreg_map(pa, VGE_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0,
922 &sc->sc_bst, &sc->sc_bsh, NULL, NULL) != 0) {
923 aprint_error_dev(self, "couldn't map memory\n");
924 return;
925 }
926
927 /*
928 * Map and establish our interrupt.
929 */
930 if (pci_intr_map(pa, &ih)) {
931 aprint_error_dev(self, "unable to map interrupt\n");
932 return;
933 }
934 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf));
935 sc->sc_intrhand = pci_intr_establish_xname(pc, ih, IPL_NET, vge_intr,
936 sc, device_xname(self));
937 if (sc->sc_intrhand == NULL) {
938 aprint_error_dev(self, "unable to establish interrupt");
939 if (intrstr != NULL)
940 aprint_error(" at %s", intrstr);
941 aprint_error("\n");
942 return;
943 }
944 aprint_normal_dev(self, "interrupting at %s\n", intrstr);
945
946 /* Reset the adapter. */
947 vge_reset(sc);
948
949 /*
950 * Get station address from the EEPROM.
951 */
952 eaddr = sc->sc_eaddr;
953 val = vge_read_eeprom(sc, VGE_EE_EADDR + 0);
954 eaddr[0] = val & 0xff;
955 eaddr[1] = val >> 8;
956 val = vge_read_eeprom(sc, VGE_EE_EADDR + 1);
957 eaddr[2] = val & 0xff;
958 eaddr[3] = val >> 8;
959 val = vge_read_eeprom(sc, VGE_EE_EADDR + 2);
960 eaddr[4] = val & 0xff;
961 eaddr[5] = val >> 8;
962
963 aprint_normal_dev(self, "Ethernet address %s\n",
964 ether_sprintf(eaddr));
965
966 /* Clear WOL and take hardware from powerdown. */
967 vge_clrwol(sc);
968
969 /*
970 * The hardware supports 64-bit DMA addresses, but it's a little
971 * complicated (see large comment about the hardware near the top
972 * of the file). TL;DR -- restrict ourselves to 48-bit.
973 */
974 if (pci_dma64_available(pa)) {
975 if (bus_dmatag_subregion(pa->pa_dmat64,
976 0,
977 (bus_addr_t)__MASK(48),
978 &sc->sc_dmat,
979 BUS_DMA_WAITOK) != 0) {
980 aprint_error_dev(self,
981 "WARNING: failed to restrict dma range,"
982 " falling back to parent bus dma range\n");
983 sc->sc_dmat = pa->pa_dmat64;
984 }
985 } else {
986 sc->sc_dmat = pa->pa_dmat;
987 }
988
989 if (vge_allocmem(sc) != 0)
990 return;
991
992 ifp = &sc->sc_ethercom.ec_if;
993 ifp->if_softc = sc;
994 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ);
995 ifp->if_mtu = ETHERMTU;
996 ifp->if_baudrate = IF_Gbps(1);
997 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
998 ifp->if_ioctl = vge_ioctl;
999 ifp->if_start = vge_start;
1000 ifp->if_init = vge_init;
1001 ifp->if_stop = vge_stop;
1002
1003 /*
1004 * We can support 802.1Q VLAN-sized frames and jumbo
1005 * Ethernet frames.
1006 */
1007 sc->sc_ethercom.ec_capabilities |=
1008 ETHERCAP_VLAN_MTU | ETHERCAP_JUMBO_MTU |
1009 ETHERCAP_VLAN_HWTAGGING;
1010 sc->sc_ethercom.ec_capenable |= ETHERCAP_VLAN_HWTAGGING;
1011
1012 /*
1013 * We can do IPv4/TCPv4/UDPv4 checksums in hardware.
1014 */
1015 ifp->if_capabilities |=
1016 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx |
1017 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx |
1018 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx;
1019
1020 #ifdef DEVICE_POLLING
1021 #ifdef IFCAP_POLLING
1022 ifp->if_capabilities |= IFCAP_POLLING;
1023 #endif
1024 #endif
1025 ifp->if_watchdog = vge_watchdog;
1026 IFQ_SET_MAXLEN(&ifp->if_snd, uimax(VGE_IFQ_MAXLEN, IFQ_MAXLEN));
1027 IFQ_SET_READY(&ifp->if_snd);
1028
1029 /*
1030 * Initialize our media structures and probe the MII.
1031 */
1032 mii->mii_ifp = ifp;
1033 mii->mii_readreg = vge_miibus_readreg;
1034 mii->mii_writereg = vge_miibus_writereg;
1035 mii->mii_statchg = vge_miibus_statchg;
1036
1037 sc->sc_ethercom.ec_mii = mii;
1038 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus);
1039 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY,
1040 MII_OFFSET_ANY, MIIF_DOPAUSE);
1041 if (LIST_FIRST(&mii->mii_phys) == NULL) {
1042 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL);
1043 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE);
1044 } else
1045 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO);
1046
1047 /*
1048 * Attach the interface.
1049 */
1050 if_attach(ifp);
1051 if_deferred_start_init(ifp, NULL);
1052 ether_ifattach(ifp, eaddr);
1053 ether_set_ifflags_cb(&sc->sc_ethercom, vge_ifflags_cb);
1054
1055 callout_init(&sc->sc_timeout, 0);
1056 callout_setfunc(&sc->sc_timeout, vge_tick, sc);
1057
1058 /*
1059 * Make sure the interface is shutdown during reboot.
1060 */
1061 if (pmf_device_register1(self, NULL, NULL, vge_shutdown))
1062 pmf_class_network_register(self, ifp);
1063 else
1064 aprint_error_dev(self, "couldn't establish power handler\n");
1065 }
1066
1067 static int
vge_newbuf(struct vge_softc * sc,int idx,struct mbuf * m)1068 vge_newbuf(struct vge_softc *sc, int idx, struct mbuf *m)
1069 {
1070 struct mbuf *m_new;
1071 struct vge_rxdesc *rxd;
1072 struct vge_rxsoft *rxs;
1073 bus_dmamap_t map;
1074 int i;
1075 #ifdef DIAGNOSTIC
1076 uint32_t rd_sts;
1077 #endif
1078
1079 m_new = NULL;
1080 if (m == NULL) {
1081 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1082 if (m_new == NULL)
1083 return ENOBUFS;
1084
1085 MCLGET(m_new, M_DONTWAIT);
1086 if ((m_new->m_flags & M_EXT) == 0) {
1087 m_freem(m_new);
1088 return ENOBUFS;
1089 }
1090
1091 m = m_new;
1092 } else
1093 m->m_data = m->m_ext.ext_buf;
1094
1095
1096 /*
1097 * This is part of an evil trick to deal with non-x86 platforms.
1098 * The VIA chip requires RX buffers to be aligned on 32-bit
1099 * boundaries, but that will hose non-x86 machines. To get around
1100 * this, we leave some empty space at the start of each buffer
1101 * and for non-x86 hosts, we copy the buffer back two bytes
1102 * to achieve word alignment. This is slightly more efficient
1103 * than allocating a new buffer, copying the contents, and
1104 * discarding the old buffer.
1105 */
1106 m->m_len = m->m_pkthdr.len = VGE_RX_BUFSIZE;
1107 #ifndef __NO_STRICT_ALIGNMENT
1108 m->m_data += VGE_RX_PAD;
1109 #endif
1110 rxs = &sc->sc_rxsoft[idx];
1111 map = rxs->rxs_dmamap;
1112
1113 if (bus_dmamap_load_mbuf(sc->sc_dmat, map, m, BUS_DMA_NOWAIT) != 0)
1114 goto out;
1115
1116 rxd = &sc->sc_rxdescs[idx];
1117
1118 #ifdef DIAGNOSTIC
1119 /* If this descriptor is still owned by the chip, bail. */
1120 VGE_RXDESCSYNC(sc, idx, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1121 rd_sts = le32toh(rxd->rd_sts);
1122 VGE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD);
1123 if (rd_sts & VGE_RDSTS_OWN) {
1124 panic("%s: tried to map busy RX descriptor",
1125 device_xname(sc->sc_dev));
1126 }
1127 #endif
1128
1129 rxs->rxs_mbuf = m;
1130 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,
1131 BUS_DMASYNC_PREREAD);
1132
1133 rxd->rd_buflen =
1134 htole16(VGE_BUFLEN(map->dm_segs[0].ds_len) | VGE_RXDESC_I);
1135 vge_set_rxaddr(rxd, map->dm_segs[0].ds_addr);
1136 rxd->rd_sts = 0;
1137 rxd->rd_ctl = 0;
1138 VGE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1139
1140 /*
1141 * Note: the manual fails to document the fact that for
1142 * proper operation, the driver needs to replentish the RX
1143 * DMA ring 4 descriptors at a time (rather than one at a
1144 * time, like most chips). We can allocate the new buffers
1145 * but we should not set the OWN bits until we're ready
1146 * to hand back 4 of them in one shot.
1147 */
1148
1149 #define VGE_RXCHUNK 4
1150 sc->sc_rx_consumed++;
1151 if (sc->sc_rx_consumed == VGE_RXCHUNK) {
1152 for (i = idx; i != idx - VGE_RXCHUNK; i--) {
1153 KASSERT(i >= 0);
1154 sc->sc_rxdescs[i].rd_sts |= htole32(VGE_RDSTS_OWN);
1155 VGE_RXDESCSYNC(sc, i,
1156 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1157 }
1158 sc->sc_rx_consumed = 0;
1159 }
1160
1161 return 0;
1162 out:
1163 m_freem(m_new);
1164 return ENOMEM;
1165 }
1166
1167 #ifndef __NO_STRICT_ALIGNMENT
1168 static inline void
vge_fixup_rx(struct mbuf * m)1169 vge_fixup_rx(struct mbuf *m)
1170 {
1171 int i;
1172 uint16_t *src, *dst;
1173
1174 src = mtod(m, uint16_t *);
1175 dst = src - 1;
1176
1177 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
1178 *dst++ = *src++;
1179
1180 m->m_data -= ETHER_ALIGN;
1181 }
1182 #endif
1183
1184 /*
1185 * RX handler. We support the reception of jumbo frames that have
1186 * been fragmented across multiple 2K mbuf cluster buffers.
1187 */
1188 static void
vge_rxeof(struct vge_softc * sc)1189 vge_rxeof(struct vge_softc *sc)
1190 {
1191 struct mbuf *m;
1192 struct ifnet *ifp;
1193 int idx, total_len, lim;
1194 struct vge_rxdesc *cur_rxd;
1195 struct vge_rxsoft *rxs;
1196 uint32_t rxstat, rxctl;
1197
1198 ifp = &sc->sc_ethercom.ec_if;
1199 lim = 0;
1200
1201 /* Invalidate the descriptor memory */
1202
1203 for (idx = sc->sc_rx_prodidx;; idx = VGE_NEXT_RXDESC(idx)) {
1204 cur_rxd = &sc->sc_rxdescs[idx];
1205
1206 VGE_RXDESCSYNC(sc, idx,
1207 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1208 rxstat = le32toh(cur_rxd->rd_sts);
1209 if ((rxstat & VGE_RDSTS_OWN) != 0) {
1210 VGE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD);
1211 break;
1212 }
1213
1214 rxctl = le32toh(cur_rxd->rd_ctl);
1215 rxs = &sc->sc_rxsoft[idx];
1216 m = rxs->rxs_mbuf;
1217 total_len = (rxstat & VGE_RDSTS_BUFSIZ) >> 16;
1218
1219 /* Invalidate the RX mbuf and unload its map */
1220
1221 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap,
1222 0, rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
1223 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap);
1224
1225 /*
1226 * If the 'start of frame' bit is set, this indicates
1227 * either the first fragment in a multi-fragment receive,
1228 * or an intermediate fragment. Either way, we want to
1229 * accumulate the buffers.
1230 */
1231 if (rxstat & VGE_RXPKT_SOF) {
1232 m->m_len = VGE_RX_BUFSIZE;
1233 if (sc->sc_rx_mhead == NULL)
1234 sc->sc_rx_mhead = sc->sc_rx_mtail = m;
1235 else {
1236 m->m_flags &= ~M_PKTHDR;
1237 sc->sc_rx_mtail->m_next = m;
1238 sc->sc_rx_mtail = m;
1239 }
1240 vge_newbuf(sc, idx, NULL);
1241 continue;
1242 }
1243
1244 /*
1245 * Bad/error frames will have the RXOK bit cleared.
1246 * However, there's one error case we want to allow:
1247 * if a VLAN tagged frame arrives and the chip can't
1248 * match it against the CAM filter, it considers this
1249 * a 'VLAN CAM filter miss' and clears the 'RXOK' bit.
1250 * We don't want to drop the frame though: our VLAN
1251 * filtering is done in software.
1252 */
1253 if ((rxstat & VGE_RDSTS_RXOK) == 0 &&
1254 (rxstat & VGE_RDSTS_VIDM) == 0 &&
1255 (rxstat & VGE_RDSTS_CSUMERR) == 0) {
1256 if_statinc(ifp, if_ierrors);
1257 /*
1258 * If this is part of a multi-fragment packet,
1259 * discard all the pieces.
1260 */
1261 if (sc->sc_rx_mhead != NULL) {
1262 m_freem(sc->sc_rx_mhead);
1263 sc->sc_rx_mhead = sc->sc_rx_mtail = NULL;
1264 }
1265 vge_newbuf(sc, idx, m);
1266 continue;
1267 }
1268
1269 /*
1270 * If allocating a replacement mbuf fails,
1271 * reload the current one.
1272 */
1273
1274 if (vge_newbuf(sc, idx, NULL)) {
1275 if_statinc(ifp, if_ierrors);
1276 if (sc->sc_rx_mhead != NULL) {
1277 m_freem(sc->sc_rx_mhead);
1278 sc->sc_rx_mhead = sc->sc_rx_mtail = NULL;
1279 }
1280 vge_newbuf(sc, idx, m);
1281 continue;
1282 }
1283
1284 if (sc->sc_rx_mhead != NULL) {
1285 m->m_len = total_len % VGE_RX_BUFSIZE;
1286 /*
1287 * Special case: if there's 4 bytes or less
1288 * in this buffer, the mbuf can be discarded:
1289 * the last 4 bytes is the CRC, which we don't
1290 * care about anyway.
1291 */
1292 if (m->m_len <= ETHER_CRC_LEN) {
1293 sc->sc_rx_mtail->m_len -=
1294 (ETHER_CRC_LEN - m->m_len);
1295 m_freem(m);
1296 } else {
1297 m->m_len -= ETHER_CRC_LEN;
1298 m->m_flags &= ~M_PKTHDR;
1299 sc->sc_rx_mtail->m_next = m;
1300 }
1301 m = sc->sc_rx_mhead;
1302 sc->sc_rx_mhead = sc->sc_rx_mtail = NULL;
1303 m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
1304 } else
1305 m->m_pkthdr.len = m->m_len = total_len - ETHER_CRC_LEN;
1306
1307 #ifndef __NO_STRICT_ALIGNMENT
1308 vge_fixup_rx(m);
1309 #endif
1310 m_set_rcvif(m, ifp);
1311
1312 /* Do RX checksumming if enabled */
1313 if (ifp->if_csum_flags_rx & M_CSUM_IPv4) {
1314
1315 /* Check IP header checksum */
1316 if (rxctl & VGE_RDCTL_IPPKT)
1317 m->m_pkthdr.csum_flags |= M_CSUM_IPv4;
1318 if ((rxctl & VGE_RDCTL_IPCSUMOK) == 0)
1319 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD;
1320 }
1321
1322 if (ifp->if_csum_flags_rx & M_CSUM_TCPv4) {
1323 /* Check UDP checksum */
1324 if (rxctl & VGE_RDCTL_TCPPKT)
1325 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4;
1326
1327 if ((rxctl & VGE_RDCTL_PROTOCSUMOK) == 0)
1328 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD;
1329 }
1330
1331 if (ifp->if_csum_flags_rx & M_CSUM_UDPv4) {
1332 /* Check UDP checksum */
1333 if (rxctl & VGE_RDCTL_UDPPKT)
1334 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4;
1335
1336 if ((rxctl & VGE_RDCTL_PROTOCSUMOK) == 0)
1337 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD;
1338 }
1339
1340 if (rxstat & VGE_RDSTS_VTAG) {
1341 /*
1342 * We use bswap16() here because:
1343 * On LE machines, tag is stored in BE as stream data.
1344 * On BE machines, tag is stored in BE as stream data
1345 * but it was already swapped by le32toh() above.
1346 */
1347 vlan_set_tag(m, bswap16(rxctl & VGE_RDCTL_VLANID));
1348 }
1349
1350 if_percpuq_enqueue(ifp->if_percpuq, m);
1351
1352 lim++;
1353 if (lim == VGE_NRXDESC)
1354 break;
1355 }
1356
1357 sc->sc_rx_prodidx = idx;
1358 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, lim);
1359 }
1360
1361 static void
vge_txeof(struct vge_softc * sc)1362 vge_txeof(struct vge_softc *sc)
1363 {
1364 struct ifnet *ifp;
1365 struct vge_txsoft *txs;
1366 uint32_t txstat;
1367 int idx;
1368
1369 ifp = &sc->sc_ethercom.ec_if;
1370
1371 for (idx = sc->sc_tx_considx;
1372 sc->sc_tx_free < VGE_NTXDESC;
1373 idx = VGE_NEXT_TXDESC(idx), sc->sc_tx_free++) {
1374 VGE_TXDESCSYNC(sc, idx,
1375 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1376 txstat = le32toh(sc->sc_txdescs[idx].td_sts);
1377 VGE_TXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD);
1378 if (txstat & VGE_TDSTS_OWN) {
1379 break;
1380 }
1381
1382 txs = &sc->sc_txsoft[idx];
1383 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 0,
1384 txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
1385 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap);
1386 m_freem(txs->txs_mbuf);
1387 txs->txs_mbuf = NULL;
1388 net_stat_ref_t nsr = IF_STAT_GETREF(ifp);
1389 if (txstat & (VGE_TDSTS_EXCESSCOLL | VGE_TDSTS_COLL))
1390 if_statinc_ref(ifp, nsr, if_collisions);
1391 if (txstat & VGE_TDSTS_TXERR)
1392 if_statinc_ref(ifp, nsr, if_oerrors);
1393 else
1394 if_statinc_ref(ifp, nsr, if_opackets);
1395 IF_STAT_PUTREF(ifp);
1396 }
1397
1398 sc->sc_tx_considx = idx;
1399
1400 /*
1401 * If not all descriptors have been released reaped yet,
1402 * reload the timer so that we will eventually get another
1403 * interrupt that will cause us to re-enter this routine.
1404 * This is done in case the transmitter has gone idle.
1405 */
1406 if (sc->sc_tx_free < VGE_NTXDESC)
1407 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE);
1408 else
1409 ifp->if_timer = 0;
1410 }
1411
1412 static void
vge_tick(void * arg)1413 vge_tick(void *arg)
1414 {
1415 struct vge_softc *sc;
1416 struct ifnet *ifp;
1417 struct mii_data *mii;
1418 int s;
1419
1420 sc = arg;
1421 ifp = &sc->sc_ethercom.ec_if;
1422 mii = &sc->sc_mii;
1423
1424 s = splnet();
1425
1426 callout_schedule(&sc->sc_timeout, hz);
1427
1428 mii_tick(mii);
1429 if (sc->sc_link) {
1430 if ((mii->mii_media_status & IFM_ACTIVE) == 0)
1431 sc->sc_link = 0;
1432 } else {
1433 if (mii->mii_media_status & IFM_ACTIVE &&
1434 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1435 sc->sc_link = 1;
1436 if (!IFQ_IS_EMPTY(&ifp->if_snd))
1437 vge_start(ifp);
1438 }
1439 }
1440
1441 splx(s);
1442 }
1443
1444 static int
vge_intr(void * arg)1445 vge_intr(void *arg)
1446 {
1447 struct vge_softc *sc;
1448 struct ifnet *ifp;
1449 uint32_t status;
1450 int claim;
1451
1452 sc = arg;
1453 claim = 0;
1454 if (sc->sc_suspended) {
1455 return claim;
1456 }
1457
1458 ifp = &sc->sc_ethercom.ec_if;
1459
1460 if ((ifp->if_flags & IFF_UP) == 0) {
1461 return claim;
1462 }
1463
1464 /* Disable interrupts */
1465 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK);
1466
1467 for (;;) {
1468
1469 status = CSR_READ_4(sc, VGE_ISR);
1470 /* If the card has gone away the read returns 0xffffffff. */
1471 if (status == 0xFFFFFFFF)
1472 break;
1473
1474 if (status) {
1475 claim = 1;
1476 CSR_WRITE_4(sc, VGE_ISR, status);
1477 }
1478
1479 if ((status & VGE_INTRS) == 0)
1480 break;
1481
1482 if (status & (VGE_ISR_RXOK | VGE_ISR_RXOK_HIPRIO))
1483 vge_rxeof(sc);
1484
1485 if (status & (VGE_ISR_RXOFLOW | VGE_ISR_RXNODESC)) {
1486 vge_rxeof(sc);
1487 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN);
1488 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK);
1489 }
1490
1491 if (status & (VGE_ISR_TXOK0 | VGE_ISR_TIMER0))
1492 vge_txeof(sc);
1493
1494 if (status & (VGE_ISR_TXDMA_STALL | VGE_ISR_RXDMA_STALL))
1495 vge_init(ifp);
1496
1497 if (status & VGE_ISR_LINKSTS)
1498 vge_tick(sc);
1499 }
1500
1501 /* Re-enable interrupts */
1502 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK);
1503
1504 if (claim)
1505 if_schedule_deferred_start(ifp);
1506
1507 return claim;
1508 }
1509
1510 static int
vge_encap(struct vge_softc * sc,struct mbuf * m_head,int idx)1511 vge_encap(struct vge_softc *sc, struct mbuf *m_head, int idx)
1512 {
1513 struct vge_txsoft *txs;
1514 struct vge_txdesc *txd;
1515 struct vge_txfrag *f;
1516 struct mbuf *m_new;
1517 bus_dmamap_t map;
1518 int m_csumflags, seg, error, flags;
1519 size_t sz;
1520 uint32_t td_sts, td_ctl;
1521
1522 KASSERT(sc->sc_tx_free > 0);
1523
1524 txd = &sc->sc_txdescs[idx];
1525
1526 #ifdef DIAGNOSTIC
1527 /* If this descriptor is still owned by the chip, bail. */
1528 VGE_TXDESCSYNC(sc, idx,
1529 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1530 td_sts = le32toh(txd->td_sts);
1531 VGE_TXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD);
1532 if (td_sts & VGE_TDSTS_OWN) {
1533 return ENOBUFS;
1534 }
1535 #endif
1536
1537 /*
1538 * Preserve m_pkthdr.csum_flags here since m_head might be
1539 * updated by m_defrag()
1540 */
1541 m_csumflags = m_head->m_pkthdr.csum_flags;
1542
1543 txs = &sc->sc_txsoft[idx];
1544 map = txs->txs_dmamap;
1545 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m_head, BUS_DMA_NOWAIT);
1546
1547 /* If too many segments to map, coalesce */
1548 if (error == EFBIG ||
1549 (m_head->m_pkthdr.len < ETHER_PAD_LEN &&
1550 map->dm_nsegs == VGE_TX_FRAGS)) {
1551 m_new = m_defrag(m_head, M_DONTWAIT);
1552 if (m_new == NULL)
1553 return EFBIG;
1554
1555 error = bus_dmamap_load_mbuf(sc->sc_dmat, map,
1556 m_new, BUS_DMA_NOWAIT);
1557 if (error) {
1558 m_freem(m_new);
1559 return error;
1560 }
1561
1562 m_head = m_new;
1563 } else if (error)
1564 return error;
1565
1566 txs->txs_mbuf = m_head;
1567
1568 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,
1569 BUS_DMASYNC_PREWRITE);
1570
1571 for (seg = 0, f = &txd->td_frag[0]; seg < map->dm_nsegs; seg++, f++) {
1572 f->tf_buflen = htole16(VGE_BUFLEN(map->dm_segs[seg].ds_len));
1573 vge_set_txaddr(f, map->dm_segs[seg].ds_addr);
1574 }
1575
1576 /* Argh. This chip does not autopad short frames */
1577 sz = m_head->m_pkthdr.len;
1578 if (sz < ETHER_PAD_LEN) {
1579 f->tf_buflen = htole16(VGE_BUFLEN(ETHER_PAD_LEN - sz));
1580 vge_set_txaddr(f, VGE_CDPADADDR(sc));
1581 sz = ETHER_PAD_LEN;
1582 seg++;
1583 }
1584 VGE_TXFRAGSYNC(sc, idx, seg, BUS_DMASYNC_PREWRITE);
1585
1586 /*
1587 * When telling the chip how many segments there are, we
1588 * must use nsegs + 1 instead of just nsegs. Darned if I
1589 * know why.
1590 */
1591 seg++;
1592
1593 flags = 0;
1594 if (m_csumflags & M_CSUM_IPv4)
1595 flags |= VGE_TDCTL_IPCSUM;
1596 if (m_csumflags & M_CSUM_TCPv4)
1597 flags |= VGE_TDCTL_TCPCSUM;
1598 if (m_csumflags & M_CSUM_UDPv4)
1599 flags |= VGE_TDCTL_UDPCSUM;
1600 td_sts = sz << 16;
1601 td_ctl = flags | (seg << 28) | VGE_TD_LS_NORM;
1602
1603 if (sz > ETHERMTU + ETHER_HDR_LEN)
1604 td_ctl |= VGE_TDCTL_JUMBO;
1605
1606 /*
1607 * Set up hardware VLAN tagging.
1608 */
1609 if (vlan_has_tag(m_head)) {
1610 /*
1611 * No need htons() here since vge(4) chip assumes
1612 * that tags are written in little endian and
1613 * we already use htole32() here.
1614 */
1615 td_ctl |= vlan_get_tag(m_head) | VGE_TDCTL_VTAG;
1616 }
1617 txd->td_ctl = htole32(td_ctl);
1618 txd->td_sts = htole32(td_sts);
1619 VGE_TXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1620
1621 txd->td_sts = htole32(VGE_TDSTS_OWN | td_sts);
1622 VGE_TXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1623
1624 sc->sc_tx_free--;
1625
1626 return 0;
1627 }
1628
1629 /*
1630 * Main transmit routine.
1631 */
1632
1633 static void
vge_start(struct ifnet * ifp)1634 vge_start(struct ifnet *ifp)
1635 {
1636 struct vge_softc *sc;
1637 struct vge_txsoft *txs;
1638 struct mbuf *m_head;
1639 int idx, pidx, ofree, error;
1640
1641 sc = ifp->if_softc;
1642
1643 if (!sc->sc_link ||
1644 (ifp->if_flags & IFF_RUNNING) == 0) {
1645 return;
1646 }
1647
1648 m_head = NULL;
1649 idx = sc->sc_tx_prodidx;
1650 pidx = VGE_PREV_TXDESC(idx);
1651 ofree = sc->sc_tx_free;
1652
1653 /*
1654 * Loop through the send queue, setting up transmit descriptors
1655 * until we drain the queue, or use up all available transmit
1656 * descriptors.
1657 */
1658 while (sc->sc_tx_free != 0) {
1659 /* Grab a packet off the queue. */
1660 IFQ_POLL(&ifp->if_snd, m_head);
1661 if (m_head == NULL)
1662 break;
1663
1664 txs = &sc->sc_txsoft[idx];
1665 KASSERT(txs->txs_mbuf == NULL);
1666
1667 if ((error = vge_encap(sc, m_head, idx))) {
1668 if (error == EFBIG) {
1669 printf("%s: Tx packet consumes too many "
1670 "DMA segments, dropping...\n",
1671 device_xname(sc->sc_dev));
1672 IFQ_DEQUEUE(&ifp->if_snd, m_head);
1673 m_freem(m_head);
1674 continue;
1675 }
1676
1677 /*
1678 * Short on resources, just stop for now.
1679 */
1680 break;
1681 }
1682
1683 IFQ_DEQUEUE(&ifp->if_snd, m_head);
1684
1685 /*
1686 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET.
1687 */
1688
1689 sc->sc_txdescs[pidx].td_frag[0].tf_buflen |=
1690 htole16(VGE_TXDESC_Q);
1691 VGE_TXFRAGSYNC(sc, pidx, 1,
1692 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1693
1694 if (txs->txs_mbuf != m_head) {
1695 m_freem(m_head);
1696 m_head = txs->txs_mbuf;
1697 }
1698
1699 pidx = idx;
1700 idx = VGE_NEXT_TXDESC(idx);
1701
1702 /*
1703 * If there's a BPF listener, bounce a copy of this frame
1704 * to him.
1705 */
1706 bpf_mtap(ifp, m_head, BPF_D_OUT);
1707 }
1708
1709 if (sc->sc_tx_free < ofree) {
1710 /* TX packet queued */
1711
1712 sc->sc_tx_prodidx = idx;
1713
1714 /* Issue a transmit command. */
1715 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0);
1716
1717 /*
1718 * Use the countdown timer for interrupt moderation.
1719 * 'TX done' interrupts are disabled. Instead, we reset the
1720 * countdown timer, which will begin counting until it hits
1721 * the value in the SSTIMER register, and then trigger an
1722 * interrupt. Each time we set the TIMER0_ENABLE bit, the
1723 * the timer count is reloaded. Only when the transmitter
1724 * is idle will the timer hit 0 and an interrupt fire.
1725 */
1726 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE);
1727
1728 /*
1729 * Set a timeout in case the chip goes out to lunch.
1730 */
1731 ifp->if_timer = 5;
1732 }
1733 }
1734
1735 static int
vge_init(struct ifnet * ifp)1736 vge_init(struct ifnet *ifp)
1737 {
1738 struct vge_softc *sc;
1739 int i, rc = 0;
1740
1741 sc = ifp->if_softc;
1742
1743 /*
1744 * Cancel pending I/O and free all RX/TX buffers.
1745 */
1746 vge_stop(ifp, 0);
1747 vge_reset(sc);
1748
1749 /* Initialize the RX descriptors and mbufs. */
1750 memset(sc->sc_rxdescs, 0, sizeof(sc->sc_rxdescs));
1751 sc->sc_rx_consumed = 0;
1752 for (i = 0; i < VGE_NRXDESC; i++) {
1753 if (vge_newbuf(sc, i, NULL) == ENOBUFS) {
1754 printf("%s: unable to allocate or map rx buffer\n",
1755 device_xname(sc->sc_dev));
1756 return 1; /* XXX */
1757 }
1758 }
1759 sc->sc_rx_prodidx = 0;
1760 sc->sc_rx_mhead = sc->sc_rx_mtail = NULL;
1761
1762 /* Initialize the TX descriptors and mbufs. */
1763 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs));
1764 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap,
1765 VGE_CDTXOFF(0), sizeof(sc->sc_txdescs),
1766 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1767 for (i = 0; i < VGE_NTXDESC; i++)
1768 sc->sc_txsoft[i].txs_mbuf = NULL;
1769
1770 sc->sc_tx_prodidx = 0;
1771 sc->sc_tx_considx = 0;
1772 sc->sc_tx_free = VGE_NTXDESC;
1773
1774 /* Set our station address */
1775 for (i = 0; i < ETHER_ADDR_LEN; i++)
1776 CSR_WRITE_1(sc, VGE_PAR0 + i, sc->sc_eaddr[i]);
1777
1778 /*
1779 * Set receive FIFO threshold. Also allow transmission and
1780 * reception of VLAN tagged frames.
1781 */
1782 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR | VGE_RXCFG_VTAGOPT);
1783 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES | VGE_VTAG_OPT2);
1784
1785 /* Set DMA burst length */
1786 CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN);
1787 CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128);
1788
1789 CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO | VGE_TXCFG_NONBLK);
1790
1791 /* Set collision backoff algorithm */
1792 CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM |
1793 VGE_CHIPCFG1_CAP | VGE_CHIPCFG1_MBA | VGE_CHIPCFG1_BAKOPT);
1794 CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFFSET);
1795
1796 /* Disable LPSEL field in priority resolution */
1797 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS);
1798
1799 /*
1800 * Load the addresses of the DMA queues into the chip.
1801 * Note that we only use one transmit queue.
1802 */
1803
1804 CSR_WRITE_4(sc, VGE_TXDESC_HIADDR, VGE_ADDR_HI(VGE_CDTXADDR(sc, 0)));
1805 CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0, VGE_ADDR_LO(VGE_CDTXADDR(sc, 0)));
1806 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_NTXDESC - 1);
1807
1808 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, VGE_ADDR_LO(VGE_CDRXADDR(sc, 0)));
1809 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_NRXDESC - 1);
1810 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_NRXDESC);
1811
1812 /* Enable and wake up the RX descriptor queue */
1813 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN);
1814 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK);
1815
1816 /* Enable the TX descriptor queue */
1817 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0);
1818
1819 /* Set up the receive filter -- allow large frames for VLANs. */
1820 CSR_WRITE_1(sc, VGE_RXCTL, VGE_RXCTL_RX_UCAST | VGE_RXCTL_RX_GIANT);
1821
1822 /* If we want promiscuous mode, set the allframes bit. */
1823 if (ifp->if_flags & IFF_PROMISC) {
1824 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC);
1825 }
1826
1827 /* Set capture broadcast bit to capture broadcast frames. */
1828 if (ifp->if_flags & IFF_BROADCAST) {
1829 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_BCAST);
1830 }
1831
1832 /* Set multicast bit to capture multicast frames. */
1833 if (ifp->if_flags & IFF_MULTICAST) {
1834 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_MCAST);
1835 }
1836
1837 /* Init the cam filter. */
1838 vge_cam_clear(sc);
1839
1840 /* Init the multicast filter. */
1841 vge_setmulti(sc);
1842
1843 /* Enable flow control */
1844
1845 CSR_WRITE_1(sc, VGE_CRS2, 0x8B);
1846
1847 /* Enable jumbo frame reception (if desired) */
1848
1849 /* Start the MAC. */
1850 CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP);
1851 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL);
1852 CSR_WRITE_1(sc, VGE_CRS0,
1853 VGE_CR0_TX_ENABLE | VGE_CR0_RX_ENABLE | VGE_CR0_START);
1854
1855 /*
1856 * Configure one-shot timer for microsecond
1857 * resolution and load it for 500 usecs.
1858 */
1859 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_TIMER0_RES);
1860 CSR_WRITE_2(sc, VGE_SSTIMER, 400);
1861
1862 /*
1863 * Configure interrupt moderation for receive. Enable
1864 * the holdoff counter and load it, and set the RX
1865 * suppression count to the number of descriptors we
1866 * want to allow before triggering an interrupt.
1867 * The holdoff timer is in units of 20 usecs.
1868 */
1869
1870 #ifdef notyet
1871 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_TXINTSUP_DISABLE);
1872 /* Select the interrupt holdoff timer page. */
1873 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
1874 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF);
1875 CSR_WRITE_1(sc, VGE_INTHOLDOFF, 10); /* ~200 usecs */
1876
1877 /* Enable use of the holdoff timer. */
1878 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF);
1879 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_SC_RELOAD);
1880
1881 /* Select the RX suppression threshold page. */
1882 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
1883 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR);
1884 CSR_WRITE_1(sc, VGE_RXSUPPTHR, 64); /* interrupt after 64 packets */
1885
1886 /* Restore the page select bits. */
1887 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
1888 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR);
1889 #endif
1890
1891 #ifdef DEVICE_POLLING
1892 /*
1893 * Disable interrupts if we are polling.
1894 */
1895 if (ifp->if_flags & IFF_POLLING) {
1896 CSR_WRITE_4(sc, VGE_IMR, 0);
1897 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK);
1898 } else /* otherwise ... */
1899 #endif /* DEVICE_POLLING */
1900 {
1901 /*
1902 * Enable interrupts.
1903 */
1904 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS);
1905 CSR_WRITE_4(sc, VGE_ISR, 0);
1906 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK);
1907 }
1908
1909 if ((rc = ether_mediachange(ifp)) != 0)
1910 goto out;
1911
1912 ifp->if_flags |= IFF_RUNNING;
1913
1914 sc->sc_if_flags = 0;
1915 sc->sc_link = 0;
1916
1917 callout_schedule(&sc->sc_timeout, hz);
1918
1919 out:
1920 return rc;
1921 }
1922
1923 static void
vge_miibus_statchg(struct ifnet * ifp)1924 vge_miibus_statchg(struct ifnet *ifp)
1925 {
1926 struct vge_softc *sc = ifp->if_softc;
1927 struct mii_data *mii = &sc->sc_mii;
1928 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
1929 uint8_t dctl;
1930
1931 /*
1932 * If the user manually selects a media mode, we need to turn
1933 * on the forced MAC mode bit in the DIAGCTL register. If the
1934 * user happens to choose a full duplex mode, we also need to
1935 * set the 'force full duplex' bit. This applies only to
1936 * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC
1937 * mode is disabled, and in 1000baseT mode, full duplex is
1938 * always implied, so we turn on the forced mode bit but leave
1939 * the FDX bit cleared.
1940 */
1941 dctl = CSR_READ_1(sc, VGE_DIAGCTL);
1942
1943 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) {
1944 dctl &= ~VGE_DIAGCTL_MACFORCE;
1945 dctl &= ~VGE_DIAGCTL_FDXFORCE;
1946 } else {
1947 u_int ifmword;
1948
1949 /* If the link is up, use the current active media. */
1950 if ((mii->mii_media_status & IFM_ACTIVE) != 0)
1951 ifmword = mii->mii_media_active;
1952 else
1953 ifmword = ife->ifm_media;
1954
1955 dctl |= VGE_DIAGCTL_MACFORCE;
1956 if ((ifmword & IFM_FDX) != 0)
1957 dctl |= VGE_DIAGCTL_FDXFORCE;
1958 else
1959 dctl &= ~VGE_DIAGCTL_FDXFORCE;
1960
1961 if (IFM_SUBTYPE(ifmword) == IFM_1000_T) {
1962 /*
1963 * It means the user setting is not auto but it's
1964 * 1000baseT-FDX or 1000baseT.
1965 */
1966 dctl |= VGE_DIAGCTL_GMII;
1967 } else
1968 dctl &= ~VGE_DIAGCTL_GMII;
1969 }
1970
1971 CSR_WRITE_1(sc, VGE_DIAGCTL, dctl);
1972 }
1973
1974 static int
vge_ifflags_cb(struct ethercom * ec)1975 vge_ifflags_cb(struct ethercom *ec)
1976 {
1977 struct ifnet *ifp = &ec->ec_if;
1978 struct vge_softc *sc = ifp->if_softc;
1979 u_short change = ifp->if_flags ^ sc->sc_if_flags;
1980
1981 if ((change & ~(IFF_CANTCHANGE | IFF_DEBUG)) != 0)
1982 return ENETRESET;
1983 else if ((change & IFF_PROMISC) == 0)
1984 return 0;
1985
1986 if ((ifp->if_flags & IFF_PROMISC) == 0)
1987 CSR_CLRBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC);
1988 else
1989 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC);
1990 vge_setmulti(sc);
1991 return 0;
1992 }
1993
1994 static int
vge_ioctl(struct ifnet * ifp,u_long command,void * data)1995 vge_ioctl(struct ifnet *ifp, u_long command, void *data)
1996 {
1997 struct vge_softc *sc;
1998 int s, error;
1999
2000 sc = ifp->if_softc;
2001 error = 0;
2002
2003 s = splnet();
2004
2005 if ((error = ether_ioctl(ifp, command, data)) == ENETRESET) {
2006 error = 0;
2007 if (command != SIOCADDMULTI && command != SIOCDELMULTI)
2008 ;
2009 else if (ifp->if_flags & IFF_RUNNING) {
2010 /*
2011 * Multicast list has changed; set the hardware filter
2012 * accordingly.
2013 */
2014 vge_setmulti(sc);
2015 }
2016 }
2017 sc->sc_if_flags = ifp->if_flags;
2018
2019 splx(s);
2020 return error;
2021 }
2022
2023 static void
vge_watchdog(struct ifnet * ifp)2024 vge_watchdog(struct ifnet *ifp)
2025 {
2026 struct vge_softc *sc;
2027 int s;
2028
2029 sc = ifp->if_softc;
2030 s = splnet();
2031 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev));
2032 if_statinc(ifp, if_oerrors);
2033
2034 vge_txeof(sc);
2035 vge_rxeof(sc);
2036
2037 vge_init(ifp);
2038
2039 splx(s);
2040 }
2041
2042 /*
2043 * Stop the adapter and free any mbufs allocated to the
2044 * RX and TX lists.
2045 */
2046 static void
vge_stop(struct ifnet * ifp,int disable)2047 vge_stop(struct ifnet *ifp, int disable)
2048 {
2049 struct vge_softc *sc = ifp->if_softc;
2050 struct vge_txsoft *txs;
2051 struct vge_rxsoft *rxs;
2052 int i, s;
2053
2054 s = splnet();
2055 ifp->if_timer = 0;
2056
2057 ifp->if_flags &= ~IFF_RUNNING;
2058 #ifdef DEVICE_POLLING
2059 ether_poll_deregister(ifp);
2060 #endif /* DEVICE_POLLING */
2061
2062 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK);
2063 CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP);
2064 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF);
2065 CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF);
2066 CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF);
2067 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0);
2068
2069 if (sc->sc_rx_mhead != NULL) {
2070 m_freem(sc->sc_rx_mhead);
2071 sc->sc_rx_mhead = sc->sc_rx_mtail = NULL;
2072 }
2073
2074 /* Free the TX list buffers. */
2075
2076 for (i = 0; i < VGE_NTXDESC; i++) {
2077 txs = &sc->sc_txsoft[i];
2078 if (txs->txs_mbuf != NULL) {
2079 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap);
2080 m_freem(txs->txs_mbuf);
2081 txs->txs_mbuf = NULL;
2082 }
2083 }
2084
2085 /* Free the RX list buffers. */
2086
2087 for (i = 0; i < VGE_NRXDESC; i++) {
2088 rxs = &sc->sc_rxsoft[i];
2089 if (rxs->rxs_mbuf != NULL) {
2090 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap);
2091 m_freem(rxs->rxs_mbuf);
2092 rxs->rxs_mbuf = NULL;
2093 }
2094 }
2095
2096 splx(s);
2097 }
2098
2099 #if VGE_POWER_MANAGEMENT
2100 /*
2101 * Device suspend routine. Stop the interface and save some PCI
2102 * settings in case the BIOS doesn't restore them properly on
2103 * resume.
2104 */
2105 static int
vge_suspend(device_t dev)2106 vge_suspend(device_t dev)
2107 {
2108 struct vge_softc *sc;
2109 int i;
2110
2111 sc = device_get_softc(dev);
2112
2113 vge_stop(sc);
2114
2115 for (i = 0; i < 5; i++)
2116 sc->sc_saved_maps[i] =
2117 pci_read_config(dev, PCIR_MAPS + i * 4, 4);
2118 sc->sc_saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
2119 sc->sc_saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
2120 sc->sc_saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
2121 sc->sc_saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
2122
2123 sc->suspended = 1;
2124
2125 return 0;
2126 }
2127
2128 /*
2129 * Device resume routine. Restore some PCI settings in case the BIOS
2130 * doesn't, re-enable busmastering, and restart the interface if
2131 * appropriate.
2132 */
2133 static int
vge_resume(device_t dev)2134 vge_resume(device_t dev)
2135 {
2136 struct vge_softc *sc;
2137 struct ifnet *ifp;
2138 int i;
2139
2140 sc = device_private(dev);
2141 ifp = &sc->sc_ethercom.ec_if;
2142
2143 /* better way to do this? */
2144 for (i = 0; i < 5; i++)
2145 pci_write_config(dev, PCIR_MAPS + i * 4,
2146 sc->sc_saved_maps[i], 4);
2147 pci_write_config(dev, PCIR_BIOS, sc->sc_saved_biosaddr, 4);
2148 pci_write_config(dev, PCIR_INTLINE, sc->sc_saved_intline, 1);
2149 pci_write_config(dev, PCIR_CACHELNSZ, sc->sc_saved_cachelnsz, 1);
2150 pci_write_config(dev, PCIR_LATTIMER, sc->sc_saved_lattimer, 1);
2151
2152 /* reenable busmastering */
2153 pci_enable_busmaster(dev);
2154 pci_enable_io(dev, SYS_RES_MEMORY);
2155
2156 /* reinitialize interface if necessary */
2157 if (ifp->if_flags & IFF_UP)
2158 vge_init(sc);
2159
2160 sc->suspended = 0;
2161
2162 return 0;
2163 }
2164 #endif
2165
2166 /*
2167 * Stop all chip I/O so that the kernel's probe routines don't
2168 * get confused by errant DMAs when rebooting.
2169 */
2170 static bool
vge_shutdown(device_t self,int howto)2171 vge_shutdown(device_t self, int howto)
2172 {
2173 struct vge_softc *sc;
2174
2175 sc = device_private(self);
2176 vge_stop(&sc->sc_ethercom.ec_if, 1);
2177
2178 return true;
2179 }
2180
2181 static void
vge_clrwol(struct vge_softc * sc)2182 vge_clrwol(struct vge_softc *sc)
2183 {
2184 uint8_t val;
2185
2186 val = CSR_READ_1(sc, VGE_PWRSTAT);
2187 val &= ~VGE_STICKHW_SWPTAG;
2188 CSR_WRITE_1(sc, VGE_PWRSTAT, val);
2189 /* Disable WOL and clear power state indicator. */
2190 val = CSR_READ_1(sc, VGE_PWRSTAT);
2191 val &= ~(VGE_STICKHW_DS0 | VGE_STICKHW_DS1);
2192 CSR_WRITE_1(sc, VGE_PWRSTAT, val);
2193
2194 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_GMII);
2195 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE);
2196
2197 /* Clear WOL on pattern match. */
2198 CSR_WRITE_1(sc, VGE_WOLCR0C, VGE_WOLCR0_PATTERN_ALL);
2199 /* Disable WOL on magic/unicast packet. */
2200 CSR_WRITE_1(sc, VGE_WOLCR1C, 0x0F);
2201 CSR_WRITE_1(sc, VGE_WOLCFGC, VGE_WOLCFG_SAB | VGE_WOLCFG_SAM |
2202 VGE_WOLCFG_PMEOVR);
2203 /* Clear WOL status on pattern match. */
2204 CSR_WRITE_1(sc, VGE_WOLSR0C, 0xFF);
2205 CSR_WRITE_1(sc, VGE_WOLSR1C, 0xFF);
2206 }
2207