1 /* Definition of RISC-V target for GNU compiler. 2 Copyright (C) 2016-2022 Free Software Foundation, Inc. 3 Contributed by Andrew Waterman (andrew@sifive.com). 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3, or (at your option) 10 any later version. 11 12 GCC is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GCC; see the file COPYING3. If not see 19 <http://www.gnu.org/licenses/>. */ 20 21 #ifndef GCC_RISCV_OPTS_H 22 #define GCC_RISCV_OPTS_H 23 24 enum riscv_abi_type { 25 ABI_ILP32, 26 ABI_ILP32E, 27 ABI_ILP32F, 28 ABI_ILP32D, 29 ABI_LP64, 30 ABI_LP64F, 31 ABI_LP64D 32 }; 33 extern enum riscv_abi_type riscv_abi; 34 35 enum riscv_code_model { 36 CM_MEDLOW, 37 CM_MEDANY, 38 CM_PIC 39 }; 40 extern enum riscv_code_model riscv_cmodel; 41 42 enum riscv_isa_spec_class { 43 ISA_SPEC_CLASS_NONE, 44 45 ISA_SPEC_CLASS_2P2, 46 ISA_SPEC_CLASS_20190608, 47 ISA_SPEC_CLASS_20191213 48 }; 49 50 extern enum riscv_isa_spec_class riscv_isa_spec; 51 52 /* Keep this list in sync with define_attr "tune" in riscv.md. */ 53 enum riscv_microarchitecture_type { 54 generic, 55 sifive_7 56 }; 57 extern enum riscv_microarchitecture_type riscv_microarchitecture; 58 59 enum riscv_align_data { 60 riscv_align_data_type_xlen, 61 riscv_align_data_type_natural 62 }; 63 64 /* Where to get the canary for the stack protector. */ 65 enum stack_protector_guard { 66 SSP_TLS, /* per-thread canary in TLS block */ 67 SSP_GLOBAL /* global canary */ 68 }; 69 70 #define MASK_ZICSR (1 << 0) 71 #define MASK_ZIFENCEI (1 << 1) 72 73 #define TARGET_ZICSR ((riscv_zi_subext & MASK_ZICSR) != 0) 74 #define TARGET_ZIFENCEI ((riscv_zi_subext & MASK_ZIFENCEI) != 0) 75 76 #define MASK_ZBA (1 << 0) 77 #define MASK_ZBB (1 << 1) 78 #define MASK_ZBC (1 << 2) 79 #define MASK_ZBS (1 << 3) 80 81 #define TARGET_ZBA ((riscv_zb_subext & MASK_ZBA) != 0) 82 #define TARGET_ZBB ((riscv_zb_subext & MASK_ZBB) != 0) 83 #define TARGET_ZBC ((riscv_zb_subext & MASK_ZBC) != 0) 84 #define TARGET_ZBS ((riscv_zb_subext & MASK_ZBS) != 0) 85 86 #define MASK_ZBKB (1 << 0) 87 #define MASK_ZBKC (1 << 1) 88 #define MASK_ZBKX (1 << 2) 89 #define MASK_ZKNE (1 << 3) 90 #define MASK_ZKND (1 << 4) 91 #define MASK_ZKNH (1 << 5) 92 #define MASK_ZKR (1 << 6) 93 #define MASK_ZKSED (1 << 7) 94 #define MASK_ZKSH (1 << 8) 95 #define MASK_ZKT (1 << 9) 96 97 #define TARGET_ZBKB ((riscv_zk_subext & MASK_ZBKB) != 0) 98 #define TARGET_ZBKC ((riscv_zk_subext & MASK_ZBKC) != 0) 99 #define TARGET_ZBKX ((riscv_zk_subext & MASK_ZBKX) != 0) 100 #define TARGET_ZKNE ((riscv_zk_subext & MASK_ZKNE) != 0) 101 #define TARGET_ZKND ((riscv_zk_subext & MASK_ZKND) != 0) 102 #define TARGET_ZKNH ((riscv_zk_subext & MASK_ZKNH) != 0) 103 #define TARGET_ZKR ((riscv_zk_subext & MASK_ZKR) != 0) 104 #define TARGET_ZKSED ((riscv_zk_subext & MASK_ZKSED) != 0) 105 #define TARGET_ZKSH ((riscv_zk_subext & MASK_ZKSH) != 0) 106 #define TARGET_ZKT ((riscv_zk_subext & MASK_ZKT) != 0) 107 108 #define MASK_VECTOR_ELEN_32 (1 << 0) 109 #define MASK_VECTOR_ELEN_64 (1 << 1) 110 #define MASK_VECTOR_ELEN_FP_32 (1 << 2) 111 #define MASK_VECTOR_ELEN_FP_64 (1 << 3) 112 113 #define TARGET_VECTOR_ELEN_32 \ 114 ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_32) != 0) 115 #define TARGET_VECTOR_ELEN_64 \ 116 ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_64) != 0) 117 #define TARGET_VECTOR_ELEN_FP_32 \ 118 ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_FP_32) != 0) 119 #define TARGET_VECTOR_ELEN_FP_64 \ 120 ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_FP_64) != 0) 121 122 #define MASK_ZVL32B (1 << 0) 123 #define MASK_ZVL64B (1 << 1) 124 #define MASK_ZVL128B (1 << 2) 125 #define MASK_ZVL256B (1 << 3) 126 #define MASK_ZVL512B (1 << 4) 127 #define MASK_ZVL1024B (1 << 5) 128 #define MASK_ZVL2048B (1 << 6) 129 #define MASK_ZVL4096B (1 << 7) 130 #define MASK_ZVL8192B (1 << 8) 131 #define MASK_ZVL16384B (1 << 9) 132 #define MASK_ZVL32768B (1 << 10) 133 #define MASK_ZVL65536B (1 << 11) 134 135 #define TARGET_ZVL32B ((riscv_zvl_flags & MASK_ZVL32B) != 0) 136 #define TARGET_ZVL64B ((riscv_zvl_flags & MASK_ZVL64B) != 0) 137 #define TARGET_ZVL128B ((riscv_zvl_flags & MASK_ZVL128B) != 0) 138 #define TARGET_ZVL256B ((riscv_zvl_flags & MASK_ZVL256B) != 0) 139 #define TARGET_ZVL512B ((riscv_zvl_flags & MASK_ZVL512B) != 0) 140 #define TARGET_ZVL1024B ((riscv_zvl_flags & MASK_ZVL1024B) != 0) 141 #define TARGET_ZVL2048B ((riscv_zvl_flags & MASK_ZVL2048B) != 0) 142 #define TARGET_ZVL4096B ((riscv_zvl_flags & MASK_ZVL4096B) != 0) 143 #define TARGET_ZVL8192B ((riscv_zvl_flags & MASK_ZVL8192B) != 0) 144 #define TARGET_ZVL16384B ((riscv_zvl_flags & MASK_ZVL16384B) != 0) 145 #define TARGET_ZVL32768B ((riscv_zvl_flags & MASK_ZVL32768B) != 0) 146 #define TARGET_ZVL65536B ((riscv_zvl_flags & MASK_ZVL65536B) != 0) 147 148 /* Bit of riscv_zvl_flags will set contintuly, N-1 bit will set if N-bit is 149 set, e.g. MASK_ZVL64B has set then MASK_ZVL32B is set, so we can use 150 popcount to caclulate the minimal VLEN. */ 151 #define TARGET_MIN_VLEN \ 152 ((riscv_zvl_flags == 0) \ 153 ? 0 \ 154 : 32 << (__builtin_popcount (riscv_zvl_flags) - 1)) 155 156 #endif /* ! GCC_RISCV_OPTS_H */ 157