| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyInstrInfo.cpp | 200 bool WebAssemblyInstrInfo::reverseBranchCondition( in reverseBranchCondition() function in WebAssemblyInstrInfo
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/ |
| H A D | MSP430InstrInfo.cpp | 132 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { in reverseBranchCondition() function in MSP430InstrInfo
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| H A D | SparcInstrInfo.cpp | 297 bool SparcInstrInfo::reverseBranchCondition( in reverseBranchCondition() function in SparcInstrInfo
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| H A D | AVRInstrInfo.cpp | 466 bool AVRInstrInfo::reverseBranchCondition( in reverseBranchCondition() function in llvm::AVRInstrInfo
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/XCore/ |
| H A D | XCoreInstrInfo.cpp | 403 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { in reverseBranchCondition() function in XCoreInstrInfo
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARC/ |
| H A D | ARCInstrInfo.cpp | 350 bool ARCInstrInfo::reverseBranchCondition( in reverseBranchCondition() function in ARCInstrInfo
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsInstrInfo.cpp | 183 bool MipsInstrInfo::reverseBranchCondition( in reverseBranchCondition() function in MipsInstrInfo
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.cpp | 646 bool LanaiInstrInfo::reverseBranchCondition( in reverseBranchCondition() function in LanaiInstrInfo
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
| H A D | VEInstrInfo.cpp | 314 bool VEInstrInfo::reverseBranchCondition( in reverseBranchCondition() function in VEInstrInfo
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.cpp | 674 bool RISCVInstrInfo::reverseBranchCondition( in reverseBranchCondition() function in RISCVInstrInfo
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| H A D | SystemZInstrInfo.cpp | 471 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { in reverseBranchCondition() function in SystemZInstrInfo
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | R600InstrInfo.cpp | 910 R600InstrInfo::reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { in reverseBranchCondition() function in R600InstrInfo
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| H A D | SIInstrInfo.cpp | 2478 bool SIInstrInfo::reverseBranchCondition( in reverseBranchCondition() function in SIInstrInfo
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | IfConversion.cpp | 624 bool IfConverter::reverseBranchCondition(BBInfo &BBI) const { in reverseBranchCondition() function in IfConverter
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | TargetInstrInfo.h | 1394 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { in reverseBranchCondition() function
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 1547 bool HexagonInstrInfo::reverseBranchCondition( in reverseBranchCondition() function in HexagonInstrInfo
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 410 bool AArch64InstrInfo::reverseBranchCondition( in reverseBranchCondition() function in AArch64InstrInfo
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 2027 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { in reverseBranchCondition() function in PPCInstrInfo
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 6808 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { in reverseBranchCondition() function in X86InstrInfo
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.cpp | 526 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { in reverseBranchCondition() function in ARMBaseInstrInfo
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