1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (C) 2015 Intel Corporation. 3 * All rights reserved. 4 */ 5 6 /** 7 * \file 8 * Intel NVMe vendor-specific definitions 9 * 10 * Reference: 11 * http://www.intel.com/content/dam/www/public/us/en/documents/product-specifications/ssd-dc-p3700-spec.pdf 12 */ 13 14 #ifndef SPDK_NVME_INTEL_H 15 #define SPDK_NVME_INTEL_H 16 17 #include "spdk/stdinc.h" 18 19 #ifdef __cplusplus 20 extern "C" { 21 #endif 22 23 #include "spdk/assert.h" 24 25 enum spdk_nvme_intel_feat { 26 SPDK_NVME_INTEL_FEAT_MAX_LBA = 0xC1, 27 SPDK_NVME_INTEL_FEAT_NATIVE_MAX_LBA = 0xC2, 28 SPDK_NVME_INTEL_FEAT_POWER_GOVERNOR_SETTING = 0xC6, 29 SPDK_NVME_INTEL_FEAT_SMBUS_ADDRESS = 0xC8, 30 SPDK_NVME_INTEL_FEAT_LED_PATTERN = 0xC9, 31 SPDK_NVME_INTEL_FEAT_RESET_TIMED_WORKLOAD_COUNTERS = 0xD5, 32 SPDK_NVME_INTEL_FEAT_LATENCY_TRACKING = 0xE2, 33 }; 34 35 enum spdk_nvme_intel_set_max_lba_command_status_code { 36 SPDK_NVME_INTEL_EXCEEDS_AVAILABLE_CAPACITY = 0xC0, 37 SPDK_NVME_INTEL_SMALLER_THAN_MIN_LIMIT = 0xC1, 38 SPDK_NVME_INTEL_SMALLER_THAN_NS_REQUIREMENTS = 0xC2, 39 }; 40 41 enum spdk_nvme_intel_log_page { 42 SPDK_NVME_INTEL_LOG_PAGE_DIRECTORY = 0xC0, 43 SPDK_NVME_INTEL_LOG_READ_CMD_LATENCY = 0xC1, 44 SPDK_NVME_INTEL_LOG_WRITE_CMD_LATENCY = 0xC2, 45 SPDK_NVME_INTEL_LOG_TEMPERATURE = 0xC5, 46 SPDK_NVME_INTEL_LOG_SMART = 0xCA, 47 SPDK_NVME_INTEL_MARKETING_DESCRIPTION = 0xDD, 48 }; 49 50 enum spdk_nvme_intel_smart_attribute_code { 51 SPDK_NVME_INTEL_SMART_PROGRAM_FAIL_COUNT = 0xAB, 52 SPDK_NVME_INTEL_SMART_ERASE_FAIL_COUNT = 0xAC, 53 SPDK_NVME_INTEL_SMART_WEAR_LEVELING_COUNT = 0xAD, 54 SPDK_NVME_INTEL_SMART_E2E_ERROR_COUNT = 0xB8, 55 SPDK_NVME_INTEL_SMART_CRC_ERROR_COUNT = 0xC7, 56 SPDK_NVME_INTEL_SMART_MEDIA_WEAR = 0xE2, 57 SPDK_NVME_INTEL_SMART_HOST_READ_PERCENTAGE = 0xE3, 58 SPDK_NVME_INTEL_SMART_TIMER = 0xE4, 59 SPDK_NVME_INTEL_SMART_THERMAL_THROTTLE_STATUS = 0xEA, 60 SPDK_NVME_INTEL_SMART_RETRY_BUFFER_OVERFLOW_COUNTER = 0xF0, 61 SPDK_NVME_INTEL_SMART_PLL_LOCK_LOSS_COUNT = 0xF3, 62 SPDK_NVME_INTEL_SMART_NAND_BYTES_WRITTEN = 0xF4, 63 SPDK_NVME_INTEL_SMART_HOST_BYTES_WRITTEN = 0xF5, 64 }; 65 66 struct spdk_nvme_intel_log_page_directory { 67 uint8_t version[2]; 68 uint8_t reserved[384]; 69 uint8_t read_latency_log_len; 70 uint8_t reserved2; 71 uint8_t write_latency_log_len; 72 uint8_t reserved3[5]; 73 uint8_t temperature_statistics_log_len; 74 uint8_t reserved4[9]; 75 uint8_t smart_log_len; 76 uint8_t reserved5[37]; 77 uint8_t marketing_description_log_len; 78 uint8_t reserved6[69]; 79 }; 80 SPDK_STATIC_ASSERT(sizeof(struct spdk_nvme_intel_log_page_directory) == 512, "Incorrect size"); 81 82 struct spdk_nvme_intel_rw_latency_page { 83 uint16_t major_revison; 84 uint16_t minor_revison; 85 uint32_t buckets_32us[32]; 86 uint32_t buckets_1ms[31]; 87 uint32_t buckets_32ms[31]; 88 }; 89 SPDK_STATIC_ASSERT(sizeof(struct spdk_nvme_intel_rw_latency_page) == 380, "Incorrect size"); 90 91 struct spdk_nvme_intel_temperature_page { 92 uint64_t current_temperature; 93 uint64_t shutdown_flag_last; 94 uint64_t shutdown_flag_life; 95 uint64_t highest_temperature; 96 uint64_t lowest_temperature; 97 uint64_t reserved[5]; 98 uint64_t specified_max_op_temperature; 99 uint64_t reserved2; 100 uint64_t specified_min_op_temperature; 101 uint64_t estimated_offset; 102 }; 103 SPDK_STATIC_ASSERT(sizeof(struct spdk_nvme_intel_temperature_page) == 112, "Incorrect size"); 104 105 struct spdk_nvme_intel_smart_attribute { 106 uint8_t code; 107 uint8_t reserved[2]; 108 uint8_t normalized_value; 109 uint8_t reserved2; 110 uint8_t raw_value[6]; 111 uint8_t reserved3; 112 }; 113 114 #pragma pack(push, 1) 115 struct spdk_nvme_intel_smart_information_page { 116 struct spdk_nvme_intel_smart_attribute attributes[13]; 117 }; 118 SPDK_STATIC_ASSERT(sizeof(struct spdk_nvme_intel_smart_information_page) == 156, "Incorrect size"); 119 #pragma pack(pop) 120 121 union spdk_nvme_intel_feat_power_governor { 122 uint32_t raw; 123 struct { 124 /** power governor setting : 00h = 25W 01h = 20W 02h = 10W */ 125 uint32_t power_governor_setting : 8; 126 uint32_t reserved : 24; 127 } bits; 128 }; 129 SPDK_STATIC_ASSERT(sizeof(union spdk_nvme_intel_feat_power_governor) == 4, "Incorrect size"); 130 131 union spdk_nvme_intel_feat_smbus_address { 132 uint32_t raw; 133 struct { 134 uint32_t reserved : 1; 135 uint32_t smbus_controller_address : 8; 136 uint32_t reserved2 : 23; 137 } bits; 138 }; 139 SPDK_STATIC_ASSERT(sizeof(union spdk_nvme_intel_feat_smbus_address) == 4, "Incorrect size"); 140 141 union spdk_nvme_intel_feat_led_pattern { 142 uint32_t raw; 143 struct { 144 uint32_t feature_options : 24; 145 uint32_t value : 8; 146 } bits; 147 }; 148 SPDK_STATIC_ASSERT(sizeof(union spdk_nvme_intel_feat_led_pattern) == 4, "Incorrect size"); 149 150 union spdk_nvme_intel_feat_reset_timed_workload_counters { 151 uint32_t raw; 152 struct { 153 /** 154 * Write Usage: 00 = NOP, 1 = Reset E2, E3,E4 counters; 155 * Read Usage: Not Supported 156 */ 157 uint32_t reset : 1; 158 uint32_t reserved : 31; 159 } bits; 160 }; 161 SPDK_STATIC_ASSERT(sizeof(union spdk_nvme_intel_feat_reset_timed_workload_counters) == 4, 162 "Incorrect size"); 163 164 union spdk_nvme_intel_feat_latency_tracking { 165 uint32_t raw; 166 struct { 167 /** 168 * Write Usage: 169 * 00h = Disable Latency Tracking (Default) 170 * 01h = Enable Latency Tracking 171 */ 172 uint32_t enable : 32; 173 } bits; 174 }; 175 SPDK_STATIC_ASSERT(sizeof(union spdk_nvme_intel_feat_latency_tracking) == 4, "Incorrect size"); 176 177 struct spdk_nvme_intel_marketing_description_page { 178 uint8_t marketing_product[512]; 179 /* Spec says this log page will only write 512 bytes, but there are some older FW 180 * versions that accidentally write 516 instead. So just pad this out to 4096 bytes 181 * to make sure users of this structure never end up overwriting unintended parts of 182 * memory. 183 */ 184 uint8_t reserved[3584]; 185 }; 186 SPDK_STATIC_ASSERT(sizeof(struct spdk_nvme_intel_marketing_description_page) == 4096, 187 "Incorrect size"); 188 #ifdef __cplusplus 189 } 190 #endif 191 192 #endif 193