1 /* Subroutines used for code generation on the Mitsubishi M32R cpu.
2 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
4
5 This file is part of GCC.
6
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
21
22 #include "config.h"
23 #include "system.h"
24 #include "tree.h"
25 #include "rtl.h"
26 #include "regs.h"
27 #include "hard-reg-set.h"
28 #include "real.h"
29 #include "insn-config.h"
30 #include "conditions.h"
31 #include "output.h"
32 #include "insn-attr.h"
33 #include "flags.h"
34 #include "expr.h"
35 #include "function.h"
36 #include "recog.h"
37 #include "toplev.h"
38 #include "ggc.h"
39 #include "tm_p.h"
40 #include "target.h"
41 #include "target-def.h"
42
43 /* Save the operands last given to a compare for use when we
44 generate a scc or bcc insn. */
45 rtx m32r_compare_op0, m32r_compare_op1;
46
47 /* Array of valid operand punctuation characters. */
48 char m32r_punct_chars[256];
49
50 /* Selected code model. */
51 const char * m32r_model_string = M32R_MODEL_DEFAULT;
52 enum m32r_model m32r_model;
53
54 /* Selected SDA support. */
55 const char * m32r_sdata_string = M32R_SDATA_DEFAULT;
56 enum m32r_sdata m32r_sdata;
57
58 /* Scheduler support */
59 static int m32r_sched_odd_word_p;
60
61 /* Forward declaration. */
62 static void init_reg_tables PARAMS ((void));
63 static void block_move_call PARAMS ((rtx, rtx, rtx));
64 static int m32r_is_insn PARAMS ((rtx));
65 const struct attribute_spec m32r_attribute_table[];
66 static tree m32r_handle_model_attribute PARAMS ((tree *, tree, tree, int, bool *));
67 static void m32r_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
68 static void m32r_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
69
70 static int m32r_adjust_cost PARAMS ((rtx, rtx, rtx, int));
71 static int m32r_adjust_priority PARAMS ((rtx, int));
72 static void m32r_sched_init PARAMS ((FILE *, int, int));
73 static int m32r_sched_reorder PARAMS ((FILE *, int, rtx *, int *, int));
74 static int m32r_variable_issue PARAMS ((FILE *, int, rtx, int));
75 static int m32r_issue_rate PARAMS ((void));
76
77 static void m32r_select_section PARAMS ((tree, int, unsigned HOST_WIDE_INT));
78 static void m32r_encode_section_info PARAMS ((tree, int));
79 static const char *m32r_strip_name_encoding PARAMS ((const char *));
80 static void init_idents PARAMS ((void));
81
82 /* Initialize the GCC target structure. */
83 #undef TARGET_ATTRIBUTE_TABLE
84 #define TARGET_ATTRIBUTE_TABLE m32r_attribute_table
85
86 #undef TARGET_ASM_ALIGNED_HI_OP
87 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
88 #undef TARGET_ASM_ALIGNED_SI_OP
89 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
90
91 #undef TARGET_ASM_FUNCTION_PROLOGUE
92 #define TARGET_ASM_FUNCTION_PROLOGUE m32r_output_function_prologue
93 #undef TARGET_ASM_FUNCTION_EPILOGUE
94 #define TARGET_ASM_FUNCTION_EPILOGUE m32r_output_function_epilogue
95
96 #undef TARGET_SCHED_ADJUST_COST
97 #define TARGET_SCHED_ADJUST_COST m32r_adjust_cost
98 #undef TARGET_SCHED_ADJUST_PRIORITY
99 #define TARGET_SCHED_ADJUST_PRIORITY m32r_adjust_priority
100 #undef TARGET_SCHED_ISSUE_RATE
101 #define TARGET_SCHED_ISSUE_RATE m32r_issue_rate
102 #undef TARGET_SCHED_VARIABLE_ISSUE
103 #define TARGET_SCHED_VARIABLE_ISSUE m32r_variable_issue
104 #undef TARGET_SCHED_INIT
105 #define TARGET_SCHED_INIT m32r_sched_init
106 #undef TARGET_SCHED_REORDER
107 #define TARGET_SCHED_REORDER m32r_sched_reorder
108
109 #undef TARGET_ENCODE_SECTION_INFO
110 #define TARGET_ENCODE_SECTION_INFO m32r_encode_section_info
111 #undef TARGET_STRIP_NAME_ENCODING
112 #define TARGET_STRIP_NAME_ENCODING m32r_strip_name_encoding
113
114 struct gcc_target targetm = TARGET_INITIALIZER;
115
116 /* Called by OVERRIDE_OPTIONS to initialize various things. */
117
118 void
m32r_init()119 m32r_init ()
120 {
121 init_reg_tables ();
122
123 /* Initialize array for PRINT_OPERAND_PUNCT_VALID_P. */
124 memset (m32r_punct_chars, 0, sizeof (m32r_punct_chars));
125 m32r_punct_chars['#'] = 1;
126 m32r_punct_chars['@'] = 1; /* ??? no longer used */
127
128 /* Provide default value if not specified. */
129 if (!g_switch_set)
130 g_switch_value = SDATA_DEFAULT_SIZE;
131
132 if (strcmp (m32r_model_string, "small") == 0)
133 m32r_model = M32R_MODEL_SMALL;
134 else if (strcmp (m32r_model_string, "medium") == 0)
135 m32r_model = M32R_MODEL_MEDIUM;
136 else if (strcmp (m32r_model_string, "large") == 0)
137 m32r_model = M32R_MODEL_LARGE;
138 else
139 error ("bad value (%s) for -mmodel switch", m32r_model_string);
140
141 if (strcmp (m32r_sdata_string, "none") == 0)
142 m32r_sdata = M32R_SDATA_NONE;
143 else if (strcmp (m32r_sdata_string, "sdata") == 0)
144 m32r_sdata = M32R_SDATA_SDATA;
145 else if (strcmp (m32r_sdata_string, "use") == 0)
146 m32r_sdata = M32R_SDATA_USE;
147 else
148 error ("bad value (%s) for -msdata switch", m32r_sdata_string);
149 }
150
151 /* Vectors to keep interesting information about registers where it can easily
152 be got. We use to use the actual mode value as the bit number, but there
153 is (or may be) more than 32 modes now. Instead we use two tables: one
154 indexed by hard register number, and one indexed by mode. */
155
156 /* The purpose of m32r_mode_class is to shrink the range of modes so that
157 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
158 mapped into one m32r_mode_class mode. */
159
160 enum m32r_mode_class
161 {
162 C_MODE,
163 S_MODE, D_MODE, T_MODE, O_MODE,
164 SF_MODE, DF_MODE, TF_MODE, OF_MODE, A_MODE
165 };
166
167 /* Modes for condition codes. */
168 #define C_MODES (1 << (int) C_MODE)
169
170 /* Modes for single-word and smaller quantities. */
171 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
172
173 /* Modes for double-word and smaller quantities. */
174 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
175
176 /* Modes for quad-word and smaller quantities. */
177 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
178
179 /* Modes for accumulators. */
180 #define A_MODES (1 << (int) A_MODE)
181
182 /* Value is 1 if register/mode pair is acceptable on arc. */
183
184 const unsigned int m32r_hard_regno_mode_ok[FIRST_PSEUDO_REGISTER] =
185 {
186 T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES,
187 T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, S_MODES, S_MODES, S_MODES,
188 S_MODES, C_MODES, A_MODES, A_MODES
189 };
190
191 unsigned int m32r_mode_class [NUM_MACHINE_MODES];
192
193 enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER];
194
195 static void
init_reg_tables()196 init_reg_tables ()
197 {
198 int i;
199
200 for (i = 0; i < NUM_MACHINE_MODES; i++)
201 {
202 switch (GET_MODE_CLASS (i))
203 {
204 case MODE_INT:
205 case MODE_PARTIAL_INT:
206 case MODE_COMPLEX_INT:
207 if (GET_MODE_SIZE (i) <= 4)
208 m32r_mode_class[i] = 1 << (int) S_MODE;
209 else if (GET_MODE_SIZE (i) == 8)
210 m32r_mode_class[i] = 1 << (int) D_MODE;
211 else if (GET_MODE_SIZE (i) == 16)
212 m32r_mode_class[i] = 1 << (int) T_MODE;
213 else if (GET_MODE_SIZE (i) == 32)
214 m32r_mode_class[i] = 1 << (int) O_MODE;
215 else
216 m32r_mode_class[i] = 0;
217 break;
218 case MODE_FLOAT:
219 case MODE_COMPLEX_FLOAT:
220 if (GET_MODE_SIZE (i) <= 4)
221 m32r_mode_class[i] = 1 << (int) SF_MODE;
222 else if (GET_MODE_SIZE (i) == 8)
223 m32r_mode_class[i] = 1 << (int) DF_MODE;
224 else if (GET_MODE_SIZE (i) == 16)
225 m32r_mode_class[i] = 1 << (int) TF_MODE;
226 else if (GET_MODE_SIZE (i) == 32)
227 m32r_mode_class[i] = 1 << (int) OF_MODE;
228 else
229 m32r_mode_class[i] = 0;
230 break;
231 case MODE_CC:
232 default:
233 /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
234 we must explicitly check for them here. */
235 if (i == (int) CCmode)
236 m32r_mode_class[i] = 1 << (int) C_MODE;
237 else
238 m32r_mode_class[i] = 0;
239 break;
240 }
241 }
242
243 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
244 {
245 if (GPR_P (i))
246 m32r_regno_reg_class[i] = GENERAL_REGS;
247 else if (i == ARG_POINTER_REGNUM)
248 m32r_regno_reg_class[i] = GENERAL_REGS;
249 else
250 m32r_regno_reg_class[i] = NO_REGS;
251 }
252 }
253
254 /* M32R specific attribute support.
255
256 interrupt - for interrupt functions
257
258 model - select code model used to access object
259
260 small: addresses use 24 bits, use bl to make calls
261 medium: addresses use 32 bits, use bl to make calls
262 large: addresses use 32 bits, use seth/add3/jl to make calls
263
264 Grep for MODEL in m32r.h for more info.
265 */
266
267 static tree small_ident1;
268 static tree small_ident2;
269 static tree medium_ident1;
270 static tree medium_ident2;
271 static tree large_ident1;
272 static tree large_ident2;
273
274 static void
init_idents()275 init_idents ()
276 {
277 if (small_ident1 == 0)
278 {
279 small_ident1 = get_identifier ("small");
280 small_ident2 = get_identifier ("__small__");
281 medium_ident1 = get_identifier ("medium");
282 medium_ident2 = get_identifier ("__medium__");
283 large_ident1 = get_identifier ("large");
284 large_ident2 = get_identifier ("__large__");
285 }
286 }
287
288 const struct attribute_spec m32r_attribute_table[] =
289 {
290 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
291 { "interrupt", 0, 0, true, false, false, NULL },
292 { "model", 1, 1, true, false, false, m32r_handle_model_attribute },
293 { NULL, 0, 0, false, false, false, NULL }
294 };
295
296
297 /* Handle an "model" attribute; arguments as in
298 struct attribute_spec.handler. */
299 static tree
m32r_handle_model_attribute(node,name,args,flags,no_add_attrs)300 m32r_handle_model_attribute (node, name, args, flags, no_add_attrs)
301 tree *node ATTRIBUTE_UNUSED;
302 tree name;
303 tree args;
304 int flags ATTRIBUTE_UNUSED;
305 bool *no_add_attrs;
306 {
307 tree arg;
308
309 init_idents ();
310 arg = TREE_VALUE (args);
311
312 if (arg != small_ident1
313 && arg != small_ident2
314 && arg != medium_ident1
315 && arg != medium_ident2
316 && arg != large_ident1
317 && arg != large_ident2)
318 {
319 warning ("invalid argument of `%s' attribute",
320 IDENTIFIER_POINTER (name));
321 *no_add_attrs = true;
322 }
323
324 return NULL_TREE;
325 }
326
327 /* A C statement or statements to switch to the appropriate
328 section for output of DECL. DECL is either a `VAR_DECL' node
329 or a constant of some sort. RELOC indicates whether forming
330 the initial value of DECL requires link-time relocations. */
331
332 static void
m32r_select_section(decl,reloc,align)333 m32r_select_section (decl, reloc, align)
334 tree decl;
335 int reloc;
336 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED;
337 {
338 if (TREE_CODE (decl) == STRING_CST)
339 {
340 if (! flag_writable_strings)
341 readonly_data_section ();
342 else
343 data_section ();
344 }
345 else if (TREE_CODE (decl) == VAR_DECL)
346 {
347 if (SDATA_NAME_P (XSTR (XEXP (DECL_RTL (decl), 0), 0)))
348 sdata_section ();
349 else if ((flag_pic && reloc)
350 || !TREE_READONLY (decl)
351 || TREE_SIDE_EFFECTS (decl)
352 || !DECL_INITIAL (decl)
353 || (DECL_INITIAL (decl) != error_mark_node
354 && !TREE_CONSTANT (DECL_INITIAL (decl))))
355 data_section ();
356 else
357 readonly_data_section ();
358 }
359 else
360 readonly_data_section ();
361 }
362
363 /* Encode section information of DECL, which is either a VAR_DECL,
364 FUNCTION_DECL, STRING_CST, CONSTRUCTOR, or ???.
365
366 For the M32R we want to record:
367
368 - whether the object lives in .sdata/.sbss.
369 objects living in .sdata/.sbss are prefixed with SDATA_FLAG_CHAR
370
371 - what code model should be used to access the object
372 small: recorded with no flag - for space efficiency since they'll
373 be the most common
374 medium: prefixed with MEDIUM_FLAG_CHAR
375 large: prefixed with LARGE_FLAG_CHAR
376 */
377
378 static void
m32r_encode_section_info(decl,first)379 m32r_encode_section_info (decl, first)
380 tree decl;
381 int first;
382 {
383 char prefix = 0;
384 tree model = 0;
385
386 if (!first)
387 return;
388
389 switch (TREE_CODE (decl))
390 {
391 case VAR_DECL :
392 case FUNCTION_DECL :
393 model = lookup_attribute ("model", DECL_ATTRIBUTES (decl));
394 break;
395 case STRING_CST :
396 case CONSTRUCTOR :
397 /* ??? document all others that can appear here */
398 default :
399 return;
400 }
401
402 /* Only mark the object as being small data area addressable if
403 it hasn't been explicitly marked with a code model.
404
405 The user can explicitly put an object in the small data area with the
406 section attribute. If the object is in sdata/sbss and marked with a
407 code model do both [put the object in .sdata and mark it as being
408 addressed with a specific code model - don't mark it as being addressed
409 with an SDA reloc though]. This is ok and might be useful at times. If
410 the object doesn't fit the linker will give an error. */
411
412 if (! model)
413 {
414 if (TREE_CODE_CLASS (TREE_CODE (decl)) == 'd'
415 && DECL_SECTION_NAME (decl) != NULL_TREE)
416 {
417 char *name = (char *) TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
418 if (! strcmp (name, ".sdata") || ! strcmp (name, ".sbss"))
419 {
420 #if 0 /* ??? There's no reason to disallow this, is there? */
421 if (TREE_READONLY (decl))
422 error_with_decl (decl, "const objects cannot go in .sdata/.sbss");
423 #endif
424 prefix = SDATA_FLAG_CHAR;
425 }
426 }
427 else
428 {
429 if (TREE_CODE (decl) == VAR_DECL
430 && ! TREE_READONLY (decl)
431 && ! TARGET_SDATA_NONE)
432 {
433 int size = int_size_in_bytes (TREE_TYPE (decl));
434
435 if (size > 0 && size <= g_switch_value)
436 prefix = SDATA_FLAG_CHAR;
437 }
438 }
439 }
440
441 /* If data area not decided yet, check for a code model. */
442 if (prefix == 0)
443 {
444 if (model)
445 {
446 tree id;
447
448 init_idents ();
449
450 id = TREE_VALUE (TREE_VALUE (model));
451
452 if (id == small_ident1 || id == small_ident2)
453 ; /* don't mark the symbol specially */
454 else if (id == medium_ident1 || id == medium_ident2)
455 prefix = MEDIUM_FLAG_CHAR;
456 else if (id == large_ident1 || id == large_ident2)
457 prefix = LARGE_FLAG_CHAR;
458 else
459 abort (); /* shouldn't happen */
460 }
461 else
462 {
463 if (TARGET_MODEL_SMALL)
464 ; /* don't mark the symbol specially */
465 else if (TARGET_MODEL_MEDIUM)
466 prefix = MEDIUM_FLAG_CHAR;
467 else if (TARGET_MODEL_LARGE)
468 prefix = LARGE_FLAG_CHAR;
469 else
470 abort (); /* shouldn't happen */
471 }
472 }
473
474 if (prefix != 0)
475 {
476 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (decl)) != 'd'
477 ? TREE_CST_RTL (decl) : DECL_RTL (decl));
478 const char *str = XSTR (XEXP (rtl, 0), 0);
479 int len = strlen (str);
480 char *newstr = ggc_alloc (len + 2);
481
482 strcpy (newstr + 1, str);
483 *newstr = prefix;
484 /* Note - we cannot leave the string in the ggc_alloc'ed space.
485 It must reside in the stringtable's domain. */
486 newstr = (char *) ggc_alloc_string (newstr, len + 2);
487
488 XSTR (XEXP (rtl, 0), 0) = newstr;
489 }
490 }
491
492 /* Undo the effects of the above. */
493
494 static const char *
m32r_strip_name_encoding(str)495 m32r_strip_name_encoding (str)
496 const char *str;
497 {
498 str += ENCODED_NAME_P (str);
499 str += *str == '*';
500 return str;
501 }
502
503 /* Do anything needed before RTL is emitted for each function. */
504
505 void
m32r_init_expanders()506 m32r_init_expanders ()
507 {
508 /* ??? At one point there was code here. The function is left in
509 to make it easy to experiment. */
510 }
511
512 /* Acceptable arguments to the call insn. */
513
514 int
call_address_operand(op,mode)515 call_address_operand (op, mode)
516 rtx op;
517 enum machine_mode mode;
518 {
519 return symbolic_operand (op, mode);
520
521 /* Constants and values in registers are not OK, because
522 the m32r BL instruction can only support PC relative branching. */
523 }
524
525 int
call_operand(op,mode)526 call_operand (op, mode)
527 rtx op;
528 enum machine_mode mode;
529 {
530 if (GET_CODE (op) != MEM)
531 return 0;
532 op = XEXP (op, 0);
533 return call_address_operand (op, mode);
534 }
535
536 /* Returns 1 if OP is a symbol reference. */
537
538 int
symbolic_operand(op,mode)539 symbolic_operand (op, mode)
540 rtx op;
541 enum machine_mode mode ATTRIBUTE_UNUSED;
542 {
543 switch (GET_CODE (op))
544 {
545 case SYMBOL_REF:
546 case LABEL_REF:
547 case CONST :
548 return 1;
549
550 default:
551 return 0;
552 }
553 }
554
555 /* Return 1 if OP is a reference to an object in .sdata/.sbss. */
556
557 int
small_data_operand(op,mode)558 small_data_operand (op, mode)
559 rtx op;
560 enum machine_mode mode ATTRIBUTE_UNUSED;
561 {
562 if (! TARGET_SDATA_USE)
563 return 0;
564
565 if (GET_CODE (op) == SYMBOL_REF)
566 return SDATA_NAME_P (XSTR (op, 0));
567
568 if (GET_CODE (op) == CONST
569 && GET_CODE (XEXP (op, 0)) == PLUS
570 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
571 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
572 && INT16_P (INTVAL (XEXP (XEXP (op, 0), 1))))
573 return SDATA_NAME_P (XSTR (XEXP (XEXP (op, 0), 0), 0));
574
575 return 0;
576 }
577
578 /* Return 1 if OP is a symbol that can use 24 bit addressing. */
579
580 int
addr24_operand(op,mode)581 addr24_operand (op, mode)
582 rtx op;
583 enum machine_mode mode ATTRIBUTE_UNUSED;
584 {
585 if (GET_CODE (op) == LABEL_REF)
586 return TARGET_ADDR24;
587
588 if (GET_CODE (op) == SYMBOL_REF)
589 return (SMALL_NAME_P (XSTR (op, 0))
590 || (TARGET_ADDR24
591 && (CONSTANT_POOL_ADDRESS_P (op)
592 || LIT_NAME_P (XSTR (op, 0)))));
593
594 if (GET_CODE (op) == CONST
595 && GET_CODE (XEXP (op, 0)) == PLUS
596 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
597 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
598 && UINT24_P (INTVAL (XEXP (XEXP (op, 0), 1))))
599 {
600 rtx sym = XEXP (XEXP (op, 0), 0);
601 return (SMALL_NAME_P (XSTR (sym, 0))
602 || (TARGET_ADDR24
603 && (CONSTANT_POOL_ADDRESS_P (op)
604 || LIT_NAME_P (XSTR (op, 0)))));
605 }
606
607 return 0;
608 }
609
610 /* Return 1 if OP is a symbol that needs 32 bit addressing. */
611
612 int
addr32_operand(op,mode)613 addr32_operand (op, mode)
614 rtx op;
615 enum machine_mode mode;
616 {
617 if (GET_CODE (op) == LABEL_REF)
618 return TARGET_ADDR32;
619
620 if (GET_CODE (op) == SYMBOL_REF)
621 return (! addr24_operand (op, mode)
622 && ! small_data_operand (op, mode));
623
624 if (GET_CODE (op) == CONST
625 && GET_CODE (XEXP (op, 0)) == PLUS
626 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
627 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
628 {
629 return (! addr24_operand (op, mode)
630 && ! small_data_operand (op, mode));
631 }
632
633 return 0;
634 }
635
636 /* Return 1 if OP is a function that can be called with the `bl' insn. */
637
638 int
call26_operand(op,mode)639 call26_operand (op, mode)
640 rtx op;
641 enum machine_mode mode ATTRIBUTE_UNUSED;
642 {
643 if (GET_CODE (op) == SYMBOL_REF)
644 return ! LARGE_NAME_P (XSTR (op, 0));
645
646 return TARGET_CALL26;
647 }
648
649 /* Returns 1 if OP is an acceptable operand for seth/add3. */
650
651 int
seth_add3_operand(op,mode)652 seth_add3_operand (op, mode)
653 rtx op;
654 enum machine_mode mode ATTRIBUTE_UNUSED;
655 {
656 if (GET_CODE (op) == SYMBOL_REF
657 || GET_CODE (op) == LABEL_REF)
658 return 1;
659
660 if (GET_CODE (op) == CONST
661 && GET_CODE (XEXP (op, 0)) == PLUS
662 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
663 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
664 && INT16_P (INTVAL (XEXP (XEXP (op, 0), 1))))
665 return 1;
666
667 return 0;
668 }
669
670 /* Return true if OP is a signed 8 bit immediate value. */
671
672 int
int8_operand(op,mode)673 int8_operand (op, mode)
674 rtx op;
675 enum machine_mode mode ATTRIBUTE_UNUSED;
676 {
677 if (GET_CODE (op) != CONST_INT)
678 return 0;
679 return INT8_P (INTVAL (op));
680 }
681
682 /* Return true if OP is a signed 16 bit immediate value
683 useful in comparisons. */
684
685 int
cmp_int16_operand(op,mode)686 cmp_int16_operand (op, mode)
687 rtx op;
688 enum machine_mode mode ATTRIBUTE_UNUSED;
689 {
690 if (GET_CODE (op) != CONST_INT)
691 return 0;
692 return CMP_INT16_P (INTVAL (op));
693 }
694
695 /* Return true if OP is an unsigned 16 bit immediate value. */
696
697 int
uint16_operand(op,mode)698 uint16_operand (op, mode)
699 rtx op;
700 enum machine_mode mode ATTRIBUTE_UNUSED;
701 {
702 if (GET_CODE (op) != CONST_INT)
703 return 0;
704 return UINT16_P (INTVAL (op));
705 }
706
707 /* Return true if OP is a register or signed 16 bit value. */
708
709 int
reg_or_int16_operand(op,mode)710 reg_or_int16_operand (op, mode)
711 rtx op;
712 enum machine_mode mode;
713 {
714 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
715 return register_operand (op, mode);
716 if (GET_CODE (op) != CONST_INT)
717 return 0;
718 return INT16_P (INTVAL (op));
719 }
720
721 /* Return true if OP is a register or an unsigned 16 bit value. */
722
723 int
reg_or_uint16_operand(op,mode)724 reg_or_uint16_operand (op, mode)
725 rtx op;
726 enum machine_mode mode;
727 {
728 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
729 return register_operand (op, mode);
730 if (GET_CODE (op) != CONST_INT)
731 return 0;
732 return UINT16_P (INTVAL (op));
733 }
734
735 /* Return true if OP is a register or an integer value that can be
736 used is SEQ/SNE. We can use either XOR of the value or ADD of
737 the negative of the value for the constant. Don't allow 0,
738 because that is special cased. */
739
740 int
reg_or_eq_int16_operand(op,mode)741 reg_or_eq_int16_operand (op, mode)
742 rtx op;
743 enum machine_mode mode;
744 {
745 HOST_WIDE_INT value;
746
747 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
748 return register_operand (op, mode);
749
750 if (GET_CODE (op) != CONST_INT)
751 return 0;
752
753 value = INTVAL (op);
754 return (value != 0) && (UINT16_P (value) || CMP_INT16_P (-value));
755 }
756
757 /* Return true if OP is a register or signed 16 bit value for compares. */
758
759 int
reg_or_cmp_int16_operand(op,mode)760 reg_or_cmp_int16_operand (op, mode)
761 rtx op;
762 enum machine_mode mode;
763 {
764 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
765 return register_operand (op, mode);
766 if (GET_CODE (op) != CONST_INT)
767 return 0;
768 return CMP_INT16_P (INTVAL (op));
769 }
770
771 /* Return true if OP is a register or the constant 0. */
772
773 int
reg_or_zero_operand(op,mode)774 reg_or_zero_operand (op, mode)
775 rtx op;
776 enum machine_mode mode;
777 {
778 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
779 return register_operand (op, mode);
780
781 if (GET_CODE (op) != CONST_INT)
782 return 0;
783
784 return INTVAL (op) == 0;
785 }
786
787 /* Return true if OP is a const_int requiring two instructions to load. */
788
789 int
two_insn_const_operand(op,mode)790 two_insn_const_operand (op, mode)
791 rtx op;
792 enum machine_mode mode ATTRIBUTE_UNUSED;
793 {
794 if (GET_CODE (op) != CONST_INT)
795 return 0;
796 if (INT16_P (INTVAL (op))
797 || UINT24_P (INTVAL (op))
798 || UPPER16_P (INTVAL (op)))
799 return 0;
800 return 1;
801 }
802
803 /* Return true if OP is an acceptable argument for a single word
804 move source. */
805
806 int
move_src_operand(op,mode)807 move_src_operand (op, mode)
808 rtx op;
809 enum machine_mode mode;
810 {
811 switch (GET_CODE (op))
812 {
813 case SYMBOL_REF :
814 case CONST :
815 return addr24_operand (op, mode);
816 case CONST_INT :
817 /* ??? We allow more cse opportunities if we only allow constants
818 loadable with one insn, and split the rest into two. The instances
819 where this would help should be rare and the current way is
820 simpler. */
821 if (HOST_BITS_PER_WIDE_INT > 32)
822 {
823 HOST_WIDE_INT rest = INTVAL (op) >> 31;
824 return (rest == 0 || rest == -1);
825 }
826 else
827 return 1;
828 case LABEL_REF :
829 return TARGET_ADDR24;
830 case CONST_DOUBLE :
831 if (mode == SFmode)
832 return 1;
833 else if (mode == SImode)
834 {
835 /* Large unsigned constants are represented as const_double's. */
836 unsigned HOST_WIDE_INT low, high;
837
838 low = CONST_DOUBLE_LOW (op);
839 high = CONST_DOUBLE_HIGH (op);
840 return high == 0 && low <= 0xffffffff;
841 }
842 else
843 return 0;
844 case REG :
845 return register_operand (op, mode);
846 case SUBREG :
847 /* (subreg (mem ...) ...) can occur here if the inner part was once a
848 pseudo-reg and is now a stack slot. */
849 if (GET_CODE (SUBREG_REG (op)) == MEM)
850 return address_operand (XEXP (SUBREG_REG (op), 0), mode);
851 else
852 return register_operand (op, mode);
853 case MEM :
854 if (GET_CODE (XEXP (op, 0)) == PRE_INC
855 || GET_CODE (XEXP (op, 0)) == PRE_DEC)
856 return 0; /* loads can't do pre-{inc,dec} */
857 return address_operand (XEXP (op, 0), mode);
858 default :
859 return 0;
860 }
861 }
862
863 /* Return true if OP is an acceptable argument for a double word
864 move source. */
865
866 int
move_double_src_operand(op,mode)867 move_double_src_operand (op, mode)
868 rtx op;
869 enum machine_mode mode;
870 {
871 switch (GET_CODE (op))
872 {
873 case CONST_INT :
874 case CONST_DOUBLE :
875 return 1;
876 case REG :
877 return register_operand (op, mode);
878 case SUBREG :
879 /* (subreg (mem ...) ...) can occur here if the inner part was once a
880 pseudo-reg and is now a stack slot. */
881 if (GET_CODE (SUBREG_REG (op)) == MEM)
882 return move_double_src_operand (SUBREG_REG (op), mode);
883 else
884 return register_operand (op, mode);
885 case MEM :
886 /* Disallow auto inc/dec for now. */
887 if (GET_CODE (XEXP (op, 0)) == PRE_DEC
888 || GET_CODE (XEXP (op, 0)) == PRE_INC)
889 return 0;
890 return address_operand (XEXP (op, 0), mode);
891 default :
892 return 0;
893 }
894 }
895
896 /* Return true if OP is an acceptable argument for a move destination. */
897
898 int
move_dest_operand(op,mode)899 move_dest_operand (op, mode)
900 rtx op;
901 enum machine_mode mode;
902 {
903 switch (GET_CODE (op))
904 {
905 case REG :
906 return register_operand (op, mode);
907 case SUBREG :
908 /* (subreg (mem ...) ...) can occur here if the inner part was once a
909 pseudo-reg and is now a stack slot. */
910 if (GET_CODE (SUBREG_REG (op)) == MEM)
911 return address_operand (XEXP (SUBREG_REG (op), 0), mode);
912 else
913 return register_operand (op, mode);
914 case MEM :
915 if (GET_CODE (XEXP (op, 0)) == POST_INC)
916 return 0; /* stores can't do post inc */
917 return address_operand (XEXP (op, 0), mode);
918 default :
919 return 0;
920 }
921 }
922
923 /* Return 1 if OP is a DImode const we want to handle inline.
924 This must match the code in the movdi pattern.
925 It is used by the 'G' CONST_DOUBLE_OK_FOR_LETTER. */
926
927 int
easy_di_const(op)928 easy_di_const (op)
929 rtx op;
930 {
931 rtx high_rtx, low_rtx;
932 HOST_WIDE_INT high, low;
933
934 split_double (op, &high_rtx, &low_rtx);
935 high = INTVAL (high_rtx);
936 low = INTVAL (low_rtx);
937 /* Pick constants loadable with 2 16 bit `ldi' insns. */
938 if (high >= -128 && high <= 127
939 && low >= -128 && low <= 127)
940 return 1;
941 return 0;
942 }
943
944 /* Return 1 if OP is a DFmode const we want to handle inline.
945 This must match the code in the movdf pattern.
946 It is used by the 'H' CONST_DOUBLE_OK_FOR_LETTER. */
947
948 int
easy_df_const(op)949 easy_df_const (op)
950 rtx op;
951 {
952 REAL_VALUE_TYPE r;
953 long l[2];
954
955 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
956 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
957 if (l[0] == 0 && l[1] == 0)
958 return 1;
959 if ((l[0] & 0xffff) == 0 && l[1] == 0)
960 return 1;
961 return 0;
962 }
963
964 /* Return 1 if OP is an EQ or NE comparison operator. */
965
966 int
eqne_comparison_operator(op,mode)967 eqne_comparison_operator (op, mode)
968 rtx op;
969 enum machine_mode mode ATTRIBUTE_UNUSED;
970 {
971 enum rtx_code code = GET_CODE (op);
972
973 if (GET_RTX_CLASS (code) != '<')
974 return 0;
975 return (code == EQ || code == NE);
976 }
977
978 /* Return 1 if OP is a signed comparison operator. */
979
980 int
signed_comparison_operator(op,mode)981 signed_comparison_operator (op, mode)
982 rtx op;
983 enum machine_mode mode ATTRIBUTE_UNUSED;
984 {
985 enum rtx_code code = GET_CODE (op);
986
987 if (GET_RTX_CLASS (code) != '<')
988 return 0;
989 return (code == EQ || code == NE
990 || code == LT || code == LE || code == GT || code == GE);
991 }
992
993 /* Return 1 if OP is (mem (reg ...)).
994 This is used in insn length calcs. */
995
996 int
memreg_operand(op,mode)997 memreg_operand (op, mode)
998 rtx op;
999 enum machine_mode mode ATTRIBUTE_UNUSED;
1000 {
1001 return GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == REG;
1002 }
1003
1004 /* Return true if OP is an acceptable input argument for a zero/sign extend
1005 operation. */
1006
1007 int
extend_operand(op,mode)1008 extend_operand (op, mode)
1009 rtx op;
1010 enum machine_mode mode;
1011 {
1012 rtx addr;
1013
1014 switch (GET_CODE (op))
1015 {
1016 case REG :
1017 case SUBREG :
1018 return register_operand (op, mode);
1019
1020 case MEM :
1021 addr = XEXP (op, 0);
1022 if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
1023 return 0; /* loads can't do pre inc/pre dec */
1024
1025 return address_operand (addr, mode);
1026
1027 default :
1028 return 0;
1029 }
1030 }
1031
1032 /* Return nonzero if the operand is an insn that is a small insn.
1033 Allow const_int 0 as well, which is a placeholder for NOP slots. */
1034
1035 int
small_insn_p(op,mode)1036 small_insn_p (op, mode)
1037 rtx op;
1038 enum machine_mode mode ATTRIBUTE_UNUSED;
1039 {
1040 if (GET_CODE (op) == CONST_INT && INTVAL (op) == 0)
1041 return 1;
1042
1043 if (! INSN_P (op))
1044 return 0;
1045
1046 return get_attr_length (op) == 2;
1047 }
1048
1049 /* Return nonzero if the operand is an insn that is a large insn. */
1050
1051 int
large_insn_p(op,mode)1052 large_insn_p (op, mode)
1053 rtx op;
1054 enum machine_mode mode ATTRIBUTE_UNUSED;
1055 {
1056 if (! INSN_P (op))
1057 return 0;
1058
1059 return get_attr_length (op) != 2;
1060 }
1061
1062
1063 /* Comparisons. */
1064
1065 /* X and Y are two things to compare using CODE. Emit the compare insn and
1066 return the rtx for compare [arg0 of the if_then_else].
1067 If need_compare is true then the comparison insn must be generated, rather
1068 than being susummed into the following branch instruction. */
1069
1070 rtx
gen_compare(code,x,y,need_compare)1071 gen_compare (code, x, y, need_compare)
1072 enum rtx_code code;
1073 rtx x, y;
1074 int need_compare;
1075 {
1076 enum rtx_code compare_code, branch_code;
1077 rtx cc_reg = gen_rtx_REG (CCmode, CARRY_REGNUM);
1078 int must_swap = 0;
1079
1080 switch (code)
1081 {
1082 case EQ: compare_code = EQ; branch_code = NE; break;
1083 case NE: compare_code = EQ; branch_code = EQ; break;
1084 case LT: compare_code = LT; branch_code = NE; break;
1085 case LE: compare_code = LT; branch_code = EQ; must_swap = 1; break;
1086 case GT: compare_code = LT; branch_code = NE; must_swap = 1; break;
1087 case GE: compare_code = LT; branch_code = EQ; break;
1088 case LTU: compare_code = LTU; branch_code = NE; break;
1089 case LEU: compare_code = LTU; branch_code = EQ; must_swap = 1; break;
1090 case GTU: compare_code = LTU; branch_code = NE; must_swap = 1; break;
1091 case GEU: compare_code = LTU; branch_code = EQ; break;
1092
1093 default:
1094 abort ();
1095 }
1096
1097 if (need_compare)
1098 {
1099 switch (compare_code)
1100 {
1101 case EQ:
1102 if (GET_CODE (y) == CONST_INT
1103 && CMP_INT16_P (INTVAL (y)) /* reg equal to small const. */
1104 && y != const0_rtx)
1105 {
1106 rtx tmp = gen_reg_rtx (SImode);
1107
1108 emit_insn (gen_cmp_ne_small_const_insn (tmp, x, y));
1109 x = tmp;
1110 y = const0_rtx;
1111 }
1112 else if (CONSTANT_P (y)) /* reg equal to const. */
1113 {
1114 rtx tmp = force_reg (GET_MODE (x), y);
1115 y = tmp;
1116 }
1117
1118 if (register_operand (y, SImode) /* reg equal to reg. */
1119 || y == const0_rtx) /* req equal to zero. */
1120 {
1121 emit_insn (gen_cmp_eqsi_insn (x, y));
1122
1123 return gen_rtx (code, CCmode, cc_reg, const0_rtx);
1124 }
1125 break;
1126
1127 case LT:
1128 if (register_operand (y, SImode)
1129 || (GET_CODE (y) == CONST_INT && CMP_INT16_P (INTVAL (y))))
1130 {
1131 rtx tmp = gen_reg_rtx (SImode); /* reg compared to reg. */
1132
1133 switch (code)
1134 {
1135 case LT:
1136 emit_insn (gen_cmp_ltsi_insn (x, y));
1137 code = EQ;
1138 break;
1139 case LE:
1140 if (y == const0_rtx)
1141 tmp = const1_rtx;
1142 else
1143 emit_insn (gen_cmp_ne_small_const_insn (tmp, y, const1_rtx));
1144 emit_insn (gen_cmp_ltsi_insn (x, tmp));
1145 code = EQ;
1146 break;
1147 case GT:
1148 if (GET_CODE (y) == CONST_INT)
1149 tmp = gen_rtx (PLUS, SImode, y, const1_rtx);
1150 else
1151 emit_insn (gen_cmp_ne_small_const_insn (tmp, y, const1_rtx));
1152 emit_insn (gen_cmp_ltsi_insn (x, tmp));
1153 code = NE;
1154 break;
1155 case GE:
1156 emit_insn (gen_cmp_ltsi_insn (x, y));
1157 code = NE;
1158 break;
1159 default:
1160 abort ();
1161 }
1162
1163 return gen_rtx (code, CCmode, cc_reg, const0_rtx);
1164 }
1165 break;
1166
1167 case LTU:
1168 if (register_operand (y, SImode)
1169 || (GET_CODE (y) == CONST_INT && CMP_INT16_P (INTVAL (y))))
1170 {
1171 rtx tmp = gen_reg_rtx (SImode); /* reg (unsigned) compared to reg. */
1172
1173 switch (code)
1174 {
1175 case LTU:
1176 emit_insn (gen_cmp_ltusi_insn (x, y));
1177 code = EQ;
1178 break;
1179 case LEU:
1180 if (y == const0_rtx)
1181 tmp = const1_rtx;
1182 else
1183 emit_insn (gen_cmp_ne_small_const_insn (tmp, y, const1_rtx));
1184 emit_insn (gen_cmp_ltusi_insn (x, tmp));
1185 code = EQ;
1186 break;
1187 case GTU:
1188 if (GET_CODE (y) == CONST_INT)
1189 tmp = gen_rtx (PLUS, SImode, y, const1_rtx);
1190 else
1191 emit_insn (gen_cmp_ne_small_const_insn (tmp, y, const1_rtx));
1192 emit_insn (gen_cmp_ltusi_insn (x, tmp));
1193 code = NE;
1194 break;
1195 case GEU:
1196 emit_insn (gen_cmp_ltusi_insn (x, y));
1197 code = NE;
1198 break;
1199 default:
1200 abort();
1201 }
1202
1203 return gen_rtx (code, CCmode, cc_reg, const0_rtx);
1204 }
1205 break;
1206
1207 default:
1208 abort();
1209 }
1210 }
1211 else
1212 {
1213 /* reg/reg equal comparison */
1214 if (compare_code == EQ
1215 && register_operand (y, SImode))
1216 return gen_rtx (code, CCmode, x, y);
1217
1218 /* reg/zero signed comparison */
1219 if ((compare_code == EQ || compare_code == LT)
1220 && y == const0_rtx)
1221 return gen_rtx (code, CCmode, x, y);
1222
1223 /* reg/smallconst equal comparison */
1224 if (compare_code == EQ
1225 && GET_CODE (y) == CONST_INT
1226 && CMP_INT16_P (INTVAL (y)))
1227 {
1228 rtx tmp = gen_reg_rtx (SImode);
1229 emit_insn (gen_cmp_ne_small_const_insn (tmp, x, y));
1230 return gen_rtx (code, CCmode, tmp, const0_rtx);
1231 }
1232
1233 /* reg/const equal comparison */
1234 if (compare_code == EQ
1235 && CONSTANT_P (y))
1236 {
1237 rtx tmp = force_reg (GET_MODE (x), y);
1238 return gen_rtx (code, CCmode, x, tmp);
1239 }
1240 }
1241
1242 if (CONSTANT_P (y))
1243 {
1244 if (must_swap)
1245 y = force_reg (GET_MODE (x), y);
1246 else
1247 {
1248 int ok_const =
1249 (code == LTU || code == LEU || code == GTU || code == GEU)
1250 ? uint16_operand (y, GET_MODE (y))
1251 : reg_or_cmp_int16_operand (y, GET_MODE (y));
1252
1253 if (! ok_const)
1254 y = force_reg (GET_MODE (x), y);
1255 }
1256 }
1257
1258 switch (compare_code)
1259 {
1260 case EQ :
1261 emit_insn (gen_cmp_eqsi_insn (must_swap ? y : x, must_swap ? x : y));
1262 break;
1263 case LT :
1264 emit_insn (gen_cmp_ltsi_insn (must_swap ? y : x, must_swap ? x : y));
1265 break;
1266 case LTU :
1267 emit_insn (gen_cmp_ltusi_insn (must_swap ? y : x, must_swap ? x : y));
1268 break;
1269
1270 default:
1271 abort ();
1272 }
1273
1274 return gen_rtx (branch_code, VOIDmode, cc_reg, CONST0_RTX (CCmode));
1275 }
1276
1277 /* Split a 2 word move (DI or DF) into component parts. */
1278
1279 rtx
gen_split_move_double(operands)1280 gen_split_move_double (operands)
1281 rtx operands[];
1282 {
1283 enum machine_mode mode = GET_MODE (operands[0]);
1284 rtx dest = operands[0];
1285 rtx src = operands[1];
1286 rtx val;
1287
1288 /* We might have (SUBREG (MEM)) here, so just get rid of the
1289 subregs to make this code simpler. It is safe to call
1290 alter_subreg any time after reload. */
1291 if (GET_CODE (dest) == SUBREG)
1292 alter_subreg (&dest);
1293 if (GET_CODE (src) == SUBREG)
1294 alter_subreg (&src);
1295
1296 start_sequence ();
1297 if (GET_CODE (dest) == REG)
1298 {
1299 int dregno = REGNO (dest);
1300
1301 /* reg = reg */
1302 if (GET_CODE (src) == REG)
1303 {
1304 int sregno = REGNO (src);
1305
1306 int reverse = (dregno == sregno + 1);
1307
1308 /* We normally copy the low-numbered register first. However, if
1309 the first register operand 0 is the same as the second register of
1310 operand 1, we must copy in the opposite order. */
1311 emit_insn (gen_rtx_SET (VOIDmode,
1312 operand_subword (dest, reverse, TRUE, mode),
1313 operand_subword (src, reverse, TRUE, mode)));
1314
1315 emit_insn (gen_rtx_SET (VOIDmode,
1316 operand_subword (dest, !reverse, TRUE, mode),
1317 operand_subword (src, !reverse, TRUE, mode)));
1318 }
1319
1320 /* reg = constant */
1321 else if (GET_CODE (src) == CONST_INT || GET_CODE (src) == CONST_DOUBLE)
1322 {
1323 rtx words[2];
1324 split_double (src, &words[0], &words[1]);
1325 emit_insn (gen_rtx_SET (VOIDmode,
1326 operand_subword (dest, 0, TRUE, mode),
1327 words[0]));
1328
1329 emit_insn (gen_rtx_SET (VOIDmode,
1330 operand_subword (dest, 1, TRUE, mode),
1331 words[1]));
1332 }
1333
1334 /* reg = mem */
1335 else if (GET_CODE (src) == MEM)
1336 {
1337 /* If the high-address word is used in the address, we must load it
1338 last. Otherwise, load it first. */
1339 int reverse
1340 = (refers_to_regno_p (dregno, dregno + 1, XEXP (src, 0), 0) != 0);
1341
1342 /* We used to optimize loads from single registers as
1343
1344 ld r1,r3+; ld r2,r3
1345
1346 if r3 were not used subsequently. However, the REG_NOTES aren't
1347 propigated correctly by the reload phase, and it can cause bad
1348 code to be generated. We could still try:
1349
1350 ld r1,r3+; ld r2,r3; addi r3,-4
1351
1352 which saves 2 bytes and doesn't force longword alignment. */
1353 emit_insn (gen_rtx_SET (VOIDmode,
1354 operand_subword (dest, reverse, TRUE, mode),
1355 adjust_address (src, SImode,
1356 reverse * UNITS_PER_WORD)));
1357
1358 emit_insn (gen_rtx_SET (VOIDmode,
1359 operand_subword (dest, !reverse, TRUE, mode),
1360 adjust_address (src, SImode,
1361 !reverse * UNITS_PER_WORD)));
1362 }
1363
1364 else
1365 abort ();
1366 }
1367
1368 /* mem = reg */
1369 /* We used to optimize loads from single registers as
1370
1371 st r1,r3; st r2,+r3
1372
1373 if r3 were not used subsequently. However, the REG_NOTES aren't
1374 propigated correctly by the reload phase, and it can cause bad
1375 code to be generated. We could still try:
1376
1377 st r1,r3; st r2,+r3; addi r3,-4
1378
1379 which saves 2 bytes and doesn't force longword alignment. */
1380 else if (GET_CODE (dest) == MEM && GET_CODE (src) == REG)
1381 {
1382 emit_insn (gen_rtx_SET (VOIDmode,
1383 adjust_address (dest, SImode, 0),
1384 operand_subword (src, 0, TRUE, mode)));
1385
1386 emit_insn (gen_rtx_SET (VOIDmode,
1387 adjust_address (dest, SImode, UNITS_PER_WORD),
1388 operand_subword (src, 1, TRUE, mode)));
1389 }
1390
1391 else
1392 abort ();
1393
1394 val = get_insns ();
1395 end_sequence ();
1396 return val;
1397 }
1398
1399
1400 /* Implements the FUNCTION_ARG_PARTIAL_NREGS macro. */
1401
1402 int
function_arg_partial_nregs(cum,mode,type,named)1403 function_arg_partial_nregs (cum, mode, type, named)
1404 CUMULATIVE_ARGS *cum;
1405 enum machine_mode mode;
1406 tree type;
1407 int named ATTRIBUTE_UNUSED;
1408 {
1409 int ret;
1410 unsigned int size =
1411 (((mode == BLKmode && type)
1412 ? (unsigned int) int_size_in_bytes (type)
1413 : GET_MODE_SIZE (mode)) + UNITS_PER_WORD - 1)
1414 / UNITS_PER_WORD;
1415
1416 if (*cum >= M32R_MAX_PARM_REGS)
1417 ret = 0;
1418 else if (*cum + size > M32R_MAX_PARM_REGS)
1419 ret = (*cum + size) - M32R_MAX_PARM_REGS;
1420 else
1421 ret = 0;
1422
1423 return ret;
1424 }
1425
1426 /* Do any needed setup for a variadic function. For the M32R, we must
1427 create a register parameter block, and then copy any anonymous arguments
1428 in registers to memory.
1429
1430 CUM has not been updated for the last named argument which has type TYPE
1431 and mode MODE, and we rely on this fact. */
1432
1433 void
m32r_setup_incoming_varargs(cum,mode,type,pretend_size,no_rtl)1434 m32r_setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl)
1435 CUMULATIVE_ARGS *cum;
1436 enum machine_mode mode;
1437 tree type;
1438 int *pretend_size;
1439 int no_rtl;
1440 {
1441 int first_anon_arg;
1442
1443 if (no_rtl)
1444 return;
1445
1446 /* All BLKmode values are passed by reference. */
1447 if (mode == BLKmode)
1448 abort ();
1449
1450 first_anon_arg = (ROUND_ADVANCE_CUM (*cum, mode, type)
1451 + ROUND_ADVANCE_ARG (mode, type));
1452
1453 if (first_anon_arg < M32R_MAX_PARM_REGS)
1454 {
1455 /* Note that first_reg_offset < M32R_MAX_PARM_REGS. */
1456 int first_reg_offset = first_anon_arg;
1457 /* Size in words to "pretend" allocate. */
1458 int size = M32R_MAX_PARM_REGS - first_reg_offset;
1459 rtx regblock;
1460
1461 regblock = gen_rtx_MEM (BLKmode,
1462 plus_constant (arg_pointer_rtx,
1463 FIRST_PARM_OFFSET (0)));
1464 set_mem_alias_set (regblock, get_varargs_alias_set ());
1465 move_block_from_reg (first_reg_offset, regblock,
1466 size, size * UNITS_PER_WORD);
1467
1468 *pretend_size = (size * UNITS_PER_WORD);
1469 }
1470 }
1471
1472
1473 /* Implement `va_arg'. */
1474
1475 rtx
m32r_va_arg(valist,type)1476 m32r_va_arg (valist, type)
1477 tree valist, type;
1478 {
1479 HOST_WIDE_INT size, rsize;
1480 tree t;
1481 rtx addr_rtx;
1482
1483 size = int_size_in_bytes (type);
1484 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
1485
1486 if (size > 8)
1487 {
1488 tree type_ptr, type_ptr_ptr;
1489
1490 /* Pass by reference. */
1491
1492 type_ptr = build_pointer_type (type);
1493 type_ptr_ptr = build_pointer_type (type_ptr);
1494
1495 t = build (POSTINCREMENT_EXPR, va_list_type_node, valist,
1496 build_int_2 (UNITS_PER_WORD, 0));
1497 TREE_SIDE_EFFECTS (t) = 1;
1498 t = build1 (NOP_EXPR, type_ptr_ptr, t);
1499 TREE_SIDE_EFFECTS (t) = 1;
1500 t = build1 (INDIRECT_REF, type_ptr, t);
1501
1502 addr_rtx = expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
1503 }
1504 else
1505 {
1506 /* Pass by value. */
1507
1508 if (size < UNITS_PER_WORD)
1509 {
1510 /* Care for bigendian correction on the aligned address. */
1511 t = build (PLUS_EXPR, ptr_type_node, valist,
1512 build_int_2 (rsize - size, 0));
1513 addr_rtx = expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
1514 addr_rtx = copy_to_reg (addr_rtx);
1515
1516 /* Increment AP. */
1517 t = build (PLUS_EXPR, va_list_type_node, valist,
1518 build_int_2 (rsize, 0));
1519 t = build (MODIFY_EXPR, va_list_type_node, valist, t);
1520 TREE_SIDE_EFFECTS (t) = 1;
1521 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
1522 }
1523 else
1524 {
1525 t = build (POSTINCREMENT_EXPR, va_list_type_node, valist,
1526 build_int_2 (rsize, 0));
1527 TREE_SIDE_EFFECTS (t) = 1;
1528 addr_rtx = expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
1529 }
1530 }
1531
1532 return addr_rtx;
1533 }
1534
1535 static int
m32r_adjust_cost(insn,link,dep_insn,cost)1536 m32r_adjust_cost (insn, link, dep_insn, cost)
1537 rtx insn ATTRIBUTE_UNUSED;
1538 rtx link ATTRIBUTE_UNUSED;
1539 rtx dep_insn ATTRIBUTE_UNUSED;
1540 int cost;
1541 {
1542 return cost;
1543 }
1544
1545
1546 /* Return true if INSN is real instruction bearing insn. */
1547
1548 static int
m32r_is_insn(insn)1549 m32r_is_insn (insn)
1550 rtx insn;
1551 {
1552 return (INSN_P (insn)
1553 && GET_CODE (PATTERN (insn)) != USE
1554 && GET_CODE (PATTERN (insn)) != CLOBBER
1555 && GET_CODE (PATTERN (insn)) != ADDR_VEC);
1556 }
1557
1558 /* Increase the priority of long instructions so that the
1559 short instructions are scheduled ahead of the long ones. */
1560
1561 static int
m32r_adjust_priority(insn,priority)1562 m32r_adjust_priority (insn, priority)
1563 rtx insn;
1564 int priority;
1565 {
1566 if (m32r_is_insn (insn)
1567 && get_attr_insn_size (insn) != INSN_SIZE_SHORT)
1568 priority <<= 3;
1569
1570 return priority;
1571 }
1572
1573
1574 /* Initialize for scheduling a group of instructions. */
1575
1576 static void
m32r_sched_init(stream,verbose,max_ready)1577 m32r_sched_init (stream, verbose, max_ready)
1578 FILE * stream ATTRIBUTE_UNUSED;
1579 int verbose ATTRIBUTE_UNUSED;
1580 int max_ready ATTRIBUTE_UNUSED;
1581 {
1582 m32r_sched_odd_word_p = FALSE;
1583 }
1584
1585
1586 /* Reorder the schedulers priority list if needed */
1587
1588 static int
m32r_sched_reorder(stream,verbose,ready,n_readyp,clock)1589 m32r_sched_reorder (stream, verbose, ready, n_readyp, clock)
1590 FILE * stream;
1591 int verbose;
1592 rtx * ready;
1593 int *n_readyp;
1594 int clock ATTRIBUTE_UNUSED;
1595 {
1596 int n_ready = *n_readyp;
1597
1598 if (TARGET_DEBUG)
1599 return m32r_issue_rate ();
1600
1601 if (verbose <= 7)
1602 stream = (FILE *)0;
1603
1604 if (stream)
1605 fprintf (stream,
1606 ";;\t\t::: Looking at %d insn(s) on ready list, boundary is %s word\n",
1607 n_ready,
1608 (m32r_sched_odd_word_p) ? "odd" : "even");
1609
1610 if (n_ready > 1)
1611 {
1612 rtx * long_head = (rtx *) alloca (sizeof (rtx) * n_ready);
1613 rtx * long_tail = long_head;
1614 rtx * short_head = (rtx *) alloca (sizeof (rtx) * n_ready);
1615 rtx * short_tail = short_head;
1616 rtx * new_head = (rtx *) alloca (sizeof (rtx) * n_ready);
1617 rtx * new_tail = new_head + (n_ready - 1);
1618 int i;
1619
1620 /* Loop through the instructions, classifing them as short/long. Try
1621 to keep 2 short together and/or 1 long. Note, the ready list is
1622 actually ordered backwards, so keep it in that manner. */
1623 for (i = n_ready-1; i >= 0; i--)
1624 {
1625 rtx insn = ready[i];
1626
1627 if (! m32r_is_insn (insn))
1628 {
1629 /* Dump all current short/long insns just in case. */
1630 while (long_head != long_tail)
1631 *new_tail-- = *long_head++;
1632
1633 while (short_head != short_tail)
1634 *new_tail-- = *short_head++;
1635
1636 *new_tail-- = insn;
1637 if (stream)
1638 fprintf (stream,
1639 ";;\t\t::: Skipping non instruction %d\n",
1640 INSN_UID (insn));
1641
1642 }
1643
1644 else
1645 {
1646 if (get_attr_insn_size (insn) != INSN_SIZE_SHORT)
1647 *long_tail++ = insn;
1648
1649 else
1650 *short_tail++ = insn;
1651 }
1652 }
1653
1654 /* If we are on an odd word, emit a single short instruction if
1655 we can */
1656 if (m32r_sched_odd_word_p && short_head != short_tail)
1657 *new_tail-- = *short_head++;
1658
1659 /* Now dump out all of the long instructions */
1660 while (long_head != long_tail)
1661 *new_tail-- = *long_head++;
1662
1663 /* Now dump out all of the short instructions */
1664 while (short_head != short_tail)
1665 *new_tail-- = *short_head++;
1666
1667 if (new_tail+1 != new_head)
1668 abort ();
1669
1670 memcpy (ready, new_head, sizeof (rtx) * n_ready);
1671 if (stream)
1672 {
1673 int i;
1674 fprintf (stream, ";;\t\t::: New ready list: ");
1675 for (i = 0; i < n_ready; i++)
1676 {
1677 rtx insn = ready[i];
1678
1679 fprintf (stream, " %d", INSN_UID (ready[i]));
1680
1681 if (! m32r_is_insn (insn))
1682 fputs ("(?)", stream);
1683
1684 else if (get_attr_insn_size (insn) != INSN_SIZE_SHORT)
1685 fputs ("(l)", stream);
1686
1687 else
1688 fputs ("(s)", stream);
1689 }
1690
1691 fprintf (stream, "\n");
1692 }
1693 }
1694 return m32r_issue_rate ();
1695 }
1696
1697 /* Indicate how many instructions can be issued at the same time.
1698 This is sort of a lie. The m32r can issue only 1 long insn at
1699 once, but it can issue 2 short insns. The default therefore is
1700 set at 2, but this can be overridden by the command line option
1701 -missue-rate=1 */
1702 static int
m32r_issue_rate()1703 m32r_issue_rate ()
1704 {
1705 return ((TARGET_LOW_ISSUE_RATE) ? 1 : 2);
1706 }
1707
1708 /* If we have a machine that can issue a variable # of instructions
1709 per cycle, indicate how many more instructions can be issued
1710 after the current one. */
1711 static int
m32r_variable_issue(stream,verbose,insn,how_many)1712 m32r_variable_issue (stream, verbose, insn, how_many)
1713 FILE * stream;
1714 int verbose;
1715 rtx insn;
1716 int how_many;
1717 {
1718 int orig_odd_word_p = m32r_sched_odd_word_p;
1719 int short_p = FALSE;
1720
1721 how_many--;
1722 if (how_many > 0 && !TARGET_DEBUG)
1723 {
1724 if (! m32r_is_insn (insn))
1725 how_many++;
1726
1727 else if (get_attr_insn_size (insn) != INSN_SIZE_SHORT)
1728 {
1729 how_many = 0;
1730 m32r_sched_odd_word_p = 0;
1731 }
1732 else
1733 {
1734 m32r_sched_odd_word_p = !m32r_sched_odd_word_p;
1735 short_p = TRUE;
1736 }
1737 }
1738
1739 if (verbose > 7 && stream)
1740 fprintf (stream,
1741 ";;\t\t::: %s insn %d starts on an %s word, can emit %d more instruction(s)\n",
1742 short_p ? "short" : "long",
1743 INSN_UID (insn),
1744 orig_odd_word_p ? "odd" : "even",
1745 how_many);
1746
1747 return how_many;
1748 }
1749
1750 /* Cost functions. */
1751
1752 /* Provide the costs of an addressing mode that contains ADDR.
1753 If ADDR is not a valid address, its cost is irrelevant.
1754
1755 This function is trivial at the moment. This code doesn't live
1756 in m32r.h so it's easy to experiment. */
1757
1758 int
m32r_address_cost(addr)1759 m32r_address_cost (addr)
1760 rtx addr ATTRIBUTE_UNUSED;
1761 {
1762 return 1;
1763 }
1764
1765 /* Type of function DECL.
1766
1767 The result is cached. To reset the cache at the end of a function,
1768 call with DECL = NULL_TREE. */
1769
1770 enum m32r_function_type
m32r_compute_function_type(decl)1771 m32r_compute_function_type (decl)
1772 tree decl;
1773 {
1774 /* Cached value. */
1775 static enum m32r_function_type fn_type = M32R_FUNCTION_UNKNOWN;
1776 /* Last function we were called for. */
1777 static tree last_fn = NULL_TREE;
1778
1779 /* Resetting the cached value? */
1780 if (decl == NULL_TREE)
1781 {
1782 fn_type = M32R_FUNCTION_UNKNOWN;
1783 last_fn = NULL_TREE;
1784 return fn_type;
1785 }
1786
1787 if (decl == last_fn && fn_type != M32R_FUNCTION_UNKNOWN)
1788 return fn_type;
1789
1790 /* Compute function type. */
1791 fn_type = (lookup_attribute ("interrupt", DECL_ATTRIBUTES (current_function_decl)) != NULL_TREE
1792 ? M32R_FUNCTION_INTERRUPT
1793 : M32R_FUNCTION_NORMAL);
1794
1795 last_fn = decl;
1796 return fn_type;
1797 }
1798 /* Function prologue/epilogue handlers. */
1799
1800 /* M32R stack frames look like:
1801
1802 Before call After call
1803 +-----------------------+ +-----------------------+
1804 | | | |
1805 high | local variables, | | local variables, |
1806 mem | reg save area, etc. | | reg save area, etc. |
1807 | | | |
1808 +-----------------------+ +-----------------------+
1809 | | | |
1810 | arguments on stack. | | arguments on stack. |
1811 | | | |
1812 SP+0->+-----------------------+ +-----------------------+
1813 | reg parm save area, |
1814 | only created for |
1815 | variable argument |
1816 | functions |
1817 +-----------------------+
1818 | previous frame ptr |
1819 +-----------------------+
1820 | |
1821 | register save area |
1822 | |
1823 +-----------------------+
1824 | return address |
1825 +-----------------------+
1826 | |
1827 | local variables |
1828 | |
1829 +-----------------------+
1830 | |
1831 | alloca allocations |
1832 | |
1833 +-----------------------+
1834 | |
1835 low | arguments on stack |
1836 memory | |
1837 SP+0->+-----------------------+
1838
1839 Notes:
1840 1) The "reg parm save area" does not exist for non variable argument fns.
1841 2) The "reg parm save area" can be eliminated completely if we saved regs
1842 containing anonymous args separately but that complicates things too
1843 much (so it's not done).
1844 3) The return address is saved after the register save area so as to have as
1845 many insns as possible between the restoration of `lr' and the `jmp lr'.
1846 */
1847
1848 /* Structure to be filled in by m32r_compute_frame_size with register
1849 save masks, and offsets for the current function. */
1850 struct m32r_frame_info
1851 {
1852 unsigned int total_size; /* # bytes that the entire frame takes up */
1853 unsigned int extra_size; /* # bytes of extra stuff */
1854 unsigned int pretend_size; /* # bytes we push and pretend caller did */
1855 unsigned int args_size; /* # bytes that outgoing arguments take up */
1856 unsigned int reg_size; /* # bytes needed to store regs */
1857 unsigned int var_size; /* # bytes that variables take up */
1858 unsigned int gmask; /* mask of saved gp registers */
1859 unsigned int save_fp; /* nonzero if fp must be saved */
1860 unsigned int save_lr; /* nonzero if lr (return addr) must be saved */
1861 int initialized; /* nonzero if frame size already calculated */
1862 };
1863
1864 /* Current frame information calculated by m32r_compute_frame_size. */
1865 static struct m32r_frame_info current_frame_info;
1866
1867 /* Zero structure to initialize current_frame_info. */
1868 static struct m32r_frame_info zero_frame_info;
1869
1870 #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
1871 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
1872
1873 /* Tell prologue and epilogue if register REGNO should be saved / restored.
1874 The return address and frame pointer are treated separately.
1875 Don't consider them here. */
1876 #define MUST_SAVE_REGISTER(regno, interrupt_p) \
1877 ((regno) != RETURN_ADDR_REGNUM && (regno) != FRAME_POINTER_REGNUM \
1878 && (regs_ever_live[regno] && (!call_used_regs[regno] || interrupt_p)))
1879
1880 #define MUST_SAVE_FRAME_POINTER (regs_ever_live[FRAME_POINTER_REGNUM])
1881 #define MUST_SAVE_RETURN_ADDR (regs_ever_live[RETURN_ADDR_REGNUM] || current_function_profile)
1882
1883 #define SHORT_INSN_SIZE 2 /* size of small instructions */
1884 #define LONG_INSN_SIZE 4 /* size of long instructions */
1885
1886 /* Return the bytes needed to compute the frame pointer from the current
1887 stack pointer.
1888
1889 SIZE is the size needed for local variables. */
1890
1891 unsigned int
m32r_compute_frame_size(size)1892 m32r_compute_frame_size (size)
1893 int size; /* # of var. bytes allocated. */
1894 {
1895 int regno;
1896 unsigned int total_size, var_size, args_size, pretend_size, extra_size;
1897 unsigned int reg_size, frame_size;
1898 unsigned int gmask;
1899 enum m32r_function_type fn_type;
1900 int interrupt_p;
1901
1902 var_size = M32R_STACK_ALIGN (size);
1903 args_size = M32R_STACK_ALIGN (current_function_outgoing_args_size);
1904 pretend_size = current_function_pretend_args_size;
1905 extra_size = FIRST_PARM_OFFSET (0);
1906 total_size = extra_size + pretend_size + args_size + var_size;
1907 reg_size = 0;
1908 gmask = 0;
1909
1910 /* See if this is an interrupt handler. Call used registers must be saved
1911 for them too. */
1912 fn_type = m32r_compute_function_type (current_function_decl);
1913 interrupt_p = M32R_INTERRUPT_P (fn_type);
1914
1915 /* Calculate space needed for registers. */
1916
1917 for (regno = 0; regno < M32R_MAX_INT_REGS; regno++)
1918 {
1919 if (MUST_SAVE_REGISTER (regno, interrupt_p))
1920 {
1921 reg_size += UNITS_PER_WORD;
1922 gmask |= 1 << regno;
1923 }
1924 }
1925
1926 current_frame_info.save_fp = MUST_SAVE_FRAME_POINTER;
1927 current_frame_info.save_lr = MUST_SAVE_RETURN_ADDR;
1928
1929 reg_size += ((current_frame_info.save_fp + current_frame_info.save_lr)
1930 * UNITS_PER_WORD);
1931 total_size += reg_size;
1932
1933 /* ??? Not sure this is necessary, and I don't think the epilogue
1934 handler will do the right thing if this changes total_size. */
1935 total_size = M32R_STACK_ALIGN (total_size);
1936
1937 frame_size = total_size - (pretend_size + reg_size);
1938
1939 /* Save computed information. */
1940 current_frame_info.total_size = total_size;
1941 current_frame_info.extra_size = extra_size;
1942 current_frame_info.pretend_size = pretend_size;
1943 current_frame_info.var_size = var_size;
1944 current_frame_info.args_size = args_size;
1945 current_frame_info.reg_size = reg_size;
1946 current_frame_info.gmask = gmask;
1947 current_frame_info.initialized = reload_completed;
1948
1949 /* Ok, we're done. */
1950 return total_size;
1951 }
1952
1953 /* When the `length' insn attribute is used, this macro specifies the
1954 value to be assigned to the address of the first insn in a
1955 function. If not specified, 0 is used. */
1956
1957 int
m32r_first_insn_address()1958 m32r_first_insn_address ()
1959 {
1960 if (! current_frame_info.initialized)
1961 m32r_compute_frame_size (get_frame_size ());
1962
1963 return 0;
1964 }
1965
1966 /* Expand the m32r prologue as a series of insns. */
1967
1968 void
m32r_expand_prologue()1969 m32r_expand_prologue ()
1970 {
1971 int regno;
1972 int frame_size;
1973 unsigned int gmask;
1974
1975 if (! current_frame_info.initialized)
1976 m32r_compute_frame_size (get_frame_size ());
1977
1978 gmask = current_frame_info.gmask;
1979
1980 /* These cases shouldn't happen. Catch them now. */
1981 if (current_frame_info.total_size == 0 && gmask)
1982 abort ();
1983
1984 /* Allocate space for register arguments if this is a variadic function. */
1985 if (current_frame_info.pretend_size != 0)
1986 {
1987 /* Use a HOST_WIDE_INT temporary, since negating an unsigned int gives
1988 the wrong result on a 64-bit host. */
1989 HOST_WIDE_INT pretend_size = current_frame_info.pretend_size;
1990 emit_insn (gen_addsi3 (stack_pointer_rtx,
1991 stack_pointer_rtx,
1992 GEN_INT (-pretend_size)));
1993 }
1994
1995 /* Save any registers we need to and set up fp. */
1996
1997 if (current_frame_info.save_fp)
1998 emit_insn (gen_movsi_push (stack_pointer_rtx, frame_pointer_rtx));
1999
2000 gmask &= ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK);
2001
2002 /* Save any needed call-saved regs (and call-used if this is an
2003 interrupt handler). */
2004 for (regno = 0; regno <= M32R_MAX_INT_REGS; ++regno)
2005 {
2006 if ((gmask & (1 << regno)) != 0)
2007 emit_insn (gen_movsi_push (stack_pointer_rtx,
2008 gen_rtx_REG (Pmode, regno)));
2009 }
2010
2011 if (current_frame_info.save_lr)
2012 emit_insn (gen_movsi_push (stack_pointer_rtx,
2013 gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM)));
2014
2015 /* Allocate the stack frame. */
2016 frame_size = (current_frame_info.total_size
2017 - (current_frame_info.pretend_size
2018 + current_frame_info.reg_size));
2019
2020 if (frame_size == 0)
2021 ; /* nothing to do */
2022 else if (frame_size <= 32768)
2023 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
2024 GEN_INT (-frame_size)));
2025 else
2026 {
2027 rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM);
2028 emit_insn (gen_movsi (tmp, GEN_INT (frame_size)));
2029 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, tmp));
2030 }
2031
2032 if (frame_pointer_needed)
2033 emit_insn (gen_movsi (frame_pointer_rtx, stack_pointer_rtx));
2034
2035 if (current_function_profile)
2036 emit_insn (gen_blockage ());
2037 }
2038
2039
2040 /* Set up the stack and frame pointer (if desired) for the function.
2041 Note, if this is changed, you need to mirror the changes in
2042 m32r_compute_frame_size which calculates the prolog size. */
2043
2044 static void
m32r_output_function_prologue(file,size)2045 m32r_output_function_prologue (file, size)
2046 FILE * file;
2047 HOST_WIDE_INT size;
2048 {
2049 enum m32r_function_type fn_type = m32r_compute_function_type (current_function_decl);
2050
2051 /* If this is an interrupt handler, mark it as such. */
2052 if (M32R_INTERRUPT_P (fn_type))
2053 {
2054 fprintf (file, "\t%s interrupt handler\n",
2055 ASM_COMMENT_START);
2056 }
2057
2058 if (! current_frame_info.initialized)
2059 m32r_compute_frame_size (size);
2060
2061 /* This is only for the human reader. */
2062 fprintf (file,
2063 "\t%s PROLOGUE, vars= %d, regs= %d, args= %d, extra= %d\n",
2064 ASM_COMMENT_START,
2065 current_frame_info.var_size,
2066 current_frame_info.reg_size / 4,
2067 current_frame_info.args_size,
2068 current_frame_info.extra_size);
2069 }
2070
2071 /* Do any necessary cleanup after a function to restore stack, frame,
2072 and regs. */
2073
2074 static void
m32r_output_function_epilogue(file,size)2075 m32r_output_function_epilogue (file, size)
2076 FILE * file;
2077 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
2078 {
2079 int regno;
2080 int noepilogue = FALSE;
2081 int total_size;
2082 enum m32r_function_type fn_type = m32r_compute_function_type (current_function_decl);
2083
2084 /* This is only for the human reader. */
2085 fprintf (file, "\t%s EPILOGUE\n", ASM_COMMENT_START);
2086
2087 if (!current_frame_info.initialized)
2088 abort ();
2089 total_size = current_frame_info.total_size;
2090
2091 if (total_size == 0)
2092 {
2093 rtx insn = get_last_insn ();
2094
2095 /* If the last insn was a BARRIER, we don't have to write any code
2096 because a jump (aka return) was put there. */
2097 if (GET_CODE (insn) == NOTE)
2098 insn = prev_nonnote_insn (insn);
2099 if (insn && GET_CODE (insn) == BARRIER)
2100 noepilogue = TRUE;
2101 }
2102
2103 if (!noepilogue)
2104 {
2105 unsigned int var_size = current_frame_info.var_size;
2106 unsigned int args_size = current_frame_info.args_size;
2107 unsigned int gmask = current_frame_info.gmask;
2108 int can_trust_sp_p = !current_function_calls_alloca;
2109 const char * sp_str = reg_names[STACK_POINTER_REGNUM];
2110 const char * fp_str = reg_names[FRAME_POINTER_REGNUM];
2111
2112 /* The first thing to do is point the sp at the bottom of the register
2113 save area. */
2114 if (can_trust_sp_p)
2115 {
2116 unsigned int reg_offset = var_size + args_size;
2117 if (reg_offset == 0)
2118 ; /* nothing to do */
2119 else if (reg_offset < 128)
2120 fprintf (file, "\taddi %s,%s%d\n",
2121 sp_str, IMMEDIATE_PREFIX, reg_offset);
2122 else if (reg_offset < 32768)
2123 fprintf (file, "\tadd3 %s,%s,%s%d\n",
2124 sp_str, sp_str, IMMEDIATE_PREFIX, reg_offset);
2125 else
2126 fprintf (file, "\tld24 %s,%s%d\n\tadd %s,%s\n",
2127 reg_names[PROLOGUE_TMP_REGNUM],
2128 IMMEDIATE_PREFIX, reg_offset,
2129 sp_str, reg_names[PROLOGUE_TMP_REGNUM]);
2130 }
2131 else if (frame_pointer_needed)
2132 {
2133 unsigned int reg_offset = var_size + args_size;
2134 if (reg_offset == 0)
2135 fprintf (file, "\tmv %s,%s\n", sp_str, fp_str);
2136 else if (reg_offset < 32768)
2137 fprintf (file, "\tadd3 %s,%s,%s%d\n",
2138 sp_str, fp_str, IMMEDIATE_PREFIX, reg_offset);
2139 else
2140 fprintf (file, "\tld24 %s,%s%d\n\tadd %s,%s\n",
2141 reg_names[PROLOGUE_TMP_REGNUM],
2142 IMMEDIATE_PREFIX, reg_offset,
2143 sp_str, reg_names[PROLOGUE_TMP_REGNUM]);
2144 }
2145 else
2146 abort ();
2147
2148 if (current_frame_info.save_lr)
2149 fprintf (file, "\tpop %s\n", reg_names[RETURN_ADDR_REGNUM]);
2150
2151 /* Restore any saved registers, in reverse order of course. */
2152 gmask &= ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK);
2153 for (regno = M32R_MAX_INT_REGS - 1; regno >= 0; --regno)
2154 {
2155 if ((gmask & (1L << regno)) != 0)
2156 fprintf (file, "\tpop %s\n", reg_names[regno]);
2157 }
2158
2159 if (current_frame_info.save_fp)
2160 fprintf (file, "\tpop %s\n", fp_str);
2161
2162 /* Remove varargs area if present. */
2163 if (current_frame_info.pretend_size != 0)
2164 fprintf (file, "\taddi %s,%s%d\n",
2165 sp_str, IMMEDIATE_PREFIX, current_frame_info.pretend_size);
2166
2167 /* Emit the return instruction. */
2168 if (M32R_INTERRUPT_P (fn_type))
2169 fprintf (file, "\trte\n");
2170 else
2171 fprintf (file, "\tjmp %s\n", reg_names[RETURN_ADDR_REGNUM]);
2172 }
2173
2174 #if 0 /* no longer needed */
2175 /* Ensure the function cleanly ends on a 32 bit boundary. */
2176 fprintf (file, "\t.fillinsn\n");
2177 #endif
2178
2179 /* Reset state info for each function. */
2180 current_frame_info = zero_frame_info;
2181 m32r_compute_function_type (NULL_TREE);
2182 }
2183
2184 /* Return nonzero if this function is known to have a null or 1 instruction
2185 epilogue. */
2186
2187 int
direct_return()2188 direct_return ()
2189 {
2190 if (!reload_completed)
2191 return FALSE;
2192
2193 if (! current_frame_info.initialized)
2194 m32r_compute_frame_size (get_frame_size ());
2195
2196 return current_frame_info.total_size == 0;
2197 }
2198
2199
2200 /* PIC */
2201
2202 /* Emit special PIC prologues and epilogues. */
2203
2204 void
m32r_finalize_pic()2205 m32r_finalize_pic ()
2206 {
2207 /* nothing to do */
2208 }
2209
2210 /* Nested function support. */
2211
2212 /* Emit RTL insns to initialize the variable parts of a trampoline.
2213 FNADDR is an RTX for the address of the function's pure code.
2214 CXT is an RTX for the static chain value for the function. */
2215
2216 void
m32r_initialize_trampoline(tramp,fnaddr,cxt)2217 m32r_initialize_trampoline (tramp, fnaddr, cxt)
2218 rtx tramp ATTRIBUTE_UNUSED;
2219 rtx fnaddr ATTRIBUTE_UNUSED;
2220 rtx cxt ATTRIBUTE_UNUSED;
2221 {
2222 }
2223
2224 /* Set the cpu type and print out other fancy things,
2225 at the top of the file. */
2226
2227 void
m32r_asm_file_start(file)2228 m32r_asm_file_start (file)
2229 FILE * file;
2230 {
2231 if (flag_verbose_asm)
2232 fprintf (file, "%s M32R/D special options: -G %d\n",
2233 ASM_COMMENT_START, g_switch_value);
2234 }
2235
2236 /* Print operand X (an rtx) in assembler syntax to file FILE.
2237 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2238 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2239
2240 void
m32r_print_operand(file,x,code)2241 m32r_print_operand (file, x, code)
2242 FILE * file;
2243 rtx x;
2244 int code;
2245 {
2246 rtx addr;
2247
2248 switch (code)
2249 {
2250 /* The 's' and 'p' codes are used by output_block_move() to
2251 indicate pre-increment 's'tores and 'p'ost-increment loads. */
2252 case 's':
2253 if (GET_CODE (x) == REG)
2254 fprintf (file, "@+%s", reg_names [REGNO (x)]);
2255 else
2256 output_operand_lossage ("invalid operand to %%s code");
2257 return;
2258
2259 case 'p':
2260 if (GET_CODE (x) == REG)
2261 fprintf (file, "@%s+", reg_names [REGNO (x)]);
2262 else
2263 output_operand_lossage ("invalid operand to %%p code");
2264 return;
2265
2266 case 'R' :
2267 /* Write second word of DImode or DFmode reference,
2268 register or memory. */
2269 if (GET_CODE (x) == REG)
2270 fputs (reg_names[REGNO (x)+1], file);
2271 else if (GET_CODE (x) == MEM)
2272 {
2273 fprintf (file, "@(");
2274 /* Handle possible auto-increment. Since it is pre-increment and
2275 we have already done it, we can just use an offset of four. */
2276 /* ??? This is taken from rs6000.c I think. I don't think it is
2277 currently necessary, but keep it around. */
2278 if (GET_CODE (XEXP (x, 0)) == PRE_INC
2279 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
2280 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 4));
2281 else
2282 output_address (plus_constant (XEXP (x, 0), 4));
2283 fputc (')', file);
2284 }
2285 else
2286 output_operand_lossage ("invalid operand to %%R code");
2287 return;
2288
2289 case 'H' : /* High word */
2290 case 'L' : /* Low word */
2291 if (GET_CODE (x) == REG)
2292 {
2293 /* L = least significant word, H = most significant word */
2294 if ((WORDS_BIG_ENDIAN != 0) ^ (code == 'L'))
2295 fputs (reg_names[REGNO (x)], file);
2296 else
2297 fputs (reg_names[REGNO (x)+1], file);
2298 }
2299 else if (GET_CODE (x) == CONST_INT
2300 || GET_CODE (x) == CONST_DOUBLE)
2301 {
2302 rtx first, second;
2303
2304 split_double (x, &first, &second);
2305 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
2306 code == 'L' ? INTVAL (first) : INTVAL (second));
2307 }
2308 else
2309 output_operand_lossage ("invalid operand to %%H/%%L code");
2310 return;
2311
2312 case 'A' :
2313 {
2314 char str[30];
2315
2316 if (GET_CODE (x) != CONST_DOUBLE
2317 || GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT)
2318 fatal_insn ("bad insn for 'A'", x);
2319
2320 real_to_decimal (str, CONST_DOUBLE_REAL_VALUE (x), sizeof (str), 0, 1);
2321 fprintf (file, "%s", str);
2322 return;
2323 }
2324
2325 case 'B' : /* Bottom half */
2326 case 'T' : /* Top half */
2327 /* Output the argument to a `seth' insn (sets the Top half-word).
2328 For constants output arguments to a seth/or3 pair to set Top and
2329 Bottom halves. For symbols output arguments to a seth/add3 pair to
2330 set Top and Bottom halves. The difference exists because for
2331 constants seth/or3 is more readable but for symbols we need to use
2332 the same scheme as `ld' and `st' insns (16 bit addend is signed). */
2333 switch (GET_CODE (x))
2334 {
2335 case CONST_INT :
2336 case CONST_DOUBLE :
2337 {
2338 rtx first, second;
2339
2340 split_double (x, &first, &second);
2341 x = WORDS_BIG_ENDIAN ? second : first;
2342 fprintf (file,
2343 #if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT
2344 "0x%x",
2345 #else
2346 "0x%lx",
2347 #endif
2348 (code == 'B'
2349 ? INTVAL (x) & 0xffff
2350 : (INTVAL (x) >> 16) & 0xffff));
2351 }
2352 return;
2353 case CONST :
2354 case SYMBOL_REF :
2355 if (code == 'B'
2356 && small_data_operand (x, VOIDmode))
2357 {
2358 fputs ("sda(", file);
2359 output_addr_const (file, x);
2360 fputc (')', file);
2361 return;
2362 }
2363 /* fall through */
2364 case LABEL_REF :
2365 fputs (code == 'T' ? "shigh(" : "low(", file);
2366 output_addr_const (file, x);
2367 fputc (')', file);
2368 return;
2369 default :
2370 output_operand_lossage ("invalid operand to %%T/%%B code");
2371 return;
2372 }
2373 break;
2374
2375 case 'U' :
2376 /* ??? wip */
2377 /* Output a load/store with update indicator if appropriate. */
2378 if (GET_CODE (x) == MEM)
2379 {
2380 if (GET_CODE (XEXP (x, 0)) == PRE_INC
2381 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
2382 fputs (".a", file);
2383 }
2384 else
2385 output_operand_lossage ("invalid operand to %%U code");
2386 return;
2387
2388 case 'N' :
2389 /* Print a constant value negated. */
2390 if (GET_CODE (x) == CONST_INT)
2391 output_addr_const (file, GEN_INT (- INTVAL (x)));
2392 else
2393 output_operand_lossage ("invalid operand to %%N code");
2394 return;
2395
2396 case 'X' :
2397 /* Print a const_int in hex. Used in comments. */
2398 if (GET_CODE (x) == CONST_INT)
2399 fprintf (file,
2400 #if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT
2401 "0x%x",
2402 #else
2403 "0x%lx",
2404 #endif
2405 INTVAL (x));
2406 return;
2407
2408 case '#' :
2409 fputs (IMMEDIATE_PREFIX, file);
2410 return;
2411
2412 #if 0 /* ??? no longer used */
2413 case '@' :
2414 fputs (reg_names[SDA_REGNUM], file);
2415 return;
2416 #endif
2417
2418 case 0 :
2419 /* Do nothing special. */
2420 break;
2421
2422 default :
2423 /* Unknown flag. */
2424 output_operand_lossage ("invalid operand output code");
2425 }
2426
2427 switch (GET_CODE (x))
2428 {
2429 case REG :
2430 fputs (reg_names[REGNO (x)], file);
2431 break;
2432
2433 case MEM :
2434 addr = XEXP (x, 0);
2435 if (GET_CODE (addr) == PRE_INC)
2436 {
2437 if (GET_CODE (XEXP (addr, 0)) != REG)
2438 fatal_insn ("pre-increment address is not a register", x);
2439
2440 fprintf (file, "@+%s", reg_names[REGNO (XEXP (addr, 0))]);
2441 }
2442 else if (GET_CODE (addr) == PRE_DEC)
2443 {
2444 if (GET_CODE (XEXP (addr, 0)) != REG)
2445 fatal_insn ("pre-decrement address is not a register", x);
2446
2447 fprintf (file, "@-%s", reg_names[REGNO (XEXP (addr, 0))]);
2448 }
2449 else if (GET_CODE (addr) == POST_INC)
2450 {
2451 if (GET_CODE (XEXP (addr, 0)) != REG)
2452 fatal_insn ("post-increment address is not a register", x);
2453
2454 fprintf (file, "@%s+", reg_names[REGNO (XEXP (addr, 0))]);
2455 }
2456 else
2457 {
2458 fputs ("@(", file);
2459 output_address (XEXP (x, 0));
2460 fputc (')', file);
2461 }
2462 break;
2463
2464 case CONST_DOUBLE :
2465 /* We handle SFmode constants here as output_addr_const doesn't. */
2466 if (GET_MODE (x) == SFmode)
2467 {
2468 REAL_VALUE_TYPE d;
2469 long l;
2470
2471 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
2472 REAL_VALUE_TO_TARGET_SINGLE (d, l);
2473 fprintf (file, "0x%08lx", l);
2474 break;
2475 }
2476
2477 /* Fall through. Let output_addr_const deal with it. */
2478
2479 default :
2480 output_addr_const (file, x);
2481 break;
2482 }
2483 }
2484
2485 /* Print a memory address as an operand to reference that memory location. */
2486
2487 void
m32r_print_operand_address(file,addr)2488 m32r_print_operand_address (file, addr)
2489 FILE * file;
2490 rtx addr;
2491 {
2492 register rtx base;
2493 register rtx index = 0;
2494 int offset = 0;
2495
2496 switch (GET_CODE (addr))
2497 {
2498 case REG :
2499 fputs (reg_names[REGNO (addr)], file);
2500 break;
2501
2502 case PLUS :
2503 if (GET_CODE (XEXP (addr, 0)) == CONST_INT)
2504 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);
2505 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
2506 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);
2507 else
2508 base = XEXP (addr, 0), index = XEXP (addr, 1);
2509 if (GET_CODE (base) == REG)
2510 {
2511 /* Print the offset first (if present) to conform to the manual. */
2512 if (index == 0)
2513 {
2514 if (offset != 0)
2515 fprintf (file, "%d,", offset);
2516 fputs (reg_names[REGNO (base)], file);
2517 }
2518 /* The chip doesn't support this, but left in for generality. */
2519 else if (GET_CODE (index) == REG)
2520 fprintf (file, "%s,%s",
2521 reg_names[REGNO (base)], reg_names[REGNO (index)]);
2522 /* Not sure this can happen, but leave in for now. */
2523 else if (GET_CODE (index) == SYMBOL_REF)
2524 {
2525 output_addr_const (file, index);
2526 fputc (',', file);
2527 fputs (reg_names[REGNO (base)], file);
2528 }
2529 else
2530 fatal_insn ("bad address", addr);
2531 }
2532 else if (GET_CODE (base) == LO_SUM)
2533 {
2534 if (index != 0
2535 || GET_CODE (XEXP (base, 0)) != REG)
2536 abort ();
2537 if (small_data_operand (XEXP (base, 1), VOIDmode))
2538 fputs ("sda(", file);
2539 else
2540 fputs ("low(", file);
2541 output_addr_const (file, plus_constant (XEXP (base, 1), offset));
2542 fputs ("),", file);
2543 fputs (reg_names[REGNO (XEXP (base, 0))], file);
2544 }
2545 else
2546 fatal_insn ("bad address", addr);
2547 break;
2548
2549 case LO_SUM :
2550 if (GET_CODE (XEXP (addr, 0)) != REG)
2551 fatal_insn ("lo_sum not of register", addr);
2552 if (small_data_operand (XEXP (addr, 1), VOIDmode))
2553 fputs ("sda(", file);
2554 else
2555 fputs ("low(", file);
2556 output_addr_const (file, XEXP (addr, 1));
2557 fputs ("),", file);
2558 fputs (reg_names[REGNO (XEXP (addr, 0))], file);
2559 break;
2560
2561 case PRE_INC : /* Assume SImode */
2562 fprintf (file, "+%s", reg_names[REGNO (XEXP (addr, 0))]);
2563 break;
2564
2565 case PRE_DEC : /* Assume SImode */
2566 fprintf (file, "-%s", reg_names[REGNO (XEXP (addr, 0))]);
2567 break;
2568
2569 case POST_INC : /* Assume SImode */
2570 fprintf (file, "%s+", reg_names[REGNO (XEXP (addr, 0))]);
2571 break;
2572
2573 default :
2574 output_addr_const (file, addr);
2575 break;
2576 }
2577 }
2578
2579 /* Return true if the operands are the constants 0 and 1. */
2580 int
zero_and_one(operand1,operand2)2581 zero_and_one (operand1, operand2)
2582 rtx operand1;
2583 rtx operand2;
2584 {
2585 return
2586 GET_CODE (operand1) == CONST_INT
2587 && GET_CODE (operand2) == CONST_INT
2588 && ( ((INTVAL (operand1) == 0) && (INTVAL (operand2) == 1))
2589 ||((INTVAL (operand1) == 1) && (INTVAL (operand2) == 0)));
2590 }
2591
2592 /* Return nonzero if the operand is suitable for use in a conditional move sequence. */
2593 int
conditional_move_operand(operand,mode)2594 conditional_move_operand (operand, mode)
2595 rtx operand;
2596 enum machine_mode mode;
2597 {
2598 /* Only defined for simple integers so far... */
2599 if (mode != SImode && mode != HImode && mode != QImode)
2600 return FALSE;
2601
2602 /* At the moment we can hanndle moving registers and loading constants. */
2603 /* To be added: Addition/subtraction/bitops/multiplication of registers. */
2604
2605 switch (GET_CODE (operand))
2606 {
2607 case REG:
2608 return 1;
2609
2610 case CONST_INT:
2611 return INT8_P (INTVAL (operand));
2612
2613 default:
2614 #if 0
2615 fprintf (stderr, "Test for cond move op of type: %s\n",
2616 GET_RTX_NAME (GET_CODE (operand)));
2617 #endif
2618 return 0;
2619 }
2620 }
2621
2622 /* Return true if the code is a test of the carry bit */
2623 int
carry_compare_operand(op,mode)2624 carry_compare_operand (op, mode)
2625 rtx op;
2626 enum machine_mode mode ATTRIBUTE_UNUSED;
2627 {
2628 rtx x;
2629
2630 if (GET_MODE (op) != CCmode && GET_MODE (op) != VOIDmode)
2631 return FALSE;
2632
2633 if (GET_CODE (op) != NE && GET_CODE (op) != EQ)
2634 return FALSE;
2635
2636 x = XEXP (op, 0);
2637 if (GET_CODE (x) != REG || REGNO (x) != CARRY_REGNUM)
2638 return FALSE;
2639
2640 x = XEXP (op, 1);
2641 if (GET_CODE (x) != CONST_INT || INTVAL (x) != 0)
2642 return FALSE;
2643
2644 return TRUE;
2645 }
2646
2647 /* Generate the correct assembler code to handle the conditional loading of a
2648 value into a register. It is known that the operands satisfy the
2649 conditional_move_operand() function above. The destination is operand[0].
2650 The condition is operand [1]. The 'true' value is operand [2] and the
2651 'false' value is operand [3]. */
2652 char *
emit_cond_move(operands,insn)2653 emit_cond_move (operands, insn)
2654 rtx * operands;
2655 rtx insn ATTRIBUTE_UNUSED;
2656 {
2657 static char buffer [100];
2658 const char * dest = reg_names [REGNO (operands [0])];
2659
2660 buffer [0] = 0;
2661
2662 /* Destination must be a register. */
2663 if (GET_CODE (operands [0]) != REG)
2664 abort();
2665 if (! conditional_move_operand (operands [2], SImode))
2666 abort();
2667 if (! conditional_move_operand (operands [3], SImode))
2668 abort();
2669
2670 /* Check to see if the test is reversed. */
2671 if (GET_CODE (operands [1]) == NE)
2672 {
2673 rtx tmp = operands [2];
2674 operands [2] = operands [3];
2675 operands [3] = tmp;
2676 }
2677
2678 sprintf (buffer, "mvfc %s, cbr", dest);
2679
2680 /* If the true value was '0' then we need to invert the results of the move. */
2681 if (INTVAL (operands [2]) == 0)
2682 sprintf (buffer + strlen (buffer), "\n\txor3 %s, %s, #1",
2683 dest, dest);
2684
2685 return buffer;
2686 }
2687
2688 /* Returns true if the registers contained in the two
2689 rtl expressions are different. */
2690 int
m32r_not_same_reg(a,b)2691 m32r_not_same_reg (a, b)
2692 rtx a;
2693 rtx b;
2694 {
2695 int reg_a = -1;
2696 int reg_b = -2;
2697
2698 while (GET_CODE (a) == SUBREG)
2699 a = SUBREG_REG (a);
2700
2701 if (GET_CODE (a) == REG)
2702 reg_a = REGNO (a);
2703
2704 while (GET_CODE (b) == SUBREG)
2705 b = SUBREG_REG (b);
2706
2707 if (GET_CODE (b) == REG)
2708 reg_b = REGNO (b);
2709
2710 return reg_a != reg_b;
2711 }
2712
2713
2714 /* Use a library function to move some bytes. */
2715 static void
block_move_call(dest_reg,src_reg,bytes_rtx)2716 block_move_call (dest_reg, src_reg, bytes_rtx)
2717 rtx dest_reg;
2718 rtx src_reg;
2719 rtx bytes_rtx;
2720 {
2721 /* We want to pass the size as Pmode, which will normally be SImode
2722 but will be DImode if we are using 64 bit longs and pointers. */
2723 if (GET_MODE (bytes_rtx) != VOIDmode
2724 && GET_MODE (bytes_rtx) != Pmode)
2725 bytes_rtx = convert_to_mode (Pmode, bytes_rtx, 1);
2726
2727 #ifdef TARGET_MEM_FUNCTIONS
2728 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "memcpy"), 0,
2729 VOIDmode, 3, dest_reg, Pmode, src_reg, Pmode,
2730 convert_to_mode (TYPE_MODE (sizetype), bytes_rtx,
2731 TREE_UNSIGNED (sizetype)),
2732 TYPE_MODE (sizetype));
2733 #else
2734 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "bcopy"), 0,
2735 VOIDmode, 3, src_reg, Pmode, dest_reg, Pmode,
2736 convert_to_mode (TYPE_MODE (integer_type_node), bytes_rtx,
2737 TREE_UNSIGNED (integer_type_node)),
2738 TYPE_MODE (integer_type_node));
2739 #endif
2740 }
2741
2742 /* The maximum number of bytes to copy using pairs of load/store instructions.
2743 If a block is larger than this then a loop will be generated to copy
2744 MAX_MOVE_BYTES chunks at a time. The value of 32 is a semi-arbitary choice.
2745 A customer uses Dhrystome as their benchmark, and Dhrystone has a 31 byte
2746 string copy in it. */
2747 #define MAX_MOVE_BYTES 32
2748
2749 /* Expand string/block move operations.
2750
2751 operands[0] is the pointer to the destination.
2752 operands[1] is the pointer to the source.
2753 operands[2] is the number of bytes to move.
2754 operands[3] is the alignment. */
2755
2756 void
m32r_expand_block_move(operands)2757 m32r_expand_block_move (operands)
2758 rtx operands[];
2759 {
2760 rtx orig_dst = operands[0];
2761 rtx orig_src = operands[1];
2762 rtx bytes_rtx = operands[2];
2763 rtx align_rtx = operands[3];
2764 int constp = GET_CODE (bytes_rtx) == CONST_INT;
2765 HOST_WIDE_INT bytes = constp ? INTVAL (bytes_rtx) : 0;
2766 int align = INTVAL (align_rtx);
2767 int leftover;
2768 rtx src_reg;
2769 rtx dst_reg;
2770
2771 if (constp && bytes <= 0)
2772 return;
2773
2774 /* Move the address into scratch registers. */
2775 dst_reg = copy_addr_to_reg (XEXP (orig_dst, 0));
2776 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2777
2778 if (align > UNITS_PER_WORD)
2779 align = UNITS_PER_WORD;
2780
2781 /* If we prefer size over speed, always use a function call.
2782 If we do not know the size, use a function call.
2783 If the blocks are not word aligned, use a function call. */
2784 if (optimize_size || ! constp || align != UNITS_PER_WORD)
2785 {
2786 block_move_call (dst_reg, src_reg, bytes_rtx);
2787 return;
2788 }
2789
2790 leftover = bytes % MAX_MOVE_BYTES;
2791 bytes -= leftover;
2792
2793 /* If necessary, generate a loop to handle the bulk of the copy. */
2794 if (bytes)
2795 {
2796 rtx label = NULL_RTX;
2797 rtx final_src = NULL_RTX;
2798 rtx at_a_time = GEN_INT (MAX_MOVE_BYTES);
2799 rtx rounded_total = GEN_INT (bytes);
2800
2801 /* If we are going to have to perform this loop more than
2802 once, then generate a label and compute the address the
2803 source register will contain upon completion of the final
2804 itteration. */
2805 if (bytes > MAX_MOVE_BYTES)
2806 {
2807 final_src = gen_reg_rtx (Pmode);
2808
2809 if (INT16_P(bytes))
2810 emit_insn (gen_addsi3 (final_src, src_reg, rounded_total));
2811 else
2812 {
2813 emit_insn (gen_movsi (final_src, rounded_total));
2814 emit_insn (gen_addsi3 (final_src, final_src, src_reg));
2815 }
2816
2817 label = gen_label_rtx ();
2818 emit_label (label);
2819 }
2820
2821 /* It is known that output_block_move() will update src_reg to point
2822 to the word after the end of the source block, and dst_reg to point
2823 to the last word of the destination block, provided that the block
2824 is MAX_MOVE_BYTES long. */
2825 emit_insn (gen_movstrsi_internal (dst_reg, src_reg, at_a_time));
2826 emit_insn (gen_addsi3 (dst_reg, dst_reg, GEN_INT (4)));
2827
2828 if (bytes > MAX_MOVE_BYTES)
2829 {
2830 emit_insn (gen_cmpsi (src_reg, final_src));
2831 emit_jump_insn (gen_bne (label));
2832 }
2833 }
2834
2835 if (leftover)
2836 {
2837 HOST_WIDE_INT bytes = leftover;
2838
2839 leftover = bytes % 4;
2840 bytes -= leftover;
2841
2842 if (bytes)
2843 {
2844 emit_insn (gen_movstrsi_internal (dst_reg, src_reg, GEN_INT (bytes)));
2845 emit_insn (gen_addsi3 (dst_reg, dst_reg, GEN_INT (4)));
2846 }
2847
2848 if (leftover)
2849 emit_insn (gen_movstrsi_small_internal (dst_reg, src_reg, GEN_INT (leftover)));
2850 }
2851 }
2852
2853
2854 /* Emit load/stores for a small constant word aligned block_move.
2855
2856 operands[0] is the memory address of the destination.
2857 operands[1] is the memory address of the source.
2858 operands[2] is the number of bytes to move.
2859 operands[3] is a temp register.
2860 operands[4] is a temp register. */
2861
2862 void
m32r_output_block_move(insn,operands)2863 m32r_output_block_move (insn, operands)
2864 rtx insn ATTRIBUTE_UNUSED;
2865 rtx operands[];
2866 {
2867 HOST_WIDE_INT bytes = INTVAL (operands[2]);
2868 int first_time;
2869 int got_extra = 0;
2870
2871 if (bytes < 1 || bytes > MAX_MOVE_BYTES)
2872 abort ();
2873
2874 /* We do not have a post-increment store available, so the first set of
2875 stores are done without any increment, then the remaining ones can use
2876 the pre-increment addressing mode.
2877
2878 Note: expand_block_move() also relies upon this behavior when building
2879 loops to copy large blocks. */
2880 first_time = 1;
2881
2882 while (bytes > 0)
2883 {
2884 if (bytes >= 8)
2885 {
2886 if (first_time)
2887 {
2888 output_asm_insn ("ld\t%3, %p1", operands);
2889 output_asm_insn ("ld\t%4, %p1", operands);
2890 output_asm_insn ("st\t%3, @%0", operands);
2891 output_asm_insn ("st\t%4, %s0", operands);
2892 }
2893 else
2894 {
2895 output_asm_insn ("ld\t%3, %p1", operands);
2896 output_asm_insn ("ld\t%4, %p1", operands);
2897 output_asm_insn ("st\t%3, %s0", operands);
2898 output_asm_insn ("st\t%4, %s0", operands);
2899 }
2900
2901 bytes -= 8;
2902 }
2903 else if (bytes >= 4)
2904 {
2905 if (bytes > 4)
2906 got_extra = 1;
2907
2908 output_asm_insn ("ld\t%3, %p1", operands);
2909
2910 if (got_extra)
2911 output_asm_insn ("ld\t%4, %p1", operands);
2912
2913 if (first_time)
2914 output_asm_insn ("st\t%3, @%0", operands);
2915 else
2916 output_asm_insn ("st\t%3, %s0", operands);
2917
2918 bytes -= 4;
2919 }
2920 else
2921 {
2922 /* Get the entire next word, even though we do not want all of it.
2923 The saves us from doing several smaller loads, and we assume that
2924 we cannot cause a page fault when at least part of the word is in
2925 valid memory [since we don't get called if things aren't properly
2926 aligned]. */
2927 int dst_offset = first_time ? 0 : 4;
2928 int last_shift;
2929 rtx my_operands[3];
2930
2931 /* If got_extra is true then we have already loaded
2932 the next word as part of loading and storing the previous word. */
2933 if (! got_extra)
2934 output_asm_insn ("ld\t%4, @%1", operands);
2935
2936 if (bytes >= 2)
2937 {
2938 bytes -= 2;
2939
2940 output_asm_insn ("sra3\t%3, %4, #16", operands);
2941 my_operands[0] = operands[3];
2942 my_operands[1] = GEN_INT (dst_offset);
2943 my_operands[2] = operands[0];
2944 output_asm_insn ("sth\t%0, @(%1,%2)", my_operands);
2945
2946 /* If there is a byte left to store then increment the
2947 destination address and shift the contents of the source
2948 register down by 8 bits. We could not do the address
2949 increment in the store half word instruction, because it does
2950 not have an auto increment mode. */
2951 if (bytes > 0) /* assert (bytes == 1) */
2952 {
2953 dst_offset += 2;
2954 last_shift = 8;
2955 }
2956 }
2957 else
2958 last_shift = 24;
2959
2960 if (bytes > 0)
2961 {
2962 my_operands[0] = operands[4];
2963 my_operands[1] = GEN_INT (last_shift);
2964 output_asm_insn ("srai\t%0, #%1", my_operands);
2965 my_operands[0] = operands[4];
2966 my_operands[1] = GEN_INT (dst_offset);
2967 my_operands[2] = operands[0];
2968 output_asm_insn ("stb\t%0, @(%1,%2)", my_operands);
2969 }
2970
2971 bytes = 0;
2972 }
2973
2974 first_time = 0;
2975 }
2976 }
2977
2978 /* Return true if op is an integer constant, less than or equal to
2979 MAX_MOVE_BYTES. */
2980
2981 int
m32r_block_immediate_operand(op,mode)2982 m32r_block_immediate_operand (op, mode)
2983 rtx op;
2984 enum machine_mode mode ATTRIBUTE_UNUSED;
2985 {
2986 if (GET_CODE (op) != CONST_INT
2987 || INTVAL (op) > MAX_MOVE_BYTES
2988 || INTVAL (op) <= 0)
2989 return 0;
2990
2991 return 1;
2992 }
2993
2994 int
m32r_block_small_immediate_operand(op,mode)2995 m32r_block_small_immediate_operand (op, mode)
2996 rtx op;
2997 enum machine_mode mode ATTRIBUTE_UNUSED;
2998 {
2999 if (GET_CODE (op) != CONST_INT
3000 || INTVAL (op) > 4
3001 || INTVAL (op) <= 0)
3002 return 0;
3003
3004 return 1;
3005 }
3006