| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dmub/src/ |
| H A D | dmub_reg.h | 39 #define REG_OFFSET(reg_name) (BASE(mm##reg_name##_BASE_IDX) + mm##reg_name) argument
41 #define FD_SHIFT(reg_name, field) reg_name##__##field##__SHIFT argument
43 #define FD_MASK(reg_name, field) reg_name##__##field##_MASK argument
49 #define FN(reg_name, field) FD(reg_name##__##field) argument
60 #define REG_SET_N(reg_name, n, initial_val, ...) \ argument
63 #define REG_SET(reg_name, initial_val, field, val) \ argument
87 #define REG_UPDATE_N(reg_name, n, ...)\ argument
90 #define REG_UPDATE(reg_name, field, val) \ argument
114 #define REG_GET(reg_name, field, val) \ argument
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dcn20/ |
| H A D | amdgpu_hw_factory_dcn20.c | 64 #define REG(reg_name)\ argument
67 #define SF_HPD(reg_name, field_name, post_fix)\ argument
70 #define REGI(reg_name, block, id)\ argument
74 #define SF(reg_name, field_name, post_fix)\ argument
107 #define SF_DDC(reg_name, field_name, post_fix)\ argument
161 #define SF_GENERIC(reg_name, field_name, post_fix)\ argument
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| H A D | amdgpu_hw_translate_dcn20.c | 60 #define REG(reg_name)\ argument
62 #define SF_HPD(reg_name, field_name, post_fix)\ argument
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dcn21/ |
| H A D | amdgpu_hw_factory_dcn21.c | 62 #define REG(reg_name)\ argument
65 #define SF_HPD(reg_name, field_name, post_fix)\ argument
68 #define REGI(reg_name, block, id)\ argument
72 #define SF(reg_name, field_name, post_fix)\ argument
104 #define SF_DDC(reg_name, field_name, post_fix)\ argument
144 #define SF_GENERIC(reg_name, field_name, post_fix)\ argument
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| H A D | amdgpu_hw_translate_dcn21.c | 60 #define REG(reg_name)\ argument
62 #define SF_HPD(reg_name, field_name, post_fix)\ argument
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| H A D | dcn20_mmhubbub.h | 41 #define SR(reg_name)\ argument
45 #define SRI(reg_name, block, id)\ argument
49 #define SRI2(reg_name, block, id)\ argument
53 #define SRII(reg_name, block, id)\ argument
57 #define SF(reg_name, field_name, post_fix)\ argument
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| H A D | amdgpu_dcn20_link_encoder.c | 51 #define FN(reg_name, field_name) \ argument
271 #define AUX_REG_READ(reg_name) \ argument
274 #define AUX_REG_WRITE(reg_name, val) \ argument
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| H A D | dcn20_vmid.h | 39 #define SRI(reg_name, block, id)\ argument
43 #define SF(reg_name, field_name, post_fix)\ argument
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| H A D | dcn20_dwb.h | 39 #define SR(reg_name)\ argument
43 #define SRI(reg_name, block, id)\ argument
47 #define SRI2(reg_name, block, id)\ argument
51 #define SRII(reg_name, block, id)\ argument
55 #define SF(reg_name, field_name, post_fix)\ argument
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| H A D | dcn20_dccg.h | 46 #define DCCG_SF(reg_name, field_name, post_fix)\ argument
49 #define DCCG_SFI(reg_name, field_name, field_prefix, inst, post_fix)\ argument
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dce120/ |
| H A D | amdgpu_hw_factory_dce120.c | 51 #define SF_HPD(reg_name, field_name, post_fix)\ argument
55 #define SF_HPD(reg_name, field_name, post_fix)\ argument
65 #define REG(reg_name)\ argument
68 #define REGI(reg_name, block, id)\ argument
101 #define SF_DDC(reg_name, field_name, post_fix)\ argument
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| H A D | amdgpu_hw_translate_dce120.c | 56 #define REG(reg_name)\ argument
59 #define REGI(reg_name, block, id)\ argument
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dce110/ |
| H A D | amdgpu_hw_factory_dce110.c | 47 #define SF_HPD(reg_name, field_name, post_fix)\ argument
50 #define REG(reg_name)\ argument
53 #define REGI(reg_name, block, id)\ argument
88 #define SF_DDC(reg_name, field_name, post_fix)\ argument
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dcn10/ |
| H A D | amdgpu_hw_factory_dcn10.c | 52 #define SF_HPD(reg_name, field_name, post_fix)\ argument
62 #define REG(reg_name)\ argument
65 #define REGI(reg_name, block, id)\ argument
97 #define SF_DDC(reg_name, field_name, post_fix)\ argument
133 #define SF_GENERIC(reg_name, field_name, post_fix)\ argument
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| H A D | amdgpu_hw_translate_dcn10.c | 56 #define REG(reg_name)\ argument
59 #define REGI(reg_name, block, id)\ argument
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/ |
| H A D | dm_services.h | 116 #define get_reg_field_value(reg_value, reg_name, reg_field)\ argument
132 #define set_reg_field_value(reg_value, value, reg_name, reg_field)\ argument
177 #define generic_reg_update_soc15(ctx, inst_offset, reg_name, n, ...)\ argument
181 #define generic_reg_set_soc15(ctx, inst_offset, reg_name, n, ...)\ argument
185 #define get_reg_field_value_soc15(reg_value, block, reg_num, reg_name, reg_field)\ argument
191 #define set_reg_field_value_soc15(reg_value, value, block, reg_num, reg_name, reg_field)\ argument
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn10/ |
| H A D | rv1_clk_mgr_clk.c | 48 #define CLK_REG(reg_name, block, inst)\ argument
52 #define REG(reg_name) \ argument
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| H A D | amdgpu_rv1_clk_mgr_vbios_smu.c | 67 #define REG(reg_name) \ argument
70 #define FN(reg_name, field) \ argument
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dce80/ |
| H A D | amdgpu_hw_factory_dce80.c | 46 #define REG(reg_name)\ argument
88 #define SF_DDC(reg_name, field_name, post_fix)\ argument
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| /netbsd-src/sys/arch/mips/mips/ |
| H A D | db_disasm.c | 174 static const char * const reg_name[32] = { variable
181 static const char * const reg_name[32] = { variable
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| H A D | dcn10_dwb.h | 38 #define SR(reg_name)\ argument
42 #define SRI(reg_name, block, id)\ argument
47 #define SRII(reg_name, block, id)\ argument
51 #define SF(reg_name, field_name, post_fix)\ argument
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| /netbsd-src/external/gpl3/binutils.old/dist/gas/config/ |
| H A D | tc-cr16.c | 328 get_register (char *reg_name) in get_register()
342 get_register_pair (char *reg_name) in get_register_pair()
367 get_index_register (char *reg_name) in get_index_register()
382 get_index_register_pair (char *reg_name) in get_index_register_pair()
1098 char *reg_name; in getreg_image() local
1569 char *reg_name; in getregp_image() local
1608 char *reg_name; in getidxregp_image() local
1655 char *reg_name; in getprocreg_image() local
1693 char *reg_name; in getprocregp_image() local
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| /netbsd-src/external/gpl3/binutils/dist/gas/config/ |
| H A D | tc-cr16.c | 328 get_register (char *reg_name) in get_register()
342 get_register_pair (char *reg_name) in get_register_pair()
367 get_index_register (char *reg_name) in get_index_register()
382 get_index_register_pair (char *reg_name) in get_index_register_pair()
1098 char *reg_name; in getreg_image() local
1569 char *reg_name; in getregp_image() local
1608 char *reg_name; in getidxregp_image() local
1655 char *reg_name; in getprocreg_image() local
1693 char *reg_name; in getprocregp_image() local
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/ |
| H A D | reg_helper.h | 41 #define REG_READ(reg_name) \ argument
44 #define REG_WRITE(reg_name, value) \ argument
56 #define REG_SET_N(reg_name, n, initial_val, ...) \ argument
62 #define FN(reg_name, field) \ argument
65 #define REG_SET(reg_name, initial_val, field, val) \ argument
158 #define REG_GET(reg_name, field, val) \ argument
162 #define REG_GET_2(reg_name, f1, v1, f2, v2) \ argument
167 #define REG_GET_3(reg_name, f1, v1, f2, v2, f3, v3) \ argument
173 #define REG_GET_4(reg_name, f1, v1, f2, v2, f3, v3, f4, v4) \ argument
180 #define REG_GET_5(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ argument
[all …]
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce112/ |
| H A D | amdgpu_dce112_clk_mgr.c | 42 #define SR(reg_name)\ argument
46 #define SRI(reg_name, block, id)\ argument
|