1 //===-- AMDGPUPALMetadata.cpp - Accumulate and print AMDGPU PAL metadata -===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 /// \file 10 /// 11 /// This class has methods called by AMDGPUAsmPrinter to accumulate and print 12 /// the PAL metadata. 13 // 14 //===----------------------------------------------------------------------===// 15 // 16 17 #include "AMDGPUPALMetadata.h" 18 #include "AMDGPUPTNote.h" 19 #include "SIDefines.h" 20 #include "llvm/BinaryFormat/ELF.h" 21 #include "llvm/IR/Constants.h" 22 #include "llvm/IR/Module.h" 23 #include "llvm/MC/MCExpr.h" 24 #include "llvm/Support/AMDGPUMetadata.h" 25 #include "llvm/Support/EndianStream.h" 26 27 using namespace llvm; 28 using namespace llvm::AMDGPU; 29 30 // Read the PAL metadata from IR metadata, where it was put by the frontend. 31 void AMDGPUPALMetadata::readFromIR(Module &M) { 32 auto *NamedMD = M.getNamedMetadata("amdgpu.pal.metadata.msgpack"); 33 if (NamedMD && NamedMD->getNumOperands()) { 34 // This is the new msgpack format for metadata. It is a NamedMD containing 35 // an MDTuple containing an MDString containing the msgpack data. 36 BlobType = ELF::NT_AMDGPU_METADATA; 37 auto *MDN = dyn_cast<MDTuple>(NamedMD->getOperand(0)); 38 if (MDN && MDN->getNumOperands()) { 39 if (auto *MDS = dyn_cast<MDString>(MDN->getOperand(0))) 40 setFromMsgPackBlob(MDS->getString()); 41 } 42 return; 43 } 44 BlobType = ELF::NT_AMD_PAL_METADATA; 45 NamedMD = M.getNamedMetadata("amdgpu.pal.metadata"); 46 if (!NamedMD || !NamedMD->getNumOperands()) { 47 // Emit msgpack metadata by default 48 BlobType = ELF::NT_AMDGPU_METADATA; 49 return; 50 } 51 // This is the old reg=value pair format for metadata. It is a NamedMD 52 // containing an MDTuple containing a number of MDNodes each of which is an 53 // integer value, and each two integer values forms a key=value pair that we 54 // store as Registers[key]=value in the map. 55 auto *Tuple = dyn_cast<MDTuple>(NamedMD->getOperand(0)); 56 if (!Tuple) 57 return; 58 for (unsigned I = 0, E = Tuple->getNumOperands() & -2; I != E; I += 2) { 59 auto *Key = mdconst::dyn_extract<ConstantInt>(Tuple->getOperand(I)); 60 auto *Val = mdconst::dyn_extract<ConstantInt>(Tuple->getOperand(I + 1)); 61 if (!Key || !Val) 62 continue; 63 setRegister(Key->getZExtValue(), Val->getZExtValue()); 64 } 65 } 66 67 // Set PAL metadata from a binary blob from the applicable .note record. 68 // Returns false if bad format. Blob must remain valid for the lifetime of the 69 // Metadata. 70 bool AMDGPUPALMetadata::setFromBlob(unsigned Type, StringRef Blob) { 71 BlobType = Type; 72 if (Type == ELF::NT_AMD_PAL_METADATA) 73 return setFromLegacyBlob(Blob); 74 return setFromMsgPackBlob(Blob); 75 } 76 77 // Set PAL metadata from legacy (array of key=value pairs) blob. 78 bool AMDGPUPALMetadata::setFromLegacyBlob(StringRef Blob) { 79 const auto *Data = reinterpret_cast<const uint32_t *>(Blob.data()); 80 for (unsigned I = 0; I != Blob.size() / sizeof(uint32_t) / 2; ++I) 81 setRegister(Data[I * 2], Data[I * 2 + 1]); 82 return true; 83 } 84 85 // Set PAL metadata from msgpack blob. 86 bool AMDGPUPALMetadata::setFromMsgPackBlob(StringRef Blob) { 87 return MsgPackDoc.readFromBlob(Blob, /*Multi=*/false); 88 } 89 90 // Given the calling convention, calculate the register number for rsrc1. In 91 // principle the register number could change in future hardware, but we know 92 // it is the same for gfx6-9 (except that LS and ES don't exist on gfx9), so 93 // we can use fixed values. 94 static unsigned getRsrc1Reg(CallingConv::ID CC) { 95 switch (CC) { 96 default: 97 return PALMD::R_2E12_COMPUTE_PGM_RSRC1; 98 case CallingConv::AMDGPU_LS: 99 return PALMD::R_2D4A_SPI_SHADER_PGM_RSRC1_LS; 100 case CallingConv::AMDGPU_HS: 101 return PALMD::R_2D0A_SPI_SHADER_PGM_RSRC1_HS; 102 case CallingConv::AMDGPU_ES: 103 return PALMD::R_2CCA_SPI_SHADER_PGM_RSRC1_ES; 104 case CallingConv::AMDGPU_GS: 105 return PALMD::R_2C8A_SPI_SHADER_PGM_RSRC1_GS; 106 case CallingConv::AMDGPU_VS: 107 return PALMD::R_2C4A_SPI_SHADER_PGM_RSRC1_VS; 108 case CallingConv::AMDGPU_PS: 109 return PALMD::R_2C0A_SPI_SHADER_PGM_RSRC1_PS; 110 } 111 } 112 113 // Calculate the PAL metadata key for *S_SCRATCH_SIZE. It can be used 114 // with a constant offset to access any non-register shader-specific PAL 115 // metadata key. 116 static unsigned getScratchSizeKey(CallingConv::ID CC) { 117 switch (CC) { 118 case CallingConv::AMDGPU_PS: 119 return PALMD::Key::PS_SCRATCH_SIZE; 120 case CallingConv::AMDGPU_VS: 121 return PALMD::Key::VS_SCRATCH_SIZE; 122 case CallingConv::AMDGPU_GS: 123 return PALMD::Key::GS_SCRATCH_SIZE; 124 case CallingConv::AMDGPU_ES: 125 return PALMD::Key::ES_SCRATCH_SIZE; 126 case CallingConv::AMDGPU_HS: 127 return PALMD::Key::HS_SCRATCH_SIZE; 128 case CallingConv::AMDGPU_LS: 129 return PALMD::Key::LS_SCRATCH_SIZE; 130 default: 131 return PALMD::Key::CS_SCRATCH_SIZE; 132 } 133 } 134 135 // Set the rsrc1 register in the metadata for a particular shader stage. 136 // In fact this ORs the value into any previous setting of the register. 137 void AMDGPUPALMetadata::setRsrc1(CallingConv::ID CC, unsigned Val) { 138 setRegister(getRsrc1Reg(CC), Val); 139 } 140 141 void AMDGPUPALMetadata::setRsrc1(CallingConv::ID CC, const MCExpr *Val, 142 MCContext &Ctx) { 143 setRegister(getRsrc1Reg(CC), Val, Ctx); 144 } 145 146 // Set the rsrc2 register in the metadata for a particular shader stage. 147 // In fact this ORs the value into any previous setting of the register. 148 void AMDGPUPALMetadata::setRsrc2(CallingConv::ID CC, unsigned Val) { 149 setRegister(getRsrc1Reg(CC) + 1, Val); 150 } 151 152 void AMDGPUPALMetadata::setRsrc2(CallingConv::ID CC, const MCExpr *Val, 153 MCContext &Ctx) { 154 setRegister(getRsrc1Reg(CC) + 1, Val, Ctx); 155 } 156 157 // Set the SPI_PS_INPUT_ENA register in the metadata. 158 // In fact this ORs the value into any previous setting of the register. 159 void AMDGPUPALMetadata::setSpiPsInputEna(unsigned Val) { 160 setRegister(PALMD::R_A1B3_SPI_PS_INPUT_ENA, Val); 161 } 162 163 // Set the SPI_PS_INPUT_ADDR register in the metadata. 164 // In fact this ORs the value into any previous setting of the register. 165 void AMDGPUPALMetadata::setSpiPsInputAddr(unsigned Val) { 166 setRegister(PALMD::R_A1B4_SPI_PS_INPUT_ADDR, Val); 167 } 168 169 // Get a register from the metadata, or 0 if not currently set. 170 unsigned AMDGPUPALMetadata::getRegister(unsigned Reg) { 171 auto Regs = getRegisters(); 172 auto It = Regs.find(MsgPackDoc.getNode(Reg)); 173 if (It == Regs.end()) 174 return 0; 175 auto N = It->second; 176 if (N.getKind() != msgpack::Type::UInt) 177 return 0; 178 return N.getUInt(); 179 } 180 181 // Set a register in the metadata. 182 // In fact this ORs the value into any previous setting of the register. 183 void AMDGPUPALMetadata::setRegister(unsigned Reg, unsigned Val) { 184 if (!isLegacy()) { 185 // In the new MsgPack format, ignore register numbered >= 0x10000000. It 186 // is a PAL ABI pseudo-register in the old non-MsgPack format. 187 if (Reg >= 0x10000000) 188 return; 189 } 190 auto &N = getRegisters()[MsgPackDoc.getNode(Reg)]; 191 if (N.getKind() == msgpack::Type::UInt) 192 Val |= N.getUInt(); 193 N = N.getDocument()->getNode(Val); 194 } 195 196 // Set a register in the metadata. 197 // In fact this ORs the value into any previous setting of the register. 198 void AMDGPUPALMetadata::setRegister(unsigned Reg, const MCExpr *Val, 199 MCContext &Ctx) { 200 if (!isLegacy()) { 201 // In the new MsgPack format, ignore register numbered >= 0x10000000. It 202 // is a PAL ABI pseudo-register in the old non-MsgPack format. 203 if (Reg >= 0x10000000) 204 return; 205 } 206 auto &N = getRegisters()[MsgPackDoc.getNode(Reg)]; 207 auto ExprIt = REM.find(Reg); 208 209 if (ExprIt != REM.end()) { 210 Val = MCBinaryExpr::createOr(Val, ExprIt->getSecond(), Ctx); 211 // This conditional may be redundant most of the time, but the alternate 212 // setRegister(unsigned, unsigned) could've been called while the 213 // conditional returns true (i.e., Reg exists in REM). 214 if (N.getKind() == msgpack::Type::UInt) { 215 const MCExpr *NExpr = MCConstantExpr::create(N.getUInt(), Ctx); 216 Val = MCBinaryExpr::createOr(Val, NExpr, Ctx); 217 } 218 } else if (N.getKind() == msgpack::Type::UInt) { 219 const MCExpr *NExpr = MCConstantExpr::create(N.getUInt(), Ctx); 220 Val = MCBinaryExpr::createOr(Val, NExpr, Ctx); 221 } else { 222 // Default to uint64_t 0 so additional calls to setRegister will allow 223 // propagate ORs. 224 N = (uint64_t)0; 225 } 226 REM[Reg] = Val; 227 DelayedExprs.assignDocNode(N, msgpack::Type::UInt, Val); 228 } 229 230 // Set the entry point name for one shader. 231 void AMDGPUPALMetadata::setEntryPoint(unsigned CC, StringRef Name) { 232 if (isLegacy()) 233 return; 234 // Msgpack format. 235 getHwStage(CC)[".entry_point_symbol"] = 236 MsgPackDoc.getNode(Name, /*Copy=*/true); 237 } 238 239 // Set the number of used vgprs in the metadata. This is an optional 240 // advisory record for logging etc; wave dispatch actually uses the rsrc1 241 // register for the shader stage to determine the number of vgprs to 242 // allocate. 243 void AMDGPUPALMetadata::setNumUsedVgprs(CallingConv::ID CC, unsigned Val) { 244 if (isLegacy()) { 245 // Old non-msgpack format. 246 unsigned NumUsedVgprsKey = getScratchSizeKey(CC) + 247 PALMD::Key::VS_NUM_USED_VGPRS - 248 PALMD::Key::VS_SCRATCH_SIZE; 249 setRegister(NumUsedVgprsKey, Val); 250 return; 251 } 252 // Msgpack format. 253 getHwStage(CC)[".vgpr_count"] = MsgPackDoc.getNode(Val); 254 } 255 256 void AMDGPUPALMetadata::setNumUsedVgprs(CallingConv::ID CC, const MCExpr *Val, 257 MCContext &Ctx) { 258 if (isLegacy()) { 259 // Old non-msgpack format. 260 unsigned NumUsedVgprsKey = getScratchSizeKey(CC) + 261 PALMD::Key::VS_NUM_USED_VGPRS - 262 PALMD::Key::VS_SCRATCH_SIZE; 263 setRegister(NumUsedVgprsKey, Val, Ctx); 264 return; 265 } 266 // Msgpack format. 267 setHwStage(CC, ".vgpr_count", msgpack::Type::UInt, Val); 268 } 269 270 // Set the number of used agprs in the metadata. 271 void AMDGPUPALMetadata::setNumUsedAgprs(CallingConv::ID CC, unsigned Val) { 272 getHwStage(CC)[".agpr_count"] = Val; 273 } 274 275 void AMDGPUPALMetadata::setNumUsedAgprs(unsigned CC, const MCExpr *Val) { 276 setHwStage(CC, ".agpr_count", msgpack::Type::UInt, Val); 277 } 278 279 // Set the number of used sgprs in the metadata. This is an optional advisory 280 // record for logging etc; wave dispatch actually uses the rsrc1 register for 281 // the shader stage to determine the number of sgprs to allocate. 282 void AMDGPUPALMetadata::setNumUsedSgprs(CallingConv::ID CC, unsigned Val) { 283 if (isLegacy()) { 284 // Old non-msgpack format. 285 unsigned NumUsedSgprsKey = getScratchSizeKey(CC) + 286 PALMD::Key::VS_NUM_USED_SGPRS - 287 PALMD::Key::VS_SCRATCH_SIZE; 288 setRegister(NumUsedSgprsKey, Val); 289 return; 290 } 291 // Msgpack format. 292 getHwStage(CC)[".sgpr_count"] = MsgPackDoc.getNode(Val); 293 } 294 295 void AMDGPUPALMetadata::setNumUsedSgprs(unsigned CC, const MCExpr *Val, 296 MCContext &Ctx) { 297 if (isLegacy()) { 298 // Old non-msgpack format. 299 unsigned NumUsedSgprsKey = getScratchSizeKey(CC) + 300 PALMD::Key::VS_NUM_USED_SGPRS - 301 PALMD::Key::VS_SCRATCH_SIZE; 302 setRegister(NumUsedSgprsKey, Val, Ctx); 303 return; 304 } 305 // Msgpack format. 306 setHwStage(CC, ".sgpr_count", msgpack::Type::UInt, Val); 307 } 308 309 // Set the scratch size in the metadata. 310 void AMDGPUPALMetadata::setScratchSize(CallingConv::ID CC, unsigned Val) { 311 if (isLegacy()) { 312 // Old non-msgpack format. 313 setRegister(getScratchSizeKey(CC), Val); 314 return; 315 } 316 // Msgpack format. 317 getHwStage(CC)[".scratch_memory_size"] = MsgPackDoc.getNode(Val); 318 } 319 320 void AMDGPUPALMetadata::setScratchSize(unsigned CC, const MCExpr *Val, 321 MCContext &Ctx) { 322 if (isLegacy()) { 323 // Old non-msgpack format. 324 setRegister(getScratchSizeKey(CC), Val, Ctx); 325 return; 326 } 327 // Msgpack format. 328 setHwStage(CC, ".scratch_memory_size", msgpack::Type::UInt, Val); 329 } 330 331 // Set the stack frame size of a function in the metadata. 332 void AMDGPUPALMetadata::setFunctionScratchSize(StringRef FnName, unsigned Val) { 333 auto Node = getShaderFunction(FnName); 334 Node[".stack_frame_size_in_bytes"] = MsgPackDoc.getNode(Val); 335 Node[".backend_stack_size"] = MsgPackDoc.getNode(Val); 336 } 337 338 // Set the amount of LDS used in bytes in the metadata. 339 void AMDGPUPALMetadata::setFunctionLdsSize(StringRef FnName, unsigned Val) { 340 auto Node = getShaderFunction(FnName); 341 Node[".lds_size"] = MsgPackDoc.getNode(Val); 342 } 343 344 // Set the number of used vgprs in the metadata. 345 void AMDGPUPALMetadata::setFunctionNumUsedVgprs(StringRef FnName, 346 unsigned Val) { 347 auto Node = getShaderFunction(FnName); 348 Node[".vgpr_count"] = MsgPackDoc.getNode(Val); 349 } 350 351 void AMDGPUPALMetadata::setFunctionNumUsedVgprs(StringRef FnName, 352 const MCExpr *Val) { 353 auto Node = getShaderFunction(FnName); 354 DelayedExprs.assignDocNode(Node[".vgpr_count"], msgpack::Type::UInt, Val); 355 } 356 357 // Set the number of used vgprs in the metadata. 358 void AMDGPUPALMetadata::setFunctionNumUsedSgprs(StringRef FnName, 359 unsigned Val) { 360 auto Node = getShaderFunction(FnName); 361 Node[".sgpr_count"] = MsgPackDoc.getNode(Val); 362 } 363 364 void AMDGPUPALMetadata::setFunctionNumUsedSgprs(StringRef FnName, 365 const MCExpr *Val) { 366 auto Node = getShaderFunction(FnName); 367 DelayedExprs.assignDocNode(Node[".sgpr_count"], msgpack::Type::UInt, Val); 368 } 369 370 // Set the hardware register bit in PAL metadata to enable wave32 on the 371 // shader of the given calling convention. 372 void AMDGPUPALMetadata::setWave32(unsigned CC) { 373 switch (CC) { 374 case CallingConv::AMDGPU_HS: 375 setRegister(PALMD::R_A2D5_VGT_SHADER_STAGES_EN, S_028B54_HS_W32_EN(1)); 376 break; 377 case CallingConv::AMDGPU_GS: 378 setRegister(PALMD::R_A2D5_VGT_SHADER_STAGES_EN, S_028B54_GS_W32_EN(1)); 379 break; 380 case CallingConv::AMDGPU_VS: 381 setRegister(PALMD::R_A2D5_VGT_SHADER_STAGES_EN, S_028B54_VS_W32_EN(1)); 382 break; 383 case CallingConv::AMDGPU_PS: 384 setRegister(PALMD::R_A1B6_SPI_PS_IN_CONTROL, S_0286D8_PS_W32_EN(1)); 385 break; 386 case CallingConv::AMDGPU_CS: 387 setRegister(PALMD::R_2E00_COMPUTE_DISPATCH_INITIATOR, 388 S_00B800_CS_W32_EN(1)); 389 break; 390 } 391 } 392 393 // Convert a register number to name, for display by toString(). 394 // Returns nullptr if none. 395 static const char *getRegisterName(unsigned RegNum) { 396 // Table of registers. 397 static const struct RegInfo { 398 unsigned Num; 399 const char *Name; 400 } RegInfoTable[] = { 401 // Registers that code generation sets/modifies metadata for. 402 {PALMD::R_2C4A_SPI_SHADER_PGM_RSRC1_VS, "SPI_SHADER_PGM_RSRC1_VS"}, 403 {PALMD::R_2C4A_SPI_SHADER_PGM_RSRC1_VS + 1, "SPI_SHADER_PGM_RSRC2_VS"}, 404 {PALMD::R_2D4A_SPI_SHADER_PGM_RSRC1_LS, "SPI_SHADER_PGM_RSRC1_LS"}, 405 {PALMD::R_2D4A_SPI_SHADER_PGM_RSRC1_LS + 1, "SPI_SHADER_PGM_RSRC2_LS"}, 406 {PALMD::R_2D0A_SPI_SHADER_PGM_RSRC1_HS, "SPI_SHADER_PGM_RSRC1_HS"}, 407 {PALMD::R_2D0A_SPI_SHADER_PGM_RSRC1_HS + 1, "SPI_SHADER_PGM_RSRC2_HS"}, 408 {PALMD::R_2CCA_SPI_SHADER_PGM_RSRC1_ES, "SPI_SHADER_PGM_RSRC1_ES"}, 409 {PALMD::R_2CCA_SPI_SHADER_PGM_RSRC1_ES + 1, "SPI_SHADER_PGM_RSRC2_ES"}, 410 {PALMD::R_2C8A_SPI_SHADER_PGM_RSRC1_GS, "SPI_SHADER_PGM_RSRC1_GS"}, 411 {PALMD::R_2C8A_SPI_SHADER_PGM_RSRC1_GS + 1, "SPI_SHADER_PGM_RSRC2_GS"}, 412 {PALMD::R_2E00_COMPUTE_DISPATCH_INITIATOR, "COMPUTE_DISPATCH_INITIATOR"}, 413 {PALMD::R_2E12_COMPUTE_PGM_RSRC1, "COMPUTE_PGM_RSRC1"}, 414 {PALMD::R_2E12_COMPUTE_PGM_RSRC1 + 1, "COMPUTE_PGM_RSRC2"}, 415 {PALMD::R_2C0A_SPI_SHADER_PGM_RSRC1_PS, "SPI_SHADER_PGM_RSRC1_PS"}, 416 {PALMD::R_2C0A_SPI_SHADER_PGM_RSRC1_PS + 1, "SPI_SHADER_PGM_RSRC2_PS"}, 417 {PALMD::R_A1B3_SPI_PS_INPUT_ENA, "SPI_PS_INPUT_ENA"}, 418 {PALMD::R_A1B4_SPI_PS_INPUT_ADDR, "SPI_PS_INPUT_ADDR"}, 419 {PALMD::R_A1B6_SPI_PS_IN_CONTROL, "SPI_PS_IN_CONTROL"}, 420 {PALMD::R_A2D5_VGT_SHADER_STAGES_EN, "VGT_SHADER_STAGES_EN"}, 421 422 // Registers not known to code generation. 423 {0x2c07, "SPI_SHADER_PGM_RSRC3_PS"}, 424 {0x2c46, "SPI_SHADER_PGM_RSRC3_VS"}, 425 {0x2c87, "SPI_SHADER_PGM_RSRC3_GS"}, 426 {0x2cc7, "SPI_SHADER_PGM_RSRC3_ES"}, 427 {0x2d07, "SPI_SHADER_PGM_RSRC3_HS"}, 428 {0x2d47, "SPI_SHADER_PGM_RSRC3_LS"}, 429 430 {0xa1c3, "SPI_SHADER_POS_FORMAT"}, 431 {0xa1b1, "SPI_VS_OUT_CONFIG"}, 432 {0xa207, "PA_CL_VS_OUT_CNTL"}, 433 {0xa204, "PA_CL_CLIP_CNTL"}, 434 {0xa206, "PA_CL_VTE_CNTL"}, 435 {0xa2f9, "PA_SU_VTX_CNTL"}, 436 {0xa293, "PA_SC_MODE_CNTL_1"}, 437 {0xa2a1, "VGT_PRIMITIVEID_EN"}, 438 {0x2c81, "SPI_SHADER_PGM_RSRC4_GS"}, 439 {0x2e18, "COMPUTE_TMPRING_SIZE"}, 440 {0xa1b5, "SPI_INTERP_CONTROL_0"}, 441 {0xa1ba, "SPI_TMPRING_SIZE"}, 442 {0xa1c4, "SPI_SHADER_Z_FORMAT"}, 443 {0xa1c5, "SPI_SHADER_COL_FORMAT"}, 444 {0xa203, "DB_SHADER_CONTROL"}, 445 {0xa08f, "CB_SHADER_MASK"}, 446 {0xa191, "SPI_PS_INPUT_CNTL_0"}, 447 {0xa192, "SPI_PS_INPUT_CNTL_1"}, 448 {0xa193, "SPI_PS_INPUT_CNTL_2"}, 449 {0xa194, "SPI_PS_INPUT_CNTL_3"}, 450 {0xa195, "SPI_PS_INPUT_CNTL_4"}, 451 {0xa196, "SPI_PS_INPUT_CNTL_5"}, 452 {0xa197, "SPI_PS_INPUT_CNTL_6"}, 453 {0xa198, "SPI_PS_INPUT_CNTL_7"}, 454 {0xa199, "SPI_PS_INPUT_CNTL_8"}, 455 {0xa19a, "SPI_PS_INPUT_CNTL_9"}, 456 {0xa19b, "SPI_PS_INPUT_CNTL_10"}, 457 {0xa19c, "SPI_PS_INPUT_CNTL_11"}, 458 {0xa19d, "SPI_PS_INPUT_CNTL_12"}, 459 {0xa19e, "SPI_PS_INPUT_CNTL_13"}, 460 {0xa19f, "SPI_PS_INPUT_CNTL_14"}, 461 {0xa1a0, "SPI_PS_INPUT_CNTL_15"}, 462 {0xa1a1, "SPI_PS_INPUT_CNTL_16"}, 463 {0xa1a2, "SPI_PS_INPUT_CNTL_17"}, 464 {0xa1a3, "SPI_PS_INPUT_CNTL_18"}, 465 {0xa1a4, "SPI_PS_INPUT_CNTL_19"}, 466 {0xa1a5, "SPI_PS_INPUT_CNTL_20"}, 467 {0xa1a6, "SPI_PS_INPUT_CNTL_21"}, 468 {0xa1a7, "SPI_PS_INPUT_CNTL_22"}, 469 {0xa1a8, "SPI_PS_INPUT_CNTL_23"}, 470 {0xa1a9, "SPI_PS_INPUT_CNTL_24"}, 471 {0xa1aa, "SPI_PS_INPUT_CNTL_25"}, 472 {0xa1ab, "SPI_PS_INPUT_CNTL_26"}, 473 {0xa1ac, "SPI_PS_INPUT_CNTL_27"}, 474 {0xa1ad, "SPI_PS_INPUT_CNTL_28"}, 475 {0xa1ae, "SPI_PS_INPUT_CNTL_29"}, 476 {0xa1af, "SPI_PS_INPUT_CNTL_30"}, 477 {0xa1b0, "SPI_PS_INPUT_CNTL_31"}, 478 479 {0xa2ce, "VGT_GS_MAX_VERT_OUT"}, 480 {0xa2ab, "VGT_ESGS_RING_ITEMSIZE"}, 481 {0xa290, "VGT_GS_MODE"}, 482 {0xa291, "VGT_GS_ONCHIP_CNTL"}, 483 {0xa2d7, "VGT_GS_VERT_ITEMSIZE"}, 484 {0xa2d8, "VGT_GS_VERT_ITEMSIZE_1"}, 485 {0xa2d9, "VGT_GS_VERT_ITEMSIZE_2"}, 486 {0xa2da, "VGT_GS_VERT_ITEMSIZE_3"}, 487 {0xa298, "VGT_GSVS_RING_OFFSET_1"}, 488 {0xa299, "VGT_GSVS_RING_OFFSET_2"}, 489 {0xa29a, "VGT_GSVS_RING_OFFSET_3"}, 490 491 {0xa2e4, "VGT_GS_INSTANCE_CNT"}, 492 {0xa297, "VGT_GS_PER_VS"}, 493 {0xa29b, "VGT_GS_OUT_PRIM_TYPE"}, 494 {0xa2ac, "VGT_GSVS_RING_ITEMSIZE"}, 495 496 {0xa2ad, "VGT_REUSE_OFF"}, 497 {0xa1b8, "SPI_BARYC_CNTL"}, 498 499 {0x2c4c, "SPI_SHADER_USER_DATA_VS_0"}, 500 {0x2c4d, "SPI_SHADER_USER_DATA_VS_1"}, 501 {0x2c4e, "SPI_SHADER_USER_DATA_VS_2"}, 502 {0x2c4f, "SPI_SHADER_USER_DATA_VS_3"}, 503 {0x2c50, "SPI_SHADER_USER_DATA_VS_4"}, 504 {0x2c51, "SPI_SHADER_USER_DATA_VS_5"}, 505 {0x2c52, "SPI_SHADER_USER_DATA_VS_6"}, 506 {0x2c53, "SPI_SHADER_USER_DATA_VS_7"}, 507 {0x2c54, "SPI_SHADER_USER_DATA_VS_8"}, 508 {0x2c55, "SPI_SHADER_USER_DATA_VS_9"}, 509 {0x2c56, "SPI_SHADER_USER_DATA_VS_10"}, 510 {0x2c57, "SPI_SHADER_USER_DATA_VS_11"}, 511 {0x2c58, "SPI_SHADER_USER_DATA_VS_12"}, 512 {0x2c59, "SPI_SHADER_USER_DATA_VS_13"}, 513 {0x2c5a, "SPI_SHADER_USER_DATA_VS_14"}, 514 {0x2c5b, "SPI_SHADER_USER_DATA_VS_15"}, 515 {0x2c5c, "SPI_SHADER_USER_DATA_VS_16"}, 516 {0x2c5d, "SPI_SHADER_USER_DATA_VS_17"}, 517 {0x2c5e, "SPI_SHADER_USER_DATA_VS_18"}, 518 {0x2c5f, "SPI_SHADER_USER_DATA_VS_19"}, 519 {0x2c60, "SPI_SHADER_USER_DATA_VS_20"}, 520 {0x2c61, "SPI_SHADER_USER_DATA_VS_21"}, 521 {0x2c62, "SPI_SHADER_USER_DATA_VS_22"}, 522 {0x2c63, "SPI_SHADER_USER_DATA_VS_23"}, 523 {0x2c64, "SPI_SHADER_USER_DATA_VS_24"}, 524 {0x2c65, "SPI_SHADER_USER_DATA_VS_25"}, 525 {0x2c66, "SPI_SHADER_USER_DATA_VS_26"}, 526 {0x2c67, "SPI_SHADER_USER_DATA_VS_27"}, 527 {0x2c68, "SPI_SHADER_USER_DATA_VS_28"}, 528 {0x2c69, "SPI_SHADER_USER_DATA_VS_29"}, 529 {0x2c6a, "SPI_SHADER_USER_DATA_VS_30"}, 530 {0x2c6b, "SPI_SHADER_USER_DATA_VS_31"}, 531 532 {0x2c8c, "SPI_SHADER_USER_DATA_GS_0"}, 533 {0x2c8d, "SPI_SHADER_USER_DATA_GS_1"}, 534 {0x2c8e, "SPI_SHADER_USER_DATA_GS_2"}, 535 {0x2c8f, "SPI_SHADER_USER_DATA_GS_3"}, 536 {0x2c90, "SPI_SHADER_USER_DATA_GS_4"}, 537 {0x2c91, "SPI_SHADER_USER_DATA_GS_5"}, 538 {0x2c92, "SPI_SHADER_USER_DATA_GS_6"}, 539 {0x2c93, "SPI_SHADER_USER_DATA_GS_7"}, 540 {0x2c94, "SPI_SHADER_USER_DATA_GS_8"}, 541 {0x2c95, "SPI_SHADER_USER_DATA_GS_9"}, 542 {0x2c96, "SPI_SHADER_USER_DATA_GS_10"}, 543 {0x2c97, "SPI_SHADER_USER_DATA_GS_11"}, 544 {0x2c98, "SPI_SHADER_USER_DATA_GS_12"}, 545 {0x2c99, "SPI_SHADER_USER_DATA_GS_13"}, 546 {0x2c9a, "SPI_SHADER_USER_DATA_GS_14"}, 547 {0x2c9b, "SPI_SHADER_USER_DATA_GS_15"}, 548 {0x2c9c, "SPI_SHADER_USER_DATA_GS_16"}, 549 {0x2c9d, "SPI_SHADER_USER_DATA_GS_17"}, 550 {0x2c9e, "SPI_SHADER_USER_DATA_GS_18"}, 551 {0x2c9f, "SPI_SHADER_USER_DATA_GS_19"}, 552 {0x2ca0, "SPI_SHADER_USER_DATA_GS_20"}, 553 {0x2ca1, "SPI_SHADER_USER_DATA_GS_21"}, 554 {0x2ca2, "SPI_SHADER_USER_DATA_GS_22"}, 555 {0x2ca3, "SPI_SHADER_USER_DATA_GS_23"}, 556 {0x2ca4, "SPI_SHADER_USER_DATA_GS_24"}, 557 {0x2ca5, "SPI_SHADER_USER_DATA_GS_25"}, 558 {0x2ca6, "SPI_SHADER_USER_DATA_GS_26"}, 559 {0x2ca7, "SPI_SHADER_USER_DATA_GS_27"}, 560 {0x2ca8, "SPI_SHADER_USER_DATA_GS_28"}, 561 {0x2ca9, "SPI_SHADER_USER_DATA_GS_29"}, 562 {0x2caa, "SPI_SHADER_USER_DATA_GS_30"}, 563 {0x2cab, "SPI_SHADER_USER_DATA_GS_31"}, 564 565 {0x2ccc, "SPI_SHADER_USER_DATA_ES_0"}, 566 {0x2ccd, "SPI_SHADER_USER_DATA_ES_1"}, 567 {0x2cce, "SPI_SHADER_USER_DATA_ES_2"}, 568 {0x2ccf, "SPI_SHADER_USER_DATA_ES_3"}, 569 {0x2cd0, "SPI_SHADER_USER_DATA_ES_4"}, 570 {0x2cd1, "SPI_SHADER_USER_DATA_ES_5"}, 571 {0x2cd2, "SPI_SHADER_USER_DATA_ES_6"}, 572 {0x2cd3, "SPI_SHADER_USER_DATA_ES_7"}, 573 {0x2cd4, "SPI_SHADER_USER_DATA_ES_8"}, 574 {0x2cd5, "SPI_SHADER_USER_DATA_ES_9"}, 575 {0x2cd6, "SPI_SHADER_USER_DATA_ES_10"}, 576 {0x2cd7, "SPI_SHADER_USER_DATA_ES_11"}, 577 {0x2cd8, "SPI_SHADER_USER_DATA_ES_12"}, 578 {0x2cd9, "SPI_SHADER_USER_DATA_ES_13"}, 579 {0x2cda, "SPI_SHADER_USER_DATA_ES_14"}, 580 {0x2cdb, "SPI_SHADER_USER_DATA_ES_15"}, 581 {0x2cdc, "SPI_SHADER_USER_DATA_ES_16"}, 582 {0x2cdd, "SPI_SHADER_USER_DATA_ES_17"}, 583 {0x2cde, "SPI_SHADER_USER_DATA_ES_18"}, 584 {0x2cdf, "SPI_SHADER_USER_DATA_ES_19"}, 585 {0x2ce0, "SPI_SHADER_USER_DATA_ES_20"}, 586 {0x2ce1, "SPI_SHADER_USER_DATA_ES_21"}, 587 {0x2ce2, "SPI_SHADER_USER_DATA_ES_22"}, 588 {0x2ce3, "SPI_SHADER_USER_DATA_ES_23"}, 589 {0x2ce4, "SPI_SHADER_USER_DATA_ES_24"}, 590 {0x2ce5, "SPI_SHADER_USER_DATA_ES_25"}, 591 {0x2ce6, "SPI_SHADER_USER_DATA_ES_26"}, 592 {0x2ce7, "SPI_SHADER_USER_DATA_ES_27"}, 593 {0x2ce8, "SPI_SHADER_USER_DATA_ES_28"}, 594 {0x2ce9, "SPI_SHADER_USER_DATA_ES_29"}, 595 {0x2cea, "SPI_SHADER_USER_DATA_ES_30"}, 596 {0x2ceb, "SPI_SHADER_USER_DATA_ES_31"}, 597 598 {0x2c0c, "SPI_SHADER_USER_DATA_PS_0"}, 599 {0x2c0d, "SPI_SHADER_USER_DATA_PS_1"}, 600 {0x2c0e, "SPI_SHADER_USER_DATA_PS_2"}, 601 {0x2c0f, "SPI_SHADER_USER_DATA_PS_3"}, 602 {0x2c10, "SPI_SHADER_USER_DATA_PS_4"}, 603 {0x2c11, "SPI_SHADER_USER_DATA_PS_5"}, 604 {0x2c12, "SPI_SHADER_USER_DATA_PS_6"}, 605 {0x2c13, "SPI_SHADER_USER_DATA_PS_7"}, 606 {0x2c14, "SPI_SHADER_USER_DATA_PS_8"}, 607 {0x2c15, "SPI_SHADER_USER_DATA_PS_9"}, 608 {0x2c16, "SPI_SHADER_USER_DATA_PS_10"}, 609 {0x2c17, "SPI_SHADER_USER_DATA_PS_11"}, 610 {0x2c18, "SPI_SHADER_USER_DATA_PS_12"}, 611 {0x2c19, "SPI_SHADER_USER_DATA_PS_13"}, 612 {0x2c1a, "SPI_SHADER_USER_DATA_PS_14"}, 613 {0x2c1b, "SPI_SHADER_USER_DATA_PS_15"}, 614 {0x2c1c, "SPI_SHADER_USER_DATA_PS_16"}, 615 {0x2c1d, "SPI_SHADER_USER_DATA_PS_17"}, 616 {0x2c1e, "SPI_SHADER_USER_DATA_PS_18"}, 617 {0x2c1f, "SPI_SHADER_USER_DATA_PS_19"}, 618 {0x2c20, "SPI_SHADER_USER_DATA_PS_20"}, 619 {0x2c21, "SPI_SHADER_USER_DATA_PS_21"}, 620 {0x2c22, "SPI_SHADER_USER_DATA_PS_22"}, 621 {0x2c23, "SPI_SHADER_USER_DATA_PS_23"}, 622 {0x2c24, "SPI_SHADER_USER_DATA_PS_24"}, 623 {0x2c25, "SPI_SHADER_USER_DATA_PS_25"}, 624 {0x2c26, "SPI_SHADER_USER_DATA_PS_26"}, 625 {0x2c27, "SPI_SHADER_USER_DATA_PS_27"}, 626 {0x2c28, "SPI_SHADER_USER_DATA_PS_28"}, 627 {0x2c29, "SPI_SHADER_USER_DATA_PS_29"}, 628 {0x2c2a, "SPI_SHADER_USER_DATA_PS_30"}, 629 {0x2c2b, "SPI_SHADER_USER_DATA_PS_31"}, 630 631 {0x2e40, "COMPUTE_USER_DATA_0"}, 632 {0x2e41, "COMPUTE_USER_DATA_1"}, 633 {0x2e42, "COMPUTE_USER_DATA_2"}, 634 {0x2e43, "COMPUTE_USER_DATA_3"}, 635 {0x2e44, "COMPUTE_USER_DATA_4"}, 636 {0x2e45, "COMPUTE_USER_DATA_5"}, 637 {0x2e46, "COMPUTE_USER_DATA_6"}, 638 {0x2e47, "COMPUTE_USER_DATA_7"}, 639 {0x2e48, "COMPUTE_USER_DATA_8"}, 640 {0x2e49, "COMPUTE_USER_DATA_9"}, 641 {0x2e4a, "COMPUTE_USER_DATA_10"}, 642 {0x2e4b, "COMPUTE_USER_DATA_11"}, 643 {0x2e4c, "COMPUTE_USER_DATA_12"}, 644 {0x2e4d, "COMPUTE_USER_DATA_13"}, 645 {0x2e4e, "COMPUTE_USER_DATA_14"}, 646 {0x2e4f, "COMPUTE_USER_DATA_15"}, 647 648 {0x2e07, "COMPUTE_NUM_THREAD_X"}, 649 {0x2e08, "COMPUTE_NUM_THREAD_Y"}, 650 {0x2e09, "COMPUTE_NUM_THREAD_Z"}, 651 {0xa2db, "VGT_TF_PARAM"}, 652 {0xa2d6, "VGT_LS_HS_CONFIG"}, 653 {0xa287, "VGT_HOS_MIN_TESS_LEVEL"}, 654 {0xa286, "VGT_HOS_MAX_TESS_LEVEL"}, 655 {0xa2f8, "PA_SC_AA_CONFIG"}, 656 {0xa310, "PA_SC_SHADER_CONTROL"}, 657 {0xa313, "PA_SC_CONSERVATIVE_RASTERIZATION_CNTL"}, 658 659 {0x2d0c, "SPI_SHADER_USER_DATA_HS_0"}, 660 {0x2d0d, "SPI_SHADER_USER_DATA_HS_1"}, 661 {0x2d0e, "SPI_SHADER_USER_DATA_HS_2"}, 662 {0x2d0f, "SPI_SHADER_USER_DATA_HS_3"}, 663 {0x2d10, "SPI_SHADER_USER_DATA_HS_4"}, 664 {0x2d11, "SPI_SHADER_USER_DATA_HS_5"}, 665 {0x2d12, "SPI_SHADER_USER_DATA_HS_6"}, 666 {0x2d13, "SPI_SHADER_USER_DATA_HS_7"}, 667 {0x2d14, "SPI_SHADER_USER_DATA_HS_8"}, 668 {0x2d15, "SPI_SHADER_USER_DATA_HS_9"}, 669 {0x2d16, "SPI_SHADER_USER_DATA_HS_10"}, 670 {0x2d17, "SPI_SHADER_USER_DATA_HS_11"}, 671 {0x2d18, "SPI_SHADER_USER_DATA_HS_12"}, 672 {0x2d19, "SPI_SHADER_USER_DATA_HS_13"}, 673 {0x2d1a, "SPI_SHADER_USER_DATA_HS_14"}, 674 {0x2d1b, "SPI_SHADER_USER_DATA_HS_15"}, 675 {0x2d1c, "SPI_SHADER_USER_DATA_HS_16"}, 676 {0x2d1d, "SPI_SHADER_USER_DATA_HS_17"}, 677 {0x2d1e, "SPI_SHADER_USER_DATA_HS_18"}, 678 {0x2d1f, "SPI_SHADER_USER_DATA_HS_19"}, 679 {0x2d20, "SPI_SHADER_USER_DATA_HS_20"}, 680 {0x2d21, "SPI_SHADER_USER_DATA_HS_21"}, 681 {0x2d22, "SPI_SHADER_USER_DATA_HS_22"}, 682 {0x2d23, "SPI_SHADER_USER_DATA_HS_23"}, 683 {0x2d24, "SPI_SHADER_USER_DATA_HS_24"}, 684 {0x2d25, "SPI_SHADER_USER_DATA_HS_25"}, 685 {0x2d26, "SPI_SHADER_USER_DATA_HS_26"}, 686 {0x2d27, "SPI_SHADER_USER_DATA_HS_27"}, 687 {0x2d28, "SPI_SHADER_USER_DATA_HS_28"}, 688 {0x2d29, "SPI_SHADER_USER_DATA_HS_29"}, 689 {0x2d2a, "SPI_SHADER_USER_DATA_HS_30"}, 690 {0x2d2b, "SPI_SHADER_USER_DATA_HS_31"}, 691 692 {0x2d4c, "SPI_SHADER_USER_DATA_LS_0"}, 693 {0x2d4d, "SPI_SHADER_USER_DATA_LS_1"}, 694 {0x2d4e, "SPI_SHADER_USER_DATA_LS_2"}, 695 {0x2d4f, "SPI_SHADER_USER_DATA_LS_3"}, 696 {0x2d50, "SPI_SHADER_USER_DATA_LS_4"}, 697 {0x2d51, "SPI_SHADER_USER_DATA_LS_5"}, 698 {0x2d52, "SPI_SHADER_USER_DATA_LS_6"}, 699 {0x2d53, "SPI_SHADER_USER_DATA_LS_7"}, 700 {0x2d54, "SPI_SHADER_USER_DATA_LS_8"}, 701 {0x2d55, "SPI_SHADER_USER_DATA_LS_9"}, 702 {0x2d56, "SPI_SHADER_USER_DATA_LS_10"}, 703 {0x2d57, "SPI_SHADER_USER_DATA_LS_11"}, 704 {0x2d58, "SPI_SHADER_USER_DATA_LS_12"}, 705 {0x2d59, "SPI_SHADER_USER_DATA_LS_13"}, 706 {0x2d5a, "SPI_SHADER_USER_DATA_LS_14"}, 707 {0x2d5b, "SPI_SHADER_USER_DATA_LS_15"}, 708 709 {0xa2aa, "IA_MULTI_VGT_PARAM"}, 710 {0xa2a5, "VGT_GS_MAX_PRIMS_PER_SUBGROUP"}, 711 {0xa2e6, "VGT_STRMOUT_BUFFER_CONFIG"}, 712 {0xa2e5, "VGT_STRMOUT_CONFIG"}, 713 {0xa2b5, "VGT_STRMOUT_VTX_STRIDE_0"}, 714 {0xa2b9, "VGT_STRMOUT_VTX_STRIDE_1"}, 715 {0xa2bd, "VGT_STRMOUT_VTX_STRIDE_2"}, 716 {0xa2c1, "VGT_STRMOUT_VTX_STRIDE_3"}, 717 {0xa316, "VGT_VERTEX_REUSE_BLOCK_CNTL"}, 718 719 {0x2e28, "COMPUTE_PGM_RSRC3"}, 720 {0x2e2a, "COMPUTE_SHADER_CHKSUM"}, 721 {0x2e24, "COMPUTE_USER_ACCUM_0"}, 722 {0x2e25, "COMPUTE_USER_ACCUM_1"}, 723 {0x2e26, "COMPUTE_USER_ACCUM_2"}, 724 {0x2e27, "COMPUTE_USER_ACCUM_3"}, 725 {0xa1ff, "GE_MAX_OUTPUT_PER_SUBGROUP"}, 726 {0xa2d3, "GE_NGG_SUBGRP_CNTL"}, 727 {0xc25f, "GE_STEREO_CNTL"}, 728 {0xc262, "GE_USER_VGPR_EN"}, 729 {0xc258, "IA_MULTI_VGT_PARAM_PIPED"}, 730 {0xa210, "PA_STEREO_CNTL"}, 731 {0xa1c2, "SPI_SHADER_IDX_FORMAT"}, 732 {0x2c80, "SPI_SHADER_PGM_CHKSUM_GS"}, 733 {0x2d00, "SPI_SHADER_PGM_CHKSUM_HS"}, 734 {0x2c06, "SPI_SHADER_PGM_CHKSUM_PS"}, 735 {0x2c45, "SPI_SHADER_PGM_CHKSUM_VS"}, 736 {0x2c88, "SPI_SHADER_PGM_LO_GS"}, 737 {0x2cb2, "SPI_SHADER_USER_ACCUM_ESGS_0"}, 738 {0x2cb3, "SPI_SHADER_USER_ACCUM_ESGS_1"}, 739 {0x2cb4, "SPI_SHADER_USER_ACCUM_ESGS_2"}, 740 {0x2cb5, "SPI_SHADER_USER_ACCUM_ESGS_3"}, 741 {0x2d32, "SPI_SHADER_USER_ACCUM_LSHS_0"}, 742 {0x2d33, "SPI_SHADER_USER_ACCUM_LSHS_1"}, 743 {0x2d34, "SPI_SHADER_USER_ACCUM_LSHS_2"}, 744 {0x2d35, "SPI_SHADER_USER_ACCUM_LSHS_3"}, 745 {0x2c32, "SPI_SHADER_USER_ACCUM_PS_0"}, 746 {0x2c33, "SPI_SHADER_USER_ACCUM_PS_1"}, 747 {0x2c34, "SPI_SHADER_USER_ACCUM_PS_2"}, 748 {0x2c35, "SPI_SHADER_USER_ACCUM_PS_3"}, 749 {0x2c72, "SPI_SHADER_USER_ACCUM_VS_0"}, 750 {0x2c73, "SPI_SHADER_USER_ACCUM_VS_1"}, 751 {0x2c74, "SPI_SHADER_USER_ACCUM_VS_2"}, 752 {0x2c75, "SPI_SHADER_USER_ACCUM_VS_3"}, 753 754 {0, nullptr}}; 755 const auto *Entry = RegInfoTable; 756 for (; Entry->Num && Entry->Num != RegNum; ++Entry) 757 ; 758 return Entry->Name; 759 } 760 761 // Convert the accumulated PAL metadata into an asm directive. 762 void AMDGPUPALMetadata::toString(std::string &String) { 763 String.clear(); 764 if (!BlobType) 765 return; 766 ResolvedAll = DelayedExprs.resolveDelayedExpressions(); 767 raw_string_ostream Stream(String); 768 if (isLegacy()) { 769 if (MsgPackDoc.getRoot().getKind() == msgpack::Type::Nil) 770 return; 771 // Old linear reg=val format. 772 Stream << '\t' << AMDGPU::PALMD::AssemblerDirective << ' '; 773 auto Regs = getRegisters(); 774 for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I) { 775 if (I != Regs.begin()) 776 Stream << ','; 777 unsigned Reg = I->first.getUInt(); 778 unsigned Val = I->second.getUInt(); 779 Stream << "0x" << Twine::utohexstr(Reg) << ",0x" << Twine::utohexstr(Val); 780 } 781 Stream << '\n'; 782 return; 783 } 784 785 // New msgpack-based format -- output as YAML (with unsigned numbers in hex), 786 // but first change the registers map to use names. 787 MsgPackDoc.setHexMode(); 788 auto &RegsObj = refRegisters(); 789 auto OrigRegs = RegsObj.getMap(); 790 RegsObj = MsgPackDoc.getMapNode(); 791 for (auto I : OrigRegs) { 792 auto Key = I.first; 793 if (const char *RegName = getRegisterName(Key.getUInt())) { 794 std::string KeyName = Key.toString(); 795 KeyName += " ("; 796 KeyName += RegName; 797 KeyName += ')'; 798 Key = MsgPackDoc.getNode(KeyName, /*Copy=*/true); 799 } 800 RegsObj.getMap()[Key] = I.second; 801 } 802 803 // Output as YAML. 804 Stream << '\t' << AMDGPU::PALMD::AssemblerDirectiveBegin << '\n'; 805 MsgPackDoc.toYAML(Stream); 806 Stream << '\t' << AMDGPU::PALMD::AssemblerDirectiveEnd << '\n'; 807 808 // Restore original registers map. 809 RegsObj = OrigRegs; 810 } 811 812 // Convert the accumulated PAL metadata into a binary blob for writing as 813 // a .note record of the specified AMD type. Returns an empty blob if 814 // there is no PAL metadata, 815 void AMDGPUPALMetadata::toBlob(unsigned Type, std::string &Blob) { 816 ResolvedAll = DelayedExprs.resolveDelayedExpressions(); 817 if (Type == ELF::NT_AMD_PAL_METADATA) 818 toLegacyBlob(Blob); 819 else if (Type) 820 toMsgPackBlob(Blob); 821 } 822 823 void AMDGPUPALMetadata::toLegacyBlob(std::string &Blob) { 824 Blob.clear(); 825 auto Registers = getRegisters(); 826 if (Registers.getMap().empty()) 827 return; 828 raw_string_ostream OS(Blob); 829 support::endian::Writer EW(OS, llvm::endianness::little); 830 for (auto I : Registers.getMap()) { 831 EW.write(uint32_t(I.first.getUInt())); 832 EW.write(uint32_t(I.second.getUInt())); 833 } 834 } 835 836 void AMDGPUPALMetadata::toMsgPackBlob(std::string &Blob) { 837 Blob.clear(); 838 MsgPackDoc.writeToBlob(Blob); 839 } 840 841 // Set PAL metadata from YAML text. Returns false if failed. 842 bool AMDGPUPALMetadata::setFromString(StringRef S) { 843 BlobType = ELF::NT_AMDGPU_METADATA; 844 if (!MsgPackDoc.fromYAML(S)) 845 return false; 846 847 // In the registers map, some keys may be of the form "0xa191 848 // (SPI_PS_INPUT_CNTL_0)", in which case the YAML input code made it a 849 // string. We need to turn it into a number. 850 auto &RegsObj = refRegisters(); 851 auto OrigRegs = RegsObj; 852 RegsObj = MsgPackDoc.getMapNode(); 853 Registers = RegsObj.getMap(); 854 bool Ok = true; 855 for (auto I : OrigRegs.getMap()) { 856 auto Key = I.first; 857 if (Key.getKind() == msgpack::Type::String) { 858 StringRef S = Key.getString(); 859 uint64_t Val; 860 if (S.consumeInteger(0, Val)) { 861 Ok = false; 862 errs() << "Unrecognized PAL metadata register key '" << S << "'\n"; 863 continue; 864 } 865 Key = MsgPackDoc.getNode(uint64_t(Val)); 866 } 867 Registers.getMap()[Key] = I.second; 868 } 869 return Ok; 870 } 871 872 // Reference (create if necessary) the node for the registers map. 873 msgpack::DocNode &AMDGPUPALMetadata::refRegisters() { 874 auto &N = 875 MsgPackDoc.getRoot() 876 .getMap(/*Convert=*/true)[MsgPackDoc.getNode("amdpal.pipelines")] 877 .getArray(/*Convert=*/true)[0] 878 .getMap(/*Convert=*/true)[MsgPackDoc.getNode(".registers")]; 879 N.getMap(/*Convert=*/true); 880 return N; 881 } 882 883 // Get (create if necessary) the registers map. 884 msgpack::MapDocNode AMDGPUPALMetadata::getRegisters() { 885 if (Registers.isEmpty()) 886 Registers = refRegisters(); 887 return Registers.getMap(); 888 } 889 890 // Reference (create if necessary) the node for the shader functions map. 891 msgpack::DocNode &AMDGPUPALMetadata::refShaderFunctions() { 892 auto &N = 893 MsgPackDoc.getRoot() 894 .getMap(/*Convert=*/true)[MsgPackDoc.getNode("amdpal.pipelines")] 895 .getArray(/*Convert=*/true)[0] 896 .getMap(/*Convert=*/true)[MsgPackDoc.getNode(".shader_functions")]; 897 N.getMap(/*Convert=*/true); 898 return N; 899 } 900 901 // Get (create if necessary) the shader functions map. 902 msgpack::MapDocNode AMDGPUPALMetadata::getShaderFunctions() { 903 if (ShaderFunctions.isEmpty()) 904 ShaderFunctions = refShaderFunctions(); 905 return ShaderFunctions.getMap(); 906 } 907 908 // Get (create if necessary) a function in the shader functions map. 909 msgpack::MapDocNode AMDGPUPALMetadata::getShaderFunction(StringRef Name) { 910 auto Functions = getShaderFunctions(); 911 return Functions[Name].getMap(/*Convert=*/true); 912 } 913 914 msgpack::DocNode &AMDGPUPALMetadata::refComputeRegisters() { 915 auto &N = 916 MsgPackDoc.getRoot() 917 .getMap(/*Convert=*/true)[MsgPackDoc.getNode("amdpal.pipelines")] 918 .getArray(/*Convert=*/true)[0] 919 .getMap(/*Convert=*/true)[MsgPackDoc.getNode(".compute_registers")]; 920 N.getMap(/*Convert=*/true); 921 return N; 922 } 923 924 msgpack::MapDocNode AMDGPUPALMetadata::getComputeRegisters() { 925 if (ComputeRegisters.isEmpty()) 926 ComputeRegisters = refComputeRegisters(); 927 return ComputeRegisters.getMap(); 928 } 929 930 msgpack::DocNode &AMDGPUPALMetadata::refGraphicsRegisters() { 931 auto &N = 932 MsgPackDoc.getRoot() 933 .getMap(/*Convert=*/true)[MsgPackDoc.getNode("amdpal.pipelines")] 934 .getArray(/*Convert=*/true)[0] 935 .getMap(/*Convert=*/true)[MsgPackDoc.getNode(".graphics_registers")]; 936 N.getMap(/*Convert=*/true); 937 return N; 938 } 939 940 msgpack::MapDocNode AMDGPUPALMetadata::getGraphicsRegisters() { 941 if (GraphicsRegisters.isEmpty()) 942 GraphicsRegisters = refGraphicsRegisters(); 943 return GraphicsRegisters.getMap(); 944 } 945 946 // Return the PAL metadata hardware shader stage name. 947 static const char *getStageName(CallingConv::ID CC) { 948 switch (CC) { 949 case CallingConv::AMDGPU_PS: 950 return ".ps"; 951 case CallingConv::AMDGPU_VS: 952 return ".vs"; 953 case CallingConv::AMDGPU_GS: 954 return ".gs"; 955 case CallingConv::AMDGPU_ES: 956 return ".es"; 957 case CallingConv::AMDGPU_HS: 958 return ".hs"; 959 case CallingConv::AMDGPU_LS: 960 return ".ls"; 961 case CallingConv::AMDGPU_Gfx: 962 llvm_unreachable("Callable shader has no hardware stage"); 963 default: 964 return ".cs"; 965 } 966 } 967 968 msgpack::DocNode &AMDGPUPALMetadata::refHwStage() { 969 auto &N = 970 MsgPackDoc.getRoot() 971 .getMap(/*Convert=*/true)[MsgPackDoc.getNode("amdpal.pipelines")] 972 .getArray(/*Convert=*/true)[0] 973 .getMap(/*Convert=*/true)[MsgPackDoc.getNode(".hardware_stages")]; 974 N.getMap(/*Convert=*/true); 975 return N; 976 } 977 978 // Get (create if necessary) the .hardware_stages entry for the given calling 979 // convention. 980 msgpack::MapDocNode AMDGPUPALMetadata::getHwStage(unsigned CC) { 981 if (HwStages.isEmpty()) 982 HwStages = refHwStage(); 983 return HwStages.getMap()[getStageName(CC)].getMap(/*Convert=*/true); 984 } 985 986 // Get .note record vendor name of metadata blob to be emitted. 987 const char *AMDGPUPALMetadata::getVendor() const { 988 return isLegacy() ? ElfNote::NoteNameV2 : ElfNote::NoteNameV3; 989 } 990 991 // Get .note record type of metadata blob to be emitted: 992 // ELF::NT_AMD_PAL_METADATA (legacy key=val format), or 993 // ELF::NT_AMDGPU_METADATA (MsgPack format), or 994 // 0 (no PAL metadata). 995 unsigned AMDGPUPALMetadata::getType() const { 996 return BlobType; 997 } 998 999 // Return whether the blob type is legacy PAL metadata. 1000 bool AMDGPUPALMetadata::isLegacy() const { 1001 return BlobType == ELF::NT_AMD_PAL_METADATA; 1002 } 1003 1004 // Set legacy PAL metadata format. 1005 void AMDGPUPALMetadata::setLegacy() { 1006 BlobType = ELF::NT_AMD_PAL_METADATA; 1007 } 1008 1009 // Erase all PAL metadata. 1010 void AMDGPUPALMetadata::reset() { 1011 MsgPackDoc.clear(); 1012 REM.clear(); 1013 DelayedExprs.clear(); 1014 Registers = MsgPackDoc.getEmptyNode(); 1015 HwStages = MsgPackDoc.getEmptyNode(); 1016 ShaderFunctions = MsgPackDoc.getEmptyNode(); 1017 } 1018 1019 bool AMDGPUPALMetadata::resolvedAllMCExpr() { 1020 return ResolvedAll && DelayedExprs.empty(); 1021 } 1022 1023 unsigned AMDGPUPALMetadata::getPALVersion(unsigned idx) { 1024 assert(idx < 2 && 1025 "illegal index to PAL version - should be 0 (major) or 1 (minor)"); 1026 if (!VersionChecked) { 1027 if (Version.isEmpty()) { 1028 auto &M = MsgPackDoc.getRoot().getMap(/*Convert=*/true); 1029 auto I = M.find(MsgPackDoc.getNode("amdpal.version")); 1030 if (I != M.end()) 1031 Version = I->second; 1032 } 1033 VersionChecked = true; 1034 } 1035 if (Version.isEmpty()) 1036 // Default to 2.6 if there's no version info 1037 return idx ? 6 : 2; 1038 return Version.getArray()[idx].getUInt(); 1039 } 1040 1041 unsigned AMDGPUPALMetadata::getPALMajorVersion() { return getPALVersion(0); } 1042 1043 unsigned AMDGPUPALMetadata::getPALMinorVersion() { return getPALVersion(1); } 1044 1045 // Set the field in a given .hardware_stages entry 1046 void AMDGPUPALMetadata::setHwStage(unsigned CC, StringRef field, unsigned Val) { 1047 getHwStage(CC)[field] = Val; 1048 } 1049 1050 void AMDGPUPALMetadata::setHwStage(unsigned CC, StringRef field, bool Val) { 1051 getHwStage(CC)[field] = Val; 1052 } 1053 1054 void AMDGPUPALMetadata::setHwStage(unsigned CC, StringRef field, 1055 msgpack::Type Type, const MCExpr *Val) { 1056 DelayedExprs.assignDocNode(getHwStage(CC)[field], Type, Val); 1057 } 1058 1059 void AMDGPUPALMetadata::setComputeRegisters(StringRef field, unsigned Val) { 1060 getComputeRegisters()[field] = Val; 1061 } 1062 1063 void AMDGPUPALMetadata::setComputeRegisters(StringRef field, bool Val) { 1064 getComputeRegisters()[field] = Val; 1065 } 1066 1067 msgpack::DocNode *AMDGPUPALMetadata::refComputeRegister(StringRef field) { 1068 auto M = getComputeRegisters(); 1069 auto I = M.find(field); 1070 return I == M.end() ? nullptr : &I->second; 1071 } 1072 1073 bool AMDGPUPALMetadata::checkComputeRegisters(StringRef field, unsigned Val) { 1074 if (auto *N = refComputeRegister(field)) 1075 return N->getUInt() == Val; 1076 return false; 1077 } 1078 1079 bool AMDGPUPALMetadata::checkComputeRegisters(StringRef field, bool Val) { 1080 if (auto *N = refComputeRegister(field)) 1081 return N->getBool() == Val; 1082 return false; 1083 } 1084 1085 void AMDGPUPALMetadata::setGraphicsRegisters(StringRef field, unsigned Val) { 1086 getGraphicsRegisters()[field] = Val; 1087 } 1088 1089 void AMDGPUPALMetadata::setGraphicsRegisters(StringRef field, bool Val) { 1090 getGraphicsRegisters()[field] = Val; 1091 } 1092 1093 void AMDGPUPALMetadata::setGraphicsRegisters(StringRef field1, StringRef field2, 1094 unsigned Val) { 1095 getGraphicsRegisters()[field1].getMap(true)[field2] = Val; 1096 } 1097 1098 void AMDGPUPALMetadata::setGraphicsRegisters(StringRef field1, StringRef field2, 1099 bool Val) { 1100 getGraphicsRegisters()[field1].getMap(true)[field2] = Val; 1101 } 1102