xref: /netbsd-src/sys/arch/m68k/include/pmap_motorola.h (revision 10c53e2bf712645e3c28535457edc55b59f0b5f6)
1 /*	$NetBSD: pmap_motorola.h,v 1.43 2023/12/31 21:59:24 thorpej Exp $	*/
2 
3 /*
4  * Copyright (c) 1991, 1993
5  *	The Regents of the University of California.  All rights reserved.
6  *
7  * This code is derived from software contributed to Berkeley by
8  * the Systems Programming Group of the University of Utah Computer
9  * Science Department.
10  *
11  * Redistribution and use in source and binary forms, with or without
12  * modification, are permitted provided that the following conditions
13  * are met:
14  * 1. Redistributions of source code must retain the above copyright
15  *    notice, this list of conditions and the following disclaimer.
16  * 2. Redistributions in binary form must reproduce the above copyright
17  *    notice, this list of conditions and the following disclaimer in the
18  *    documentation and/or other materials provided with the distribution.
19  * 3. Neither the name of the University nor the names of its contributors
20  *    may be used to endorse or promote products derived from this software
21  *    without specific prior written permission.
22  *
23  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
24  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
27  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33  * SUCH DAMAGE.
34  *
35  *	@(#)pmap.h	8.1 (Berkeley) 6/10/93
36  */
37 
38 /*
39  * Copyright (c) 1987 Carnegie-Mellon University
40  *
41  * This code is derived from software contributed to Berkeley by
42  * the Systems Programming Group of the University of Utah Computer
43  * Science Department.
44  *
45  * Redistribution and use in source and binary forms, with or without
46  * modification, are permitted provided that the following conditions
47  * are met:
48  * 1. Redistributions of source code must retain the above copyright
49  *    notice, this list of conditions and the following disclaimer.
50  * 2. Redistributions in binary form must reproduce the above copyright
51  *    notice, this list of conditions and the following disclaimer in the
52  *    documentation and/or other materials provided with the distribution.
53  * 3. All advertising materials mentioning features or use of this software
54  *    must display the following acknowledgement:
55  *	This product includes software developed by the University of
56  *	California, Berkeley and its contributors.
57  * 4. Neither the name of the University nor the names of its contributors
58  *    may be used to endorse or promote products derived from this software
59  *    without specific prior written permission.
60  *
61  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
62  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
63  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
64  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
65  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
66  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
67  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
68  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
69  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
70  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
71  * SUCH DAMAGE.
72  *
73  *	@(#)pmap.h	8.1 (Berkeley) 6/10/93
74  */
75 
76 #ifndef	_M68K_PMAP_MOTOROLA_H_
77 #define	_M68K_PMAP_MOTOROLA_H_
78 
79 #ifdef _KERNEL_OPT
80 #include "opt_m68k_arch.h"
81 #endif
82 
83 #include <machine/cpu.h>
84 #include <machine/pte.h>
85 
86 /*
87  * Pmap stuff
88  */
89 struct pmap {
90 	pt_entry_t		*pm_ptab;	/* KVA of page table */
91 	st_entry_t		*pm_stab;	/* KVA of segment table */
92 	u_int			pm_stfree;	/* 040: free lev2 blocks */
93 	st_entry_t		*pm_stpa;	/* 040: ST phys addr */
94 	uint16_t		pm_sref;	/* segment table ref count */
95 	u_int			pm_count;	/* pmap reference count */
96 	struct pmap_statistics	pm_stats;	/* pmap statistics */
97 	int			pm_ptpages;	/* more stats: PT pages */
98 };
99 
100 /*
101  * Root Pointer attributes for Supervisor and User modes.
102  *
103  * Supervisor:
104  * - No index limit (Lower limit == 0)
105  * - Points to Short format descriptor table.
106  * - Shared Globally
107  *
108  * User:
109  * - No index limit (Lower limit == 0)
110  * - Points to Short format descriptor table.
111  */
112 #define	MMU51_SRP_BITS	(DTE51_LOWER | DTE51_SG | DT51_SHORT)
113 #define	MMU51_CRP_BITS	(DTE51_LOWER |            DT51_SHORT)
114 
115 /*
116  * MMU specific segment values
117  *
118  * We are using following segment layout in m68k pmap_motorola.c:
119  * 68020/030 4KB/page: l1,l2,page    == 10,10,12	(%tc = 0x82c0aa00)
120  * 68020/030 8KB/page: l1,l2,page    ==  8,11,13	(%tc = 0x82d08b00)
121  * 68040/060 4KB/page: l1,l2,l3,page == 7,7,6,12	(%tc = 0x8000)
122  * 68040/060 8KB/page: l1,l2,l3,page == 7,7,5,13	(%tc = 0xc000)
123  *
124  * 68020/030 l2 size is chosen per NPTEPG, a number of page table entries
125  * per page, to use one whole page for PTEs per one segment table entry,
126  * and maybe also because 68020 HP MMU machines use similar structures.
127  *
128  * 68040/060 layout is defined by hardware design and not configurable,
129  * as defined in <m68k/pte_motorola.h>.
130  *
131  * Even on 68040/060, we still appropriate 2-level ste-pte pmap structures
132  * for 68020/030 (derived from 4.4BSD/hp300) to handle 040's 3-level MMU.
133  * TIA_SIZE and TIB_SIZE are used to represent such pmap structures and
134  * they are also referred on 040/060.
135  *
136  * NBSEG and SEGOFSET are used to check l2 STE of the specified VA,
137  * so they have different values between 020/030 and 040/060.
138  */
139 							/*  8KB /  4KB	*/
140 #define TIB_SHIFT	(PGSHIFT - 2)			/*   11 /   10	*/
141 #define TIB_SIZE	(1U << TIB_SHIFT)		/* 2048 / 1024	*/
142 #define TIA_SHIFT	(32 - TIB_SHIFT - PGSHIFT)	/*    8 /   10	*/
143 #define TIA_SIZE	(1U << TIA_SHIFT)		/*  256 / 1024	*/
144 
145 #define	MMU51_TCR_BITS	(TCR51_E | TCR51_SRE |				\
146 			 __SHIFTIN(PGSHIFT, TCR51_PS) |			\
147 			 __SHIFTIN(TIA_SHIFT, TCR51_TIA) |		\
148 			 __SHIFTIN(TIB_SHIFT, TCR51_TIB))
149 #define	MMU40_TCR_BITS	(TCR40_E |					\
150 			 __SHIFTIN(PGSHIFT - 12, TCR40_P))
151 
152 #define SEGSHIFT	(TIB_SHIFT + PGSHIFT)		/*   24 /   22	*/
153 
154 #define NBSEG30		(1U << SEGSHIFT)
155 #define NBSEG40		(1U << SG4_SHIFT2)
156 
157 #if   ( defined(M68020) ||  defined(M68030)) &&	\
158       (!defined(M68040) && !defined(M68060))
159 #define NBSEG		NBSEG30
160 #elif ( defined(M68040) ||  defined(M68060)) &&	\
161       (!defined(M68020) && !defined(M68030))
162 #define NBSEG		NBSEG40
163 #else
164 #define NBSEG		((mmutype == MMU_68040) ? NBSEG40 : NBSEG30)
165 #endif
166 
167 #define SEGOFSET	(NBSEG - 1)	/* byte offset into segment */
168 
169 #define	m68k_round_seg(x)	((((vaddr_t)(x)) + SEGOFSET) & ~SEGOFSET)
170 #define	m68k_trunc_seg(x)	((vaddr_t)(x) & ~SEGOFSET)
171 #define	m68k_seg_offset(x)	((vaddr_t)(x) & SEGOFSET)
172 
173 /*
174  * On the 040, we keep track of which level 2 blocks are already in use
175  * with the pm_stfree mask.  Bits are arranged from LSB (block 0) to MSB
176  * (block 31).  For convenience, the level 1 table is considered to be
177  * block 0.
178  *
179  * MAX[KU]L2SIZE control how many pages of level 2 descriptors are allowed
180  * for the kernel and users.
181  * 16 or 8 implies only the initial "segment table" page is used,
182  * i.e. it means PAGE_SIZE / (SG4_LEV1SIZE * sizeof(st_entry_t)).
183  * WARNING: don't change MAXUL2SIZE unless you can allocate
184  * physically contiguous pages for the ST in pmap_motorola.c!
185  */
186 #define MAXKL2SIZE	32
187 #if PAGE_SIZE == 8192	/* NBPG / (SG4_LEV1SIZE * sizeof(st_entry_t)) */
188 #define MAXUL2SIZE	16
189 #else
190 #define MAXUL2SIZE	8
191 #endif
192 #define l2tobm(n)	(1U << (n))
193 #define bmtol2(n)	(ffs(n) - 1)
194 
195 /*
196  * For each struct vm_page, there is a list of all currently valid virtual
197  * mappings of that page.  An entry is a pv_entry, the list is pv_table.
198  */
199 struct pv_entry {
200 	struct pv_entry	*pv_next;	/* next pv_entry */
201 	struct pmap	*pv_pmap;	/* pmap where mapping lies */
202 	vaddr_t		pv_va;		/* virtual address for mapping */
203 	st_entry_t	*pv_ptste;	/* non-zero if VA maps a PT page */
204 	struct pmap	*pv_ptpmap;	/* if pv_ptste, pmap for PT page */
205 };
206 
207 extern struct pv_header	*pv_table;	/* array of entries, one per page */
208 
209 #define	pmap_resident_count(pmap)	((pmap)->pm_stats.resident_count)
210 #define	pmap_wired_count(pmap)		((pmap)->pm_stats.wired_count)
211 
212 #define	pmap_update(pmap)		__nothing	/* nothing (yet) */
213 
214 static __inline bool
pmap_remove_all(struct pmap * pmap)215 pmap_remove_all(struct pmap *pmap)
216 {
217 	/* Nothing. */
218 	return false;
219 }
220 
221 extern paddr_t		Sysseg_pa;
222 extern st_entry_t	*Sysseg;
223 extern pt_entry_t	*Sysmap, *Sysptmap;
224 #define	SYSMAP_VA	VM_MAX_KERNEL_ADDRESS
225 extern vsize_t		Sysptsize;
226 extern vsize_t		mem_size;
227 extern vaddr_t		virtual_avail, virtual_end;
228 extern u_int		protection_codes[];
229 #if defined(M68040) || defined(M68060)
230 extern u_int		protostfree;
231 #endif
232 #ifdef CACHE_HAVE_VAC
233 extern u_int		pmap_aliasmask;
234 #endif
235 
236 extern char		*vmmap;		/* map for mem, dumps, etc. */
237 extern void		*CADDR1, *CADDR2;
238 extern void		*msgbufaddr;
239 
240 /* for lwp0 uarea initialization after MMU enabled */
241 extern vaddr_t		lwp0uarea;
242 void	pmap_bootstrap_finalize(void);
243 
244 vaddr_t	pmap_map(vaddr_t, paddr_t, paddr_t, int);
245 void	pmap_procwr(struct proc *, vaddr_t, size_t);
246 #define	PMAP_NEED_PROCWR
247 
248 #ifdef CACHE_HAVE_VAC
249 void	pmap_prefer(vaddr_t, vaddr_t *);
250 #define	PMAP_PREFER(foff, vap, sz, td)	pmap_prefer((foff), (vap))
251 #endif
252 
253 void	_pmap_set_page_cacheable(struct pmap *, vaddr_t);
254 void	_pmap_set_page_cacheinhibit(struct pmap *, vaddr_t);
255 int	_pmap_page_is_cacheable(struct pmap *, vaddr_t);
256 
257 paddr_t	vtophys(vaddr_t va);
258 
259 #endif /* !_M68K_PMAP_MOTOROLA_H_ */
260