1 /* $NetBSD: piixide.c,v 1.67 2018/09/03 16:29:32 riastradh Exp $ */
2
3 /*
4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __KERNEL_RCSID(0, "$NetBSD: piixide.c,v 1.67 2018/09/03 16:29:32 riastradh Exp $");
29
30 #include <sys/param.h>
31 #include <sys/systm.h>
32
33 #include <dev/pci/pcivar.h>
34 #include <dev/pci/pcidevs.h>
35 #include <dev/pci/pciidereg.h>
36 #include <dev/pci/pciidevar.h>
37 #include <dev/pci/pciide_piix_reg.h>
38
39 static void piix_chip_map(struct pciide_softc*,
40 const struct pci_attach_args *);
41 static void piix_setup_channel(struct ata_channel *);
42 static void piix3_4_setup_channel(struct ata_channel *);
43 static u_int32_t piix_setup_idetim_timings(u_int8_t, u_int8_t, u_int8_t);
44 static u_int32_t piix_setup_idetim_drvs(struct ata_drive_datas *);
45 static u_int32_t piix_setup_sidetim_timings(u_int8_t, u_int8_t, u_int8_t);
46 static void piixsata_chip_map(struct pciide_softc*,
47 const struct pci_attach_args *);
48 static int piix_dma_init(void *, int, int, void *, size_t, int);
49
50 static bool piixide_resume(device_t, const pmf_qual_t *);
51 static bool piixide_suspend(device_t, const pmf_qual_t *);
52 static int piixide_match(device_t, cfdata_t, void *);
53 static void piixide_attach(device_t, device_t, void *);
54
55 static const struct pciide_product_desc pciide_intel_products[] = {
56 { PCI_PRODUCT_INTEL_82092AA,
57 0,
58 "Intel 82092AA IDE controller",
59 default_chip_map,
60 },
61 { PCI_PRODUCT_INTEL_82371FB_IDE,
62 0,
63 "Intel 82371FB IDE controller (PIIX)",
64 piix_chip_map,
65 },
66 { PCI_PRODUCT_INTEL_82371SB_IDE,
67 0,
68 "Intel 82371SB IDE Interface (PIIX3)",
69 piix_chip_map,
70 },
71 { PCI_PRODUCT_INTEL_82371AB_IDE,
72 0,
73 "Intel 82371AB IDE controller (PIIX4)",
74 piix_chip_map,
75 },
76 { PCI_PRODUCT_INTEL_82440MX_IDE,
77 0,
78 "Intel 82440MX IDE controller",
79 piix_chip_map
80 },
81 { PCI_PRODUCT_INTEL_82801AA_IDE,
82 0,
83 "Intel 82801AA IDE Controller (ICH)",
84 piix_chip_map,
85 },
86 { PCI_PRODUCT_INTEL_82801AB_IDE,
87 0,
88 "Intel 82801AB IDE Controller (ICH0)",
89 piix_chip_map,
90 },
91 { PCI_PRODUCT_INTEL_82801BA_IDE,
92 0,
93 "Intel 82801BA IDE Controller (ICH2)",
94 piix_chip_map,
95 },
96 { PCI_PRODUCT_INTEL_82801BAM_IDE,
97 0,
98 "Intel 82801BAM IDE Controller (ICH2-M)",
99 piix_chip_map,
100 },
101 { PCI_PRODUCT_INTEL_82801CA_IDE_1,
102 0,
103 "Intel 82801CA IDE Controller (ICH3)",
104 piix_chip_map,
105 },
106 { PCI_PRODUCT_INTEL_82801CA_IDE_2,
107 0,
108 "Intel 82801CA IDE Controller (ICH3)",
109 piix_chip_map,
110 },
111 { PCI_PRODUCT_INTEL_82801DB_IDE,
112 0,
113 "Intel 82801DB IDE Controller (ICH4)",
114 piix_chip_map,
115 },
116 { PCI_PRODUCT_INTEL_82801DBM_IDE,
117 0,
118 "Intel 82801DBM IDE Controller (ICH4-M)",
119 piix_chip_map,
120 },
121 { PCI_PRODUCT_INTEL_82801EB_IDE,
122 0,
123 "Intel 82801EB IDE Controller (ICH5)",
124 piix_chip_map,
125 },
126 { PCI_PRODUCT_INTEL_82801EB_SATA,
127 0,
128 "Intel 82801EB Serial ATA Controller",
129 piixsata_chip_map,
130 },
131 { PCI_PRODUCT_INTEL_82801ER_SATA,
132 0,
133 "Intel 82801ER Serial ATA/Raid Controller",
134 piixsata_chip_map,
135 },
136 { PCI_PRODUCT_INTEL_6300ESB_IDE,
137 0,
138 "Intel 6300ESB IDE Controller (ICH5)",
139 piix_chip_map,
140 },
141 { PCI_PRODUCT_INTEL_6300ESB_SATA,
142 0,
143 "Intel 6300ESB Serial ATA Controller",
144 piixsata_chip_map,
145 },
146 { PCI_PRODUCT_INTEL_6300ESB_RAID,
147 0,
148 "Intel 6300ESB Serial ATA/RAID Controller",
149 piixsata_chip_map,
150 },
151 { PCI_PRODUCT_INTEL_82801FB_IDE,
152 0,
153 "Intel 82801FB IDE Controller (ICH6)",
154 piix_chip_map,
155 },
156 { PCI_PRODUCT_INTEL_82801FB_SATA,
157 0,
158 "Intel 82801FB Serial ATA/Raid Controller",
159 piixsata_chip_map,
160 },
161 { PCI_PRODUCT_INTEL_82801FR_SATA,
162 0,
163 "Intel 82801FR Serial ATA/Raid Controller",
164 piixsata_chip_map,
165 },
166 { PCI_PRODUCT_INTEL_82801FBM_SATA,
167 0,
168 "Intel 82801FBM Serial ATA Controller (ICH6)",
169 piixsata_chip_map,
170 },
171 { PCI_PRODUCT_INTEL_82801G_IDE,
172 0,
173 "Intel 82801GB/GR IDE Controller (ICH7)",
174 piix_chip_map,
175 },
176 { PCI_PRODUCT_INTEL_82801G_SATA,
177 0,
178 "Intel 82801GB/GR Serial ATA/Raid Controller (ICH7)",
179 piixsata_chip_map,
180 },
181 { PCI_PRODUCT_INTEL_82801GBM_SATA,
182 0,
183 "Intel 82801GBM/GHM Serial ATA Controller (ICH7)",
184 piixsata_chip_map,
185 },
186 { PCI_PRODUCT_INTEL_82801H_SATA_1,
187 0,
188 "Intel 82801H Serial ATA Controller (ICH8)",
189 piixsata_chip_map,
190 },
191 { PCI_PRODUCT_INTEL_82801H_SATA_RAID,
192 0,
193 "Intel 82801H Serial ATA RAID Controller (ICH8)",
194 piixsata_chip_map,
195 },
196 { PCI_PRODUCT_INTEL_82801H_SATA_2,
197 0,
198 "Intel 82801H Serial ATA Controller (ICH8)",
199 piixsata_chip_map,
200 },
201 { PCI_PRODUCT_INTEL_82801HBM_IDE,
202 0,
203 "Intel 82801HBM IDE Controller (ICH8M)",
204 piix_chip_map,
205 },
206 { PCI_PRODUCT_INTEL_82801HBM_SATA_AHCI,
207 0,
208 "Intel 82801HBM Serial ATA AHCI Controller (ICH8M)",
209 piixsata_chip_map,
210 },
211 { PCI_PRODUCT_INTEL_82801HBM_SATA_RAID,
212 0,
213 "Intel 82801HBM Serial ATA RAID Controller (ICH8M)",
214 piixsata_chip_map,
215 },
216 { PCI_PRODUCT_INTEL_82801HEM_SATA,
217 0,
218 "Intel 82801HEM Serial ATA Controller (ICH8M)",
219 piixsata_chip_map,
220 },
221 { PCI_PRODUCT_INTEL_63XXESB_IDE,
222 0,
223 "Intel 631xESB/632xESB IDE Controller",
224 piix_chip_map,
225 },
226 { PCI_PRODUCT_INTEL_82801I_SATA_1,
227 0,
228 "Intel 82801I Serial ATA Controller (ICH9)",
229 piixsata_chip_map,
230 },
231 { PCI_PRODUCT_INTEL_82801I_SATA_2,
232 0,
233 "Intel 82801I Serial ATA Controller (ICH9)",
234 piixsata_chip_map,
235 },
236 { PCI_PRODUCT_INTEL_82801I_SATA_3,
237 0,
238 "Intel 82801I Serial ATA Controller (ICH9)",
239 piixsata_chip_map,
240 },
241 { PCI_PRODUCT_INTEL_82801I_SATA_4,
242 0,
243 "Intel 82801I Mobile Serial ATA Controller (ICH9)",
244 piixsata_chip_map,
245 },
246 { PCI_PRODUCT_INTEL_82801I_SATA_5,
247 0,
248 "Intel 82801I Mobile Serial ATA Controller (ICH9)",
249 piixsata_chip_map,
250 },
251 { PCI_PRODUCT_INTEL_82801I_SATA_6,
252 0,
253 "Intel 82801I Mobile Serial ATA Controller (ICH9)",
254 piixsata_chip_map,
255 },
256 { PCI_PRODUCT_INTEL_82801I_SATA_7,
257 0,
258 "Intel 82801I Mobile Serial ATA Controller (ICH9)",
259 piixsata_chip_map,
260 },
261 { PCI_PRODUCT_INTEL_63XXESB_SATA,
262 0,
263 "Intel 631xESB/632xESB Serial ATA Controller",
264 piixsata_chip_map,
265 },
266 { PCI_PRODUCT_INTEL_82801JD_SATA_IDE2,
267 0,
268 "Intel 82801JD Serial ATA Controller (ICH10)",
269 piixsata_chip_map,
270 },
271 { PCI_PRODUCT_INTEL_82801JI_SATA_IDE2,
272 0,
273 "Intel 82801JI Serial ATA Controller (ICH10)",
274 piixsata_chip_map,
275 },
276 { PCI_PRODUCT_INTEL_82801JD_SATA_IDE,
277 0,
278 "Intel 82801JD Serial ATA Controller (ICH10)",
279 piixsata_chip_map,
280 },
281 { PCI_PRODUCT_INTEL_82801JI_SATA_IDE,
282 0,
283 "Intel 82801JI Serial ATA Controller (ICH10)",
284 piixsata_chip_map,
285 },
286 {
287 PCI_PRODUCT_INTEL_82965PM_IDE,
288 0,
289 "Intel 82965PM IDE controller",
290 piixsata_chip_map,
291 },
292 { PCI_PRODUCT_INTEL_82Q45_IDER,
293 0,
294 "Intel 82Q45 IDE Redirection controller",
295 piixsata_chip_map,
296 },
297 {
298 PCI_PRODUCT_INTEL_3400_SATA_1,
299 0,
300 "Intel 3400 Serial ATA Controller",
301 piixsata_chip_map,
302 },
303 {
304 PCI_PRODUCT_INTEL_3400_SATA_1,
305 0,
306 "Intel 3400 Serial ATA Controller",
307 piixsata_chip_map,
308 },
309 {
310 PCI_PRODUCT_INTEL_3400_SATA_2,
311 0,
312 "Intel 3400 Serial ATA Controller",
313 piixsata_chip_map,
314 },
315 {
316 PCI_PRODUCT_INTEL_3400_SATA_3,
317 0,
318 "Intel 3400 Serial ATA Controller",
319 piixsata_chip_map,
320 },
321 {
322 PCI_PRODUCT_INTEL_3400_SATA_4,
323 0,
324 "Intel 3400 Serial ATA Controller",
325 piixsata_chip_map,
326 },
327 {
328 PCI_PRODUCT_INTEL_3400_SATA_5,
329 0,
330 "Intel 3400 Serial ATA Controller",
331 piixsata_chip_map,
332 },
333 {
334 PCI_PRODUCT_INTEL_3400_SATA_6,
335 0,
336 "Intel 3400 Serial ATA Controller",
337 piixsata_chip_map,
338 },
339 {
340 PCI_PRODUCT_INTEL_6SERIES_SATA_1,
341 0,
342 "Intel 6 Series Serial ATA Controller",
343 piixsata_chip_map,
344 },
345 {
346 PCI_PRODUCT_INTEL_6SERIES_SATA_2,
347 0,
348 "Intel 6 Series Serial ATA Controller",
349 piixsata_chip_map,
350 },
351 {
352 PCI_PRODUCT_INTEL_6SERIES_SATA_3,
353 0,
354 "Intel 6 Series Serial ATA Controller",
355 piixsata_chip_map,
356 },
357 {
358 PCI_PRODUCT_INTEL_6SERIES_SATA_4,
359 0,
360 "Intel 6 Series Serial ATA Controller",
361 piixsata_chip_map,
362 },
363 { 0,
364 0,
365 NULL,
366 NULL
367 }
368 };
369
370 CFATTACH_DECL_NEW(piixide, sizeof(struct pciide_softc),
371 piixide_match, piixide_attach, pciide_detach, NULL);
372
373 static int
piixide_match(device_t parent,cfdata_t match,void * aux)374 piixide_match(device_t parent, cfdata_t match, void *aux)
375 {
376 struct pci_attach_args *pa = aux;
377
378 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) {
379 if (pciide_lookup_product(pa->pa_id, pciide_intel_products))
380 return (2);
381 }
382 return (0);
383 }
384
385 static void
piixide_attach(device_t parent,device_t self,void * aux)386 piixide_attach(device_t parent, device_t self, void *aux)
387 {
388 struct pci_attach_args *pa = aux;
389 struct pciide_softc *sc = device_private(self);
390
391 sc->sc_wdcdev.sc_atac.atac_dev = self;
392
393 pciide_common_attach(sc, pa,
394 pciide_lookup_product(pa->pa_id, pciide_intel_products));
395
396 if (!pmf_device_register(self, piixide_suspend, piixide_resume))
397 aprint_error_dev(self, "couldn't establish power handler\n");
398 }
399
400 static bool
piixide_resume(device_t dv,const pmf_qual_t * qual)401 piixide_resume(device_t dv, const pmf_qual_t *qual)
402 {
403 struct pciide_softc *sc = device_private(dv);
404
405 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM,
406 sc->sc_pm_reg[0]);
407 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG,
408 sc->sc_pm_reg[1]);
409
410 return true;
411 }
412
413 static bool
piixide_suspend(device_t dv,const pmf_qual_t * qual)414 piixide_suspend(device_t dv, const pmf_qual_t *qual)
415 {
416 struct pciide_softc *sc = device_private(dv);
417
418 sc->sc_pm_reg[0] = pci_conf_read(sc->sc_pc, sc->sc_tag,
419 PIIX_IDETIM);
420 sc->sc_pm_reg[1] = pci_conf_read(sc->sc_pc, sc->sc_tag,
421 PIIX_UDMAREG);
422
423 return true;
424 }
425
426 static void
piix_chip_map(struct pciide_softc * sc,const struct pci_attach_args * pa)427 piix_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa)
428 {
429 struct pciide_channel *cp;
430 int channel;
431 u_int32_t idetim;
432 pcireg_t interface = PCI_INTERFACE(pa->pa_class);
433
434 if (pciide_chipen(sc, pa) == 0)
435 return;
436
437 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
438 "bus-master DMA support present");
439 pciide_mapreg_dma(sc, pa);
440 aprint_verbose("\n");
441 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
442 if (sc->sc_dma_ok) {
443 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
444 sc->sc_wdcdev.irqack = pciide_irqack;
445 /* Do all revisions require DMA alignment workaround? */
446 sc->sc_wdcdev.dma_init = piix_dma_init;
447 switch(sc->sc_pp->ide_product) {
448 case PCI_PRODUCT_INTEL_82371AB_IDE:
449 case PCI_PRODUCT_INTEL_82440MX_IDE:
450 case PCI_PRODUCT_INTEL_82801AA_IDE:
451 case PCI_PRODUCT_INTEL_82801AB_IDE:
452 case PCI_PRODUCT_INTEL_82801BA_IDE:
453 case PCI_PRODUCT_INTEL_82801BAM_IDE:
454 case PCI_PRODUCT_INTEL_82801CA_IDE_1:
455 case PCI_PRODUCT_INTEL_82801CA_IDE_2:
456 case PCI_PRODUCT_INTEL_82801DB_IDE:
457 case PCI_PRODUCT_INTEL_82801DBM_IDE:
458 case PCI_PRODUCT_INTEL_82801EB_IDE:
459 case PCI_PRODUCT_INTEL_6300ESB_IDE:
460 case PCI_PRODUCT_INTEL_82801FB_IDE:
461 case PCI_PRODUCT_INTEL_82801G_IDE:
462 case PCI_PRODUCT_INTEL_82801HBM_IDE:
463 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA;
464 }
465 }
466 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
467 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
468 switch(sc->sc_pp->ide_product) {
469 case PCI_PRODUCT_INTEL_82801AA_IDE:
470 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
471 break;
472 case PCI_PRODUCT_INTEL_82801BA_IDE:
473 case PCI_PRODUCT_INTEL_82801BAM_IDE:
474 case PCI_PRODUCT_INTEL_82801CA_IDE_1:
475 case PCI_PRODUCT_INTEL_82801CA_IDE_2:
476 case PCI_PRODUCT_INTEL_82801DB_IDE:
477 case PCI_PRODUCT_INTEL_82801DBM_IDE:
478 case PCI_PRODUCT_INTEL_82801EB_IDE:
479 case PCI_PRODUCT_INTEL_6300ESB_IDE:
480 case PCI_PRODUCT_INTEL_82801FB_IDE:
481 case PCI_PRODUCT_INTEL_82801G_IDE:
482 case PCI_PRODUCT_INTEL_82801HBM_IDE:
483 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
484 break;
485 default:
486 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
487 }
488 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE)
489 sc->sc_wdcdev.sc_atac.atac_set_modes = piix_setup_channel;
490 else
491 sc->sc_wdcdev.sc_atac.atac_set_modes = piix3_4_setup_channel;
492 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
493 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
494 sc->sc_wdcdev.wdc_maxdrives = 2;
495
496 ATADEBUG_PRINT(("piix_setup_chip: old idetim=0x%x",
497 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)),
498 DEBUG_PROBE);
499 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) {
500 ATADEBUG_PRINT((", sidetim=0x%x",
501 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)),
502 DEBUG_PROBE);
503 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) {
504 ATADEBUG_PRINT((", udamreg 0x%x",
505 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)),
506 DEBUG_PROBE);
507 }
508 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE ||
509 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE ||
510 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE ||
511 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE ||
512 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 ||
513 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 ||
514 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE ||
515 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE ||
516 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE ||
517 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE ||
518 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE ||
519 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE ||
520 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) {
521 ATADEBUG_PRINT((", IDE_CONTROL 0x%x",
522 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)),
523 DEBUG_PROBE);
524 }
525
526 }
527 ATADEBUG_PRINT(("\n"), DEBUG_PROBE);
528
529 wdc_allocate_regs(&sc->sc_wdcdev);
530
531 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
532 channel++) {
533 cp = &sc->pciide_channels[channel];
534 if (pciide_chansetup(sc, channel, interface) == 0)
535 continue;
536 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM);
537 if ((PIIX_IDETIM_READ(idetim, channel) &
538 PIIX_IDETIM_IDE) == 0) {
539 #if 1
540 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
541 "%s channel ignored (disabled)\n", cp->name);
542 cp->ata_channel.ch_flags |= ATACH_DISABLED;
543 continue;
544 #else
545 pcireg_t interface;
546
547 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE,
548 channel);
549 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM,
550 idetim);
551 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc,
552 sc->sc_tag, PCI_CLASS_REG));
553 aprint_normal("channel %d idetim=%08x interface=%02x\n",
554 channel, idetim, interface);
555 #endif
556 }
557 pciide_mapchan(pa, cp, interface, pciide_pci_intr);
558 }
559
560 ATADEBUG_PRINT(("piix_setup_chip: idetim=0x%x",
561 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)),
562 DEBUG_PROBE);
563 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) {
564 ATADEBUG_PRINT((", sidetim=0x%x",
565 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)),
566 DEBUG_PROBE);
567 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) {
568 ATADEBUG_PRINT((", udamreg 0x%x",
569 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)),
570 DEBUG_PROBE);
571 }
572 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE ||
573 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE ||
574 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE ||
575 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE ||
576 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 ||
577 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 ||
578 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE ||
579 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE ||
580 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE ||
581 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE ||
582 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE ||
583 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE ||
584 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) {
585 ATADEBUG_PRINT((", IDE_CONTROL 0x%x",
586 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)),
587 DEBUG_PROBE);
588 }
589 }
590 ATADEBUG_PRINT(("\n"), DEBUG_PROBE);
591 }
592
593 static void
piix_setup_channel(struct ata_channel * chp)594 piix_setup_channel(struct ata_channel *chp)
595 {
596 u_int8_t mode[2], drive;
597 u_int32_t oidetim, idetim, idedma_ctl;
598 struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
599 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
600 struct ata_drive_datas *drvp = cp->ata_channel.ch_drive;
601
602 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM);
603 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->ch_channel);
604 idedma_ctl = 0;
605
606 /* set up new idetim: Enable IDE registers decode */
607 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE,
608 chp->ch_channel);
609
610 /* setup DMA */
611 pciide_channel_dma_setup(cp);
612
613 /*
614 * Here we have to mess up with drives mode: PIIX can't have
615 * different timings for master and slave drives.
616 * We need to find the best combination.
617 */
618
619 /* If both drives supports DMA, take the lower mode */
620 if ((drvp[0].drive_flags & ATA_DRIVE_DMA) &&
621 (drvp[1].drive_flags & ATA_DRIVE_DMA)) {
622 mode[0] = mode[1] =
623 uimin(drvp[0].DMA_mode, drvp[1].DMA_mode);
624 drvp[0].DMA_mode = mode[0];
625 drvp[1].DMA_mode = mode[1];
626 goto ok;
627 }
628 /*
629 * If only one drive supports DMA, use its mode, and
630 * put the other one in PIO mode 0 if mode not compatible
631 */
632 if (drvp[0].drive_flags & ATA_DRIVE_DMA) {
633 mode[0] = drvp[0].DMA_mode;
634 mode[1] = drvp[1].PIO_mode;
635 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] ||
636 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]])
637 mode[1] = drvp[1].PIO_mode = 0;
638 goto ok;
639 }
640 if (drvp[1].drive_flags & ATA_DRIVE_DMA) {
641 mode[1] = drvp[1].DMA_mode;
642 mode[0] = drvp[0].PIO_mode;
643 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] ||
644 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]])
645 mode[0] = drvp[0].PIO_mode = 0;
646 goto ok;
647 }
648 /*
649 * If both drives are not DMA, takes the lower mode, unless
650 * one of them is PIO mode < 2
651 */
652 if (drvp[0].PIO_mode < 2) {
653 mode[0] = drvp[0].PIO_mode = 0;
654 mode[1] = drvp[1].PIO_mode;
655 } else if (drvp[1].PIO_mode < 2) {
656 mode[1] = drvp[1].PIO_mode = 0;
657 mode[0] = drvp[0].PIO_mode;
658 } else {
659 mode[0] = mode[1] =
660 uimin(drvp[1].PIO_mode, drvp[0].PIO_mode);
661 drvp[0].PIO_mode = mode[0];
662 drvp[1].PIO_mode = mode[1];
663 }
664 ok: /* The modes are setup */
665 for (drive = 0; drive < 2; drive++) {
666 if (drvp[drive].drive_flags & ATA_DRIVE_DMA) {
667 idetim |= piix_setup_idetim_timings(
668 mode[drive], 1, chp->ch_channel);
669 goto end;
670 }
671 }
672 /* If we are there, none of the drives are DMA */
673 if (mode[0] >= 2)
674 idetim |= piix_setup_idetim_timings(
675 mode[0], 0, chp->ch_channel);
676 else
677 idetim |= piix_setup_idetim_timings(
678 mode[1], 0, chp->ch_channel);
679 end: /*
680 * timing mode is now set up in the controller. Enable
681 * it per-drive
682 */
683 for (drive = 0; drive < 2; drive++) {
684 /* If no drive, skip */
685 if (drvp[drive].drive_type == ATA_DRIVET_NONE)
686 continue;
687 idetim |= piix_setup_idetim_drvs(&drvp[drive]);
688 if (drvp[drive].drive_flags & ATA_DRIVE_DMA)
689 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
690 }
691 if (idedma_ctl != 0) {
692 /* Add software bits in status register */
693 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
694 idedma_ctl);
695 }
696 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim);
697 }
698
699 static void
piix3_4_setup_channel(struct ata_channel * chp)700 piix3_4_setup_channel(struct ata_channel *chp)
701 {
702 struct ata_drive_datas *drvp;
703 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl;
704 struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
705 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
706 struct wdc_softc *wdc = &sc->sc_wdcdev;
707 int drive, s;
708 int channel = chp->ch_channel;
709
710 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM);
711 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM);
712 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG);
713 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG);
714 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel);
715 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) |
716 PIIX_SIDETIM_RTC_MASK(channel));
717 idedma_ctl = 0;
718
719 /* set up new idetim: Enable IDE registers decode */
720 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel);
721
722 /* setup DMA if needed */
723 pciide_channel_dma_setup(cp);
724
725 for (drive = 0; drive < 2; drive++) {
726 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) |
727 PIIX_UDMATIM_SET(0x3, channel, drive));
728 drvp = &chp->ch_drive[drive];
729 /* If no drive, skip */
730 if (drvp->drive_type == ATA_DRIVET_NONE)
731 continue;
732 if (((drvp->drive_flags & ATA_DRIVE_DMA) == 0 &&
733 (drvp->drive_flags & ATA_DRIVE_UDMA) == 0))
734 goto pio;
735
736 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE ||
737 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE ||
738 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE ||
739 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE ||
740 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 ||
741 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 ||
742 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE ||
743 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE ||
744 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE ||
745 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE ||
746 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE ||
747 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE ||
748 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) {
749 ideconf |= PIIX_CONFIG_PINGPONG;
750 }
751 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE ||
752 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE ||
753 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 ||
754 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 ||
755 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE ||
756 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE ||
757 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE ||
758 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE ||
759 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE ||
760 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE ||
761 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) {
762 /* setup Ultra/100 */
763 if (drvp->UDMA_mode > 2 &&
764 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0)
765 drvp->UDMA_mode = 2;
766 if (drvp->UDMA_mode > 4) {
767 ideconf |= PIIX_CONFIG_UDMA100(channel, drive);
768 } else {
769 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive);
770 if (drvp->UDMA_mode > 2) {
771 ideconf |= PIIX_CONFIG_UDMA66(channel,
772 drive);
773 } else {
774 ideconf &= ~PIIX_CONFIG_UDMA66(channel,
775 drive);
776 }
777 }
778 }
779 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) {
780 /* setup Ultra/66 */
781 if (drvp->UDMA_mode > 2 &&
782 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0)
783 drvp->UDMA_mode = 2;
784 if (drvp->UDMA_mode > 2)
785 ideconf |= PIIX_CONFIG_UDMA66(channel, drive);
786 else
787 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive);
788 }
789 if ((wdc->sc_atac.atac_cap & ATAC_CAP_UDMA) &&
790 (drvp->drive_flags & ATA_DRIVE_UDMA)) {
791 /* use Ultra/DMA */
792 s = splbio();
793 drvp->drive_flags &= ~ATA_DRIVE_DMA;
794 splx(s);
795 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive);
796 udmareg |= PIIX_UDMATIM_SET(
797 piix4_sct_udma[drvp->UDMA_mode], channel, drive);
798 } else {
799 /* use Multiword DMA */
800 s = splbio();
801 drvp->drive_flags &= ~ATA_DRIVE_UDMA;
802 splx(s);
803 if (drive == 0) {
804 idetim |= piix_setup_idetim_timings(
805 drvp->DMA_mode, 1, channel);
806 } else {
807 sidetim |= piix_setup_sidetim_timings(
808 drvp->DMA_mode, 1, channel);
809 idetim =PIIX_IDETIM_SET(idetim,
810 PIIX_IDETIM_SITRE, channel);
811 }
812 }
813 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
814
815 pio: /* use PIO mode */
816 idetim |= piix_setup_idetim_drvs(drvp);
817 if (drive == 0) {
818 idetim |= piix_setup_idetim_timings(
819 drvp->PIO_mode, 0, channel);
820 } else {
821 sidetim |= piix_setup_sidetim_timings(
822 drvp->PIO_mode, 0, channel);
823 idetim =PIIX_IDETIM_SET(idetim,
824 PIIX_IDETIM_SITRE, channel);
825 }
826 }
827 if (idedma_ctl != 0) {
828 /* Add software bits in status register */
829 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
830 idedma_ctl);
831 }
832 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim);
833 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim);
834 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg);
835 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf);
836 }
837
838
839 /* setup ISP and RTC fields, based on mode */
840 static u_int32_t
piix_setup_idetim_timings(u_int8_t mode,u_int8_t dma,u_int8_t channel)841 piix_setup_idetim_timings(u_int8_t mode, u_int8_t dma, u_int8_t channel)
842 {
843
844 if (dma)
845 return PIIX_IDETIM_SET(0,
846 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) |
847 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]),
848 channel);
849 else
850 return PIIX_IDETIM_SET(0,
851 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) |
852 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]),
853 channel);
854 }
855
856 /* setup DTE, PPE, IE and TIME field based on PIO mode */
857 static u_int32_t
piix_setup_idetim_drvs(struct ata_drive_datas * drvp)858 piix_setup_idetim_drvs(struct ata_drive_datas *drvp)
859 {
860 u_int32_t ret = 0;
861 struct ata_channel *chp = drvp->chnl_softc;
862 u_int8_t channel = chp->ch_channel;
863 u_int8_t drive = drvp->drive;
864
865 /*
866 * If drive is using UDMA, timings setups are independent
867 * So just check DMA and PIO here.
868 */
869 if (drvp->drive_flags & ATA_DRIVE_DMA) {
870 /* if mode = DMA mode 0, use compatible timings */
871 if ((drvp->drive_flags & ATA_DRIVE_DMA) &&
872 drvp->DMA_mode == 0) {
873 drvp->PIO_mode = 0;
874 return ret;
875 }
876 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel);
877 /*
878 * PIO and DMA timings are the same, use fast timings for PIO
879 * too, else use compat timings.
880 */
881 if ((piix_isp_pio[drvp->PIO_mode] !=
882 piix_isp_dma[drvp->DMA_mode]) ||
883 (piix_rtc_pio[drvp->PIO_mode] !=
884 piix_rtc_dma[drvp->DMA_mode]))
885 drvp->PIO_mode = 0;
886 /* if PIO mode <= 2, use compat timings for PIO */
887 if (drvp->PIO_mode <= 2) {
888 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive),
889 channel);
890 return ret;
891 }
892 }
893
894 /*
895 * Now setup PIO modes. If mode < 2, use compat timings.
896 * Else enable fast timings. Enable IORDY and prefetch/post
897 * if PIO mode >= 3.
898 */
899
900 if (drvp->PIO_mode < 2)
901 return ret;
902
903 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel);
904 if (drvp->PIO_mode >= 3) {
905 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel);
906 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel);
907 }
908 return ret;
909 }
910
911 /* setup values in SIDETIM registers, based on mode */
912 static u_int32_t
piix_setup_sidetim_timings(u_int8_t mode,u_int8_t dma,u_int8_t channel)913 piix_setup_sidetim_timings(u_int8_t mode, u_int8_t dma, u_int8_t channel)
914 {
915 if (dma)
916 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) |
917 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel);
918 else
919 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) |
920 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel);
921 }
922
923 static void
piixsata_chip_map(struct pciide_softc * sc,const struct pci_attach_args * pa)924 piixsata_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa)
925 {
926 struct pciide_channel *cp;
927 pcireg_t interface, cmdsts;
928 int channel;
929
930 if (pciide_chipen(sc, pa) == 0)
931 return;
932
933 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
934 "bus-master DMA support present");
935 pciide_mapreg_dma(sc, pa);
936 aprint_verbose("\n");
937
938 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
939 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
940 if (sc->sc_dma_ok) {
941 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
942 sc->sc_wdcdev.irqack = pciide_irqack;
943 /* Do all revisions require DMA alignment workaround? */
944 sc->sc_wdcdev.dma_init = piix_dma_init;
945 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
946 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
947 }
948 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel;
949
950 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
951 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
952 sc->sc_wdcdev.wdc_maxdrives = 2;
953
954 cmdsts = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG);
955 cmdsts &= ~PCI_COMMAND_INTERRUPT_DISABLE;
956 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, cmdsts);
957
958 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE &&
959 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID)
960 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID;
961
962 interface = PCI_INTERFACE(pa->pa_class);
963
964 wdc_allocate_regs(&sc->sc_wdcdev);
965
966 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
967 channel++) {
968 cp = &sc->pciide_channels[channel];
969 if (pciide_chansetup(sc, channel, interface) == 0)
970 continue;
971 pciide_mapchan(pa, cp, interface, pciide_pci_intr);
972 }
973 }
974
975 static int
piix_dma_init(void * v,int channel,int drive,void * databuf,size_t datalen,int flags)976 piix_dma_init(void *v, int channel, int drive, void *databuf,
977 size_t datalen, int flags)
978 {
979
980 /* use PIO for unaligned transfer */
981 if (((uintptr_t)databuf) & 0x1)
982 return EINVAL;
983
984 return pciide_dma_init(v, channel, drive, databuf, datalen, flags);
985 }
986