1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018-2020 NXP 3 */ 4 5 #ifndef _ENETC_HW_H_ 6 #define _ENETC_HW_H_ 7 #include <rte_io.h> 8 9 #define BIT(x) ((uint64_t)1 << ((x))) 10 11 /* ENETC device IDs */ 12 #define ENETC_DEV_ID_VF 0xef00 13 #define ENETC_DEV_ID 0xe100 14 15 /* BD RING ALIGNMENT */ 16 #define ENETC_BD_RING_ALIGN 128 17 18 /* ENETC register block BAR */ 19 #define ENETC_BAR_REGS 0x0 20 21 /* SI regs, offset: 0h */ 22 #define ENETC_SIMR 0x0 23 #define ENETC_SIMR_EN BIT(31) 24 25 #define ENETC_SICAR0 0x40 26 #define ENETC_SICAR0_COHERENT 0x2B2B6727 27 #define ENETC_SIPMAR0 0x80 28 #define ENETC_SIPMAR1 0x84 29 30 #define ENETC_SICAPR0 0x900 31 #define ENETC_SICAPR1 0x904 32 33 #define ENETC_SIMSITRV(n) (0xB00 + (n) * 0x4) 34 #define ENETC_SIMSIRRV(n) (0xB80 + (n) * 0x4) 35 36 #define ENETC_SICCAPR 0x1200 37 38 /* enum for BD type */ 39 enum enetc_bdr_type {TX, RX}; 40 41 #define ENETC_BDR(type, n, off) (0x8000 + (type) * 0x100 + (n) * 0x200 \ 42 + (off)) 43 /* RX BDR reg offsets */ 44 #define ENETC_RBMR 0x0 /* RX BDR mode register*/ 45 #define ENETC_RBMR_EN BIT(31) 46 47 #define ENETC_RBSR 0x4 /* Rx BDR status register*/ 48 #define ENETC_RBBSR 0x8 /* Rx BDR buffer size register*/ 49 #define ENETC_RBCIR 0xc /* Rx BDR consumer index register*/ 50 #define ENETC_RBBAR0 0x10 /* Rx BDR base address register 0 */ 51 #define ENETC_RBBAR1 0x14 /* Rx BDR base address register 1*/ 52 #define ENETC_RBPIR 0x18 /* Rx BDR producer index register*/ 53 #define ENETC_RBLENR 0x20 /* Rx BDR length register*/ 54 #define ENETC_RBIER 0xa0 /* Rx BDR interrupt enable register*/ 55 #define ENETC_RBIER_RXTIE BIT(0) 56 #define ENETC_RBIDR 0xa4 /* Rx BDR interrupt detect register*/ 57 #define ENETC_RBICIR0 0xa8 /* Rx BDR inetrrupt coalescing register 0*/ 58 #define ENETC_RBICIR0_ICEN BIT(31) 59 60 61 #define ENETC_TBMR 0x0 /* Tx BDR mode register (TBMR) 32 RW */ 62 #define ENETC_TBSR 0x4 /* x BDR status register (TBSR) 32 RO */ 63 #define ENETC_TBBAR0 0x10 /* Tx BDR base address register 0 (TBBAR0) 32 RW */ 64 #define ENETC_TBBAR1 0x14 /* Tx BDR base address register 1 (TBBAR1) 32 RW */ 65 #define ENETC_TBCIR 0x18 /* Tx BDR consumer index register (TBCIR) 32 RW */ 66 #define ENETC_TBCISR 0x1C /* Tx BDR consumer index shadow register 32 RW */ 67 #define ENETC_TBIER 0xA0 /* Tx BDR interrupt enable register 32 RW */ 68 #define ENETC_TBIDR 0xA4 /* Tx BDR interrupt detect register 32 RO */ 69 #define ENETC_TBICR0 0xA8 /* Tx BDR interrupt coalescing register 0 32 RW */ 70 #define ENETC_TBICR1 0xAC /* Tx BDR interrupt coalescing register 1 32 RW */ 71 #define ENETC_TBLENR 0x20 72 73 #define ENETC_TBCISR_IDX_MASK 0xffff 74 #define ENETC_TBIER_TXFIE BIT(1) 75 76 #define ENETC_RTBLENR_LEN(n) ((n) & ~0x7) 77 #define ENETC_TBMR_EN BIT(31) 78 79 /* Port regs, offset: 1_0000h */ 80 #define ENETC_PORT_BASE 0x10000 81 #define ENETC_PMR 0x00000 82 #define ENETC_PMR_EN (BIT(16) | BIT(17) | BIT(18)) 83 #define ENETC_PSR 0x00004 /* RO */ 84 #define ENETC_PSIPMR 0x00018 85 #define ENETC_PSIPMR_SET_UP(n) (0x1 << (n)) /* n = SI index */ 86 #define ENETC_PSIPMR_SET_MP(n) (0x1 << ((n) + 16)) 87 #define ENETC_PSIPMAR0(n) (0x00100 + (n) * 0x20) 88 #define ENETC_PSIPMAR1(n) (0x00104 + (n) * 0x20) 89 #define ENETC_PCAPR0 0x00900 90 #define ENETC_PCAPR1 0x00904 91 #define ENETC_PM0_RX_FIFO 0x801C 92 #define ENETC_PM0_IF_MODE 0x8300 93 #define ENETC_PM1_IF_MODE 0x9300 94 #define ENETC_PMO_IFM_RG BIT(2) 95 #define ENETC_PM0_IFM_RLP (BIT(5) | BIT(11)) 96 #define ENETC_PM0_IFM_RGAUTO (BIT(15) | ENETC_PMO_IFM_RG | BIT(1)) 97 #define ENETC_PM0_IFM_XGMII BIT(12) 98 99 #define ENETC_PV0CFGR(n) (0x00920 + (n) * 0x10) 100 #define ENETC_PVCFGR_SET_TXBDR(val) ((val) & 0xff) 101 #define ENETC_PVCFGR_SET_RXBDR(val) (((val) & 0xff) << 16) 102 103 #define ENETC_PM0_CMD_CFG 0x08008 104 #define ENETC_PM0_TX_EN BIT(0) 105 #define ENETC_PM0_RX_EN BIT(1) 106 #define ENETC_PM0_CRC BIT(6) 107 108 #define ENETC_PAR_PORT_CFG 0x03050 109 #define L3_CKSUM BIT(0) 110 #define L4_CKSUM BIT(1) 111 112 #define ENETC_PM0_MAXFRM 0x08014 113 #define ENETC_SET_TX_MTU(val) ((val) << 16) 114 #define ENETC_SET_MAXFRM(val) ((val) & 0xffff) 115 #define ENETC_PTXMBAR 0x0608 116 /* n = TC index [0..7] */ 117 #define ENETC_PTCMSDUR(n) (0x2020 + (n) * 4) 118 119 #define ENETC_PM0_STATUS 0x08304 120 #define ENETC_LINK_MODE 0x0000000000080000ULL 121 #define ENETC_LINK_STATUS 0x0000000000010000ULL 122 #define ENETC_LINK_SPEED_MASK 0x0000000000060000ULL 123 #define ENETC_LINK_SPEED_10M 0x0ULL 124 #define ENETC_LINK_SPEED_100M 0x0000000000020000ULL 125 #define ENETC_LINK_SPEED_1G 0x0000000000040000ULL 126 127 /* Global regs, offset: 2_0000h */ 128 #define ENETC_GLOBAL_BASE 0x20000 129 #define ENETC_G_EIPBRR0 0x00bf8 130 #define ENETC_G_EIPBRR1 0x00bfc 131 132 /* MAC Counters */ 133 /* Config register to reset counters*/ 134 #define ENETC_PM0_STAT_CONFIG 0x080E0 135 /* Receive frames counter without error */ 136 #define ENETC_PM0_RFRM 0x08120 137 /* Receive packets counter, good + bad */ 138 #define ENETC_PM0_RPKT 0x08160 139 /* Received octets, good + bad */ 140 #define ENETC_PM0_REOCT 0x08120 141 /* Transmit octets, good + bad */ 142 #define ENETC_PM0_TEOCT 0x08200 143 /* Transmit frames counter without error */ 144 #define ENETC_PM0_TFRM 0x08220 145 /* Transmit packets counter, good + bad */ 146 #define ENETC_PM0_TPKT 0x08260 147 /* Dropped not Truncated packets counter */ 148 #define ENETC_PM0_RDRNTP 0x081C8 149 /* Dropped + trucated packets counter */ 150 #define ENETC_PM0_RDRP 0x08158 151 /* Receive packets error counter */ 152 #define ENETC_PM0_RERR 0x08138 153 /* Transmit packets error counter */ 154 #define ENETC_PM0_TERR 0x08238 155 156 /* Stats Reset Bit*/ 157 #define ENETC_CLEAR_STATS BIT(2) 158 159 #define ENETC_G_EPFBLPR(n) (0xd00 + 4 * (n)) 160 #define ENETC_G_EPFBLPR1_XGMII 0x80000000 161 162 /* general register accessors */ 163 #define enetc_rd_reg(reg) rte_read32((void *)(reg)) 164 #define enetc_wr_reg(reg, val) rte_write32((val), (void *)(reg)) 165 #define enetc_rd(hw, off) enetc_rd_reg((size_t)(hw)->reg + (off)) 166 #define enetc_wr(hw, off, val) enetc_wr_reg((size_t)(hw)->reg + (off), val) 167 /* port register accessors - PF only */ 168 #define enetc_port_rd(hw, off) enetc_rd_reg((size_t)(hw)->port + (off)) 169 #define enetc_port_wr(hw, off, val) \ 170 enetc_wr_reg((size_t)(hw)->port + (off), val) 171 /* global register accessors - PF only */ 172 #define enetc_global_rd(hw, off) \ 173 enetc_rd_reg((size_t)(hw)->global + (off)) 174 #define enetc_global_wr(hw, off, val) \ 175 enetc_wr_reg((size_t)(hw)->global + (off), val) 176 /* BDR register accessors, see ENETC_BDR() */ 177 #define enetc_bdr_rd(hw, t, n, off) \ 178 enetc_rd(hw, ENETC_BDR(t, n, off)) 179 #define enetc_bdr_wr(hw, t, n, off, val) \ 180 enetc_wr(hw, ENETC_BDR(t, n, off), val) 181 182 #define enetc_txbdr_rd(hw, n, off) enetc_bdr_rd(hw, TX, n, off) 183 #define enetc_rxbdr_rd(hw, n, off) enetc_bdr_rd(hw, RX, n, off) 184 #define enetc_txbdr_wr(hw, n, off, val) \ 185 enetc_bdr_wr(hw, TX, n, off, val) 186 #define enetc_rxbdr_wr(hw, n, off, val) \ 187 enetc_bdr_wr(hw, RX, n, off, val) 188 189 #define ENETC_TX_ADDR(txq, addr) ((void *)((txq)->enetc_txbdr + (addr))) 190 191 #define ENETC_TXBD_FLAGS_IE BIT(13) 192 #define ENETC_TXBD_FLAGS_F BIT(15) 193 194 /* ENETC Parsed values (Little Endian) */ 195 #define ENETC_PARSE_ERROR 0x8000 196 #define ENETC_PKT_TYPE_ETHER 0x0060 197 #define ENETC_PKT_TYPE_IPV4 0x0000 198 #define ENETC_PKT_TYPE_IPV6 0x0020 199 #define ENETC_PKT_TYPE_IPV4_TCP \ 200 (0x0010 | ENETC_PKT_TYPE_IPV4) 201 #define ENETC_PKT_TYPE_IPV6_TCP \ 202 (0x0010 | ENETC_PKT_TYPE_IPV6) 203 #define ENETC_PKT_TYPE_IPV4_UDP \ 204 (0x0011 | ENETC_PKT_TYPE_IPV4) 205 #define ENETC_PKT_TYPE_IPV6_UDP \ 206 (0x0011 | ENETC_PKT_TYPE_IPV6) 207 #define ENETC_PKT_TYPE_IPV4_SCTP \ 208 (0x0013 | ENETC_PKT_TYPE_IPV4) 209 #define ENETC_PKT_TYPE_IPV6_SCTP \ 210 (0x0013 | ENETC_PKT_TYPE_IPV6) 211 #define ENETC_PKT_TYPE_IPV4_ICMP \ 212 (0x0003 | ENETC_PKT_TYPE_IPV4) 213 #define ENETC_PKT_TYPE_IPV6_ICMP \ 214 (0x0003 | ENETC_PKT_TYPE_IPV6) 215 216 /* PCI device info */ 217 struct enetc_hw { 218 void *reg; /* SI registers, used by all PCI functions */ 219 void *port; /* Port registers, PF only */ 220 void *global; /* IP global registers, PF only */ 221 }; 222 223 struct enetc_eth_mac_info { 224 uint8_t addr[RTE_ETHER_ADDR_LEN]; 225 uint8_t perm_addr[RTE_ETHER_ADDR_LEN]; 226 uint8_t get_link_status; 227 }; 228 229 struct enetc_eth_hw { 230 struct rte_eth_dev *ndev; 231 struct enetc_hw hw; 232 uint16_t device_id; 233 uint16_t vendor_id; 234 uint8_t revision_id; 235 struct enetc_eth_mac_info mac; 236 }; 237 238 /* Transmit Descriptor */ 239 struct enetc_tx_desc { 240 uint64_t addr; 241 uint16_t frm_len; 242 uint16_t buf_len; 243 uint32_t flags_errors; 244 }; 245 246 /* TX Buffer Descriptors (BD) */ 247 struct enetc_tx_bd { 248 uint64_t addr; 249 uint16_t buf_len; 250 uint16_t frm_len; 251 uint16_t err_csum; 252 uint16_t flags; 253 }; 254 255 /* RX buffer descriptor */ 256 union enetc_rx_bd { 257 struct { 258 uint64_t addr; 259 uint8_t reserved[8]; 260 } w; 261 struct { 262 uint16_t inet_csum; 263 uint16_t parse_summary; 264 uint32_t rss_hash; 265 uint16_t buf_len; 266 uint16_t vlan_opt; 267 union { 268 struct { 269 uint16_t flags; 270 uint16_t error; 271 }; 272 uint32_t lstatus; 273 }; 274 } r; 275 }; 276 277 #endif 278