1 /* Subroutines for insn-output.c for HPPA.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003 Free Software Foundation, Inc.
4 Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c
5
6 This file is part of GNU CC.
7
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
22
23 #include "config.h"
24 #include "system.h"
25 #include "rtl.h"
26 #include "regs.h"
27 #include "hard-reg-set.h"
28 #include "real.h"
29 #include "insn-config.h"
30 #include "conditions.h"
31 #include "insn-attr.h"
32 #include "flags.h"
33 #include "tree.h"
34 #include "output.h"
35 #include "except.h"
36 #include "expr.h"
37 #include "optabs.h"
38 #include "libfuncs.h"
39 #include "reload.h"
40 #include "c-tree.h"
41 #include "integrate.h"
42 #include "function.h"
43 #include "obstack.h"
44 #include "toplev.h"
45 #include "ggc.h"
46 #include "recog.h"
47 #include "predict.h"
48 #include "tm_p.h"
49 #include "target.h"
50 #include "target-def.h"
51
52 static int hppa_use_dfa_pipeline_interface PARAMS ((void));
53
54 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
55 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE hppa_use_dfa_pipeline_interface
56
57 static int
hppa_use_dfa_pipeline_interface()58 hppa_use_dfa_pipeline_interface ()
59 {
60 return 1;
61 }
62
63 /* Return nonzero if there is a bypass for the output of
64 OUT_INSN and the fp store IN_INSN. */
65 int
hppa_fpstore_bypass_p(out_insn,in_insn)66 hppa_fpstore_bypass_p (out_insn, in_insn)
67 rtx out_insn, in_insn;
68 {
69 enum machine_mode store_mode;
70 enum machine_mode other_mode;
71 rtx set;
72
73 if (recog_memoized (in_insn) < 0
74 || get_attr_type (in_insn) != TYPE_FPSTORE
75 || recog_memoized (out_insn) < 0)
76 return 0;
77
78 store_mode = GET_MODE (SET_SRC (PATTERN (in_insn)));
79
80 set = single_set (out_insn);
81 if (!set)
82 return 0;
83
84 other_mode = GET_MODE (SET_SRC (set));
85
86 return (GET_MODE_SIZE (store_mode) == GET_MODE_SIZE (other_mode));
87 }
88
89
90 #ifndef DO_FRAME_NOTES
91 #ifdef INCOMING_RETURN_ADDR_RTX
92 #define DO_FRAME_NOTES 1
93 #else
94 #define DO_FRAME_NOTES 0
95 #endif
96 #endif
97
98 static inline rtx force_mode PARAMS ((enum machine_mode, rtx));
99 static void pa_combine_instructions PARAMS ((rtx));
100 static int pa_can_combine_p PARAMS ((rtx, rtx, rtx, int, rtx, rtx, rtx));
101 static int forward_branch_p PARAMS ((rtx));
102 static int shadd_constant_p PARAMS ((int));
103 static void compute_zdepwi_operands PARAMS ((unsigned HOST_WIDE_INT, unsigned *));
104 static int compute_movstrsi_length PARAMS ((rtx));
105 static bool pa_assemble_integer PARAMS ((rtx, unsigned int, int));
106 static void remove_useless_addtr_insns PARAMS ((rtx, int));
107 static void store_reg PARAMS ((int, int, int));
108 static void store_reg_modify PARAMS ((int, int, int));
109 static void load_reg PARAMS ((int, int, int));
110 static void set_reg_plus_d PARAMS ((int, int, int, int));
111 static void pa_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
112 static void pa_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
113 static int pa_adjust_cost PARAMS ((rtx, rtx, rtx, int));
114 static int pa_adjust_priority PARAMS ((rtx, int));
115 static int pa_issue_rate PARAMS ((void));
116 static void pa_select_section PARAMS ((tree, int, unsigned HOST_WIDE_INT))
117 ATTRIBUTE_UNUSED;
118 static void pa_encode_section_info PARAMS ((tree, int));
119 static const char *pa_strip_name_encoding PARAMS ((const char *));
120 static void pa_globalize_label PARAMS ((FILE *, const char *))
121 ATTRIBUTE_UNUSED;
122 static void pa_asm_output_mi_thunk PARAMS ((FILE *, tree, HOST_WIDE_INT,
123 HOST_WIDE_INT, tree));
124 #if !defined(USE_COLLECT2)
125 static void pa_asm_out_constructor PARAMS ((rtx, int));
126 static void pa_asm_out_destructor PARAMS ((rtx, int));
127 #endif
128 static void pa_init_builtins PARAMS ((void));
129 static void copy_fp_args PARAMS ((rtx)) ATTRIBUTE_UNUSED;
130 static int length_fp_args PARAMS ((rtx)) ATTRIBUTE_UNUSED;
131 static struct deferred_plabel *get_plabel PARAMS ((const char *))
132 ATTRIBUTE_UNUSED;
133
134 /* Save the operands last given to a compare for use when we
135 generate a scc or bcc insn. */
136 rtx hppa_compare_op0, hppa_compare_op1;
137 enum cmp_type hppa_branch_type;
138
139 /* Which cpu we are scheduling for. */
140 enum processor_type pa_cpu;
141
142 /* String to hold which cpu we are scheduling for. */
143 const char *pa_cpu_string;
144
145 /* Which architecture we are generating code for. */
146 enum architecture_type pa_arch;
147
148 /* String to hold which architecture we are generating code for. */
149 const char *pa_arch_string;
150
151 /* Counts for the number of callee-saved general and floating point
152 registers which were saved by the current function's prologue. */
153 static int gr_saved, fr_saved;
154
155 static rtx find_addr_reg PARAMS ((rtx));
156
157 /* Keep track of the number of bytes we have output in the CODE subspaces
158 during this compilation so we'll know when to emit inline long-calls. */
159 unsigned long total_code_bytes;
160
161 /* Variables to handle plabels that we discover are necessary at assembly
162 output time. They are output after the current function. */
163 struct deferred_plabel GTY(())
164 {
165 rtx internal_label;
166 const char *name;
167 };
168 static GTY((length ("n_deferred_plabels"))) struct deferred_plabel *
169 deferred_plabels;
170 static size_t n_deferred_plabels = 0;
171
172 /* Initialize the GCC target structure. */
173
174 #undef TARGET_ASM_ALIGNED_HI_OP
175 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
176 #undef TARGET_ASM_ALIGNED_SI_OP
177 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
178 #undef TARGET_ASM_ALIGNED_DI_OP
179 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
180 #undef TARGET_ASM_UNALIGNED_HI_OP
181 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
182 #undef TARGET_ASM_UNALIGNED_SI_OP
183 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
184 #undef TARGET_ASM_UNALIGNED_DI_OP
185 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
186 #undef TARGET_ASM_INTEGER
187 #define TARGET_ASM_INTEGER pa_assemble_integer
188
189 #undef TARGET_ASM_FUNCTION_PROLOGUE
190 #define TARGET_ASM_FUNCTION_PROLOGUE pa_output_function_prologue
191 #undef TARGET_ASM_FUNCTION_EPILOGUE
192 #define TARGET_ASM_FUNCTION_EPILOGUE pa_output_function_epilogue
193
194 #undef TARGET_SCHED_ADJUST_COST
195 #define TARGET_SCHED_ADJUST_COST pa_adjust_cost
196 #undef TARGET_SCHED_ADJUST_PRIORITY
197 #define TARGET_SCHED_ADJUST_PRIORITY pa_adjust_priority
198 #undef TARGET_SCHED_ISSUE_RATE
199 #define TARGET_SCHED_ISSUE_RATE pa_issue_rate
200
201 #undef TARGET_ENCODE_SECTION_INFO
202 #define TARGET_ENCODE_SECTION_INFO pa_encode_section_info
203 #undef TARGET_STRIP_NAME_ENCODING
204 #define TARGET_STRIP_NAME_ENCODING pa_strip_name_encoding
205
206 #undef TARGET_ASM_OUTPUT_MI_THUNK
207 #define TARGET_ASM_OUTPUT_MI_THUNK pa_asm_output_mi_thunk
208 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
209 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
210
211 #if !defined(USE_COLLECT2)
212 #undef TARGET_ASM_CONSTRUCTOR
213 #define TARGET_ASM_CONSTRUCTOR pa_asm_out_constructor
214 #undef TARGET_ASM_DESTRUCTOR
215 #define TARGET_ASM_DESTRUCTOR pa_asm_out_destructor
216 #endif
217
218 #undef TARGET_INIT_BUILTINS
219 #define TARGET_INIT_BUILTINS pa_init_builtins
220
221 struct gcc_target targetm = TARGET_INITIALIZER;
222
223 void
override_options()224 override_options ()
225 {
226 if (pa_cpu_string == NULL)
227 pa_cpu_string = TARGET_SCHED_DEFAULT;
228
229 if (! strcmp (pa_cpu_string, "8000"))
230 {
231 pa_cpu_string = "8000";
232 pa_cpu = PROCESSOR_8000;
233 }
234 else if (! strcmp (pa_cpu_string, "7100"))
235 {
236 pa_cpu_string = "7100";
237 pa_cpu = PROCESSOR_7100;
238 }
239 else if (! strcmp (pa_cpu_string, "700"))
240 {
241 pa_cpu_string = "700";
242 pa_cpu = PROCESSOR_700;
243 }
244 else if (! strcmp (pa_cpu_string, "7100LC"))
245 {
246 pa_cpu_string = "7100LC";
247 pa_cpu = PROCESSOR_7100LC;
248 }
249 else if (! strcmp (pa_cpu_string, "7200"))
250 {
251 pa_cpu_string = "7200";
252 pa_cpu = PROCESSOR_7200;
253 }
254 else if (! strcmp (pa_cpu_string, "7300"))
255 {
256 pa_cpu_string = "7300";
257 pa_cpu = PROCESSOR_7300;
258 }
259 else
260 {
261 warning ("unknown -mschedule= option (%s).\nValid options are 700, 7100, 7100LC, 7200, 7300, and 8000\n", pa_cpu_string);
262 }
263
264 /* Set the instruction set architecture. */
265 if (pa_arch_string && ! strcmp (pa_arch_string, "1.0"))
266 {
267 pa_arch_string = "1.0";
268 pa_arch = ARCHITECTURE_10;
269 target_flags &= ~(MASK_PA_11 | MASK_PA_20);
270 }
271 else if (pa_arch_string && ! strcmp (pa_arch_string, "1.1"))
272 {
273 pa_arch_string = "1.1";
274 pa_arch = ARCHITECTURE_11;
275 target_flags &= ~MASK_PA_20;
276 target_flags |= MASK_PA_11;
277 }
278 else if (pa_arch_string && ! strcmp (pa_arch_string, "2.0"))
279 {
280 pa_arch_string = "2.0";
281 pa_arch = ARCHITECTURE_20;
282 target_flags |= MASK_PA_11 | MASK_PA_20;
283 }
284 else if (pa_arch_string)
285 {
286 warning ("unknown -march= option (%s).\nValid options are 1.0, 1.1, and 2.0\n", pa_arch_string);
287 }
288
289 /* Unconditional branches in the delay slot are not compatible with dwarf2
290 call frame information. There is no benefit in using this optimization
291 on PA8000 and later processors. */
292 if (pa_cpu >= PROCESSOR_8000
293 || (! USING_SJLJ_EXCEPTIONS && flag_exceptions)
294 || flag_unwind_tables)
295 target_flags &= ~MASK_JUMP_IN_DELAY;
296
297 if (flag_pic && TARGET_PORTABLE_RUNTIME)
298 {
299 warning ("PIC code generation is not supported in the portable runtime model\n");
300 }
301
302 if (flag_pic && TARGET_FAST_INDIRECT_CALLS)
303 {
304 warning ("PIC code generation is not compatible with fast indirect calls\n");
305 }
306
307 if (! TARGET_GAS && write_symbols != NO_DEBUG)
308 {
309 warning ("-g is only supported when using GAS on this processor,");
310 warning ("-g option disabled");
311 write_symbols = NO_DEBUG;
312 }
313
314 /* We only support the "big PIC" model now. And we always generate PIC
315 code when in 64bit mode. */
316 if (flag_pic == 1 || TARGET_64BIT)
317 flag_pic = 2;
318
319 /* We can't guarantee that .dword is available for 32-bit targets. */
320 if (UNITS_PER_WORD == 4)
321 targetm.asm_out.aligned_op.di = NULL;
322
323 /* The unaligned ops are only available when using GAS. */
324 if (!TARGET_GAS)
325 {
326 targetm.asm_out.unaligned_op.hi = NULL;
327 targetm.asm_out.unaligned_op.si = NULL;
328 targetm.asm_out.unaligned_op.di = NULL;
329 }
330 }
331
332 static void
pa_init_builtins()333 pa_init_builtins ()
334 {
335 #ifdef DONT_HAVE_FPUTC_UNLOCKED
336 built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED] = NULL_TREE;
337 #endif
338 }
339
340 /* Return nonzero only if OP is a register of mode MODE,
341 or CONST0_RTX. */
342 int
reg_or_0_operand(op,mode)343 reg_or_0_operand (op, mode)
344 rtx op;
345 enum machine_mode mode;
346 {
347 return (op == CONST0_RTX (mode) || register_operand (op, mode));
348 }
349
350 /* Return nonzero if OP is suitable for use in a call to a named
351 function.
352
353 For 2.5 try to eliminate either call_operand_address or
354 function_label_operand, they perform very similar functions. */
355 int
call_operand_address(op,mode)356 call_operand_address (op, mode)
357 rtx op;
358 enum machine_mode mode ATTRIBUTE_UNUSED;
359 {
360 return (GET_MODE (op) == word_mode
361 && CONSTANT_P (op) && ! TARGET_PORTABLE_RUNTIME);
362 }
363
364 /* Return 1 if X contains a symbolic expression. We know these
365 expressions will have one of a few well defined forms, so
366 we need only check those forms. */
367 int
symbolic_expression_p(x)368 symbolic_expression_p (x)
369 register rtx x;
370 {
371
372 /* Strip off any HIGH. */
373 if (GET_CODE (x) == HIGH)
374 x = XEXP (x, 0);
375
376 return (symbolic_operand (x, VOIDmode));
377 }
378
379 int
symbolic_operand(op,mode)380 symbolic_operand (op, mode)
381 register rtx op;
382 enum machine_mode mode ATTRIBUTE_UNUSED;
383 {
384 switch (GET_CODE (op))
385 {
386 case SYMBOL_REF:
387 case LABEL_REF:
388 return 1;
389 case CONST:
390 op = XEXP (op, 0);
391 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
392 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
393 && GET_CODE (XEXP (op, 1)) == CONST_INT);
394 default:
395 return 0;
396 }
397 }
398
399 /* Return truth value of statement that OP is a symbolic memory
400 operand of mode MODE. */
401
402 int
symbolic_memory_operand(op,mode)403 symbolic_memory_operand (op, mode)
404 rtx op;
405 enum machine_mode mode ATTRIBUTE_UNUSED;
406 {
407 if (GET_CODE (op) == SUBREG)
408 op = SUBREG_REG (op);
409 if (GET_CODE (op) != MEM)
410 return 0;
411 op = XEXP (op, 0);
412 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
413 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
414 }
415
416 /* Return 1 if the operand is either a register or a memory operand that is
417 not symbolic. */
418
419 int
reg_or_nonsymb_mem_operand(op,mode)420 reg_or_nonsymb_mem_operand (op, mode)
421 register rtx op;
422 enum machine_mode mode;
423 {
424 if (register_operand (op, mode))
425 return 1;
426
427 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
428 return 1;
429
430 return 0;
431 }
432
433 /* Return 1 if the operand is either a register, zero, or a memory operand
434 that is not symbolic. */
435
436 int
reg_or_0_or_nonsymb_mem_operand(op,mode)437 reg_or_0_or_nonsymb_mem_operand (op, mode)
438 register rtx op;
439 enum machine_mode mode;
440 {
441 if (register_operand (op, mode))
442 return 1;
443
444 if (op == CONST0_RTX (mode))
445 return 1;
446
447 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
448 return 1;
449
450 return 0;
451 }
452
453 /* Return 1 if the operand is a register operand or a non-symbolic memory
454 operand after reload. This predicate is used for branch patterns that
455 internally handle register reloading. We need to accept non-symbolic
456 memory operands after reload to ensure that the pattern is still valid
457 if reload didn't find a hard register for the operand. */
458
459 int
reg_before_reload_operand(op,mode)460 reg_before_reload_operand (op, mode)
461 register rtx op;
462 enum machine_mode mode;
463 {
464 /* Don't accept a SUBREG since it will need a reload. */
465 if (GET_CODE (op) == SUBREG)
466 return 0;
467
468 if (register_operand (op, mode))
469 return 1;
470
471 if (reload_completed
472 && memory_operand (op, mode)
473 && ! symbolic_memory_operand (op, mode))
474 return 1;
475
476 return 0;
477 }
478
479 /* Accept any constant that can be moved in one instruction into a
480 general register. */
481 int
cint_ok_for_move(intval)482 cint_ok_for_move (intval)
483 HOST_WIDE_INT intval;
484 {
485 /* OK if ldo, ldil, or zdepi, can be used. */
486 return (CONST_OK_FOR_LETTER_P (intval, 'J')
487 || CONST_OK_FOR_LETTER_P (intval, 'N')
488 || CONST_OK_FOR_LETTER_P (intval, 'K'));
489 }
490
491 /* Accept anything that can be moved in one instruction into a general
492 register. */
493 int
move_operand(op,mode)494 move_operand (op, mode)
495 rtx op;
496 enum machine_mode mode;
497 {
498 if (register_operand (op, mode))
499 return 1;
500
501 if (GET_CODE (op) == CONSTANT_P_RTX)
502 return 1;
503
504 if (GET_CODE (op) == CONST_INT)
505 return cint_ok_for_move (INTVAL (op));
506
507 if (GET_CODE (op) == SUBREG)
508 op = SUBREG_REG (op);
509 if (GET_CODE (op) != MEM)
510 return 0;
511
512 op = XEXP (op, 0);
513
514 /* We consider a LO_SUM DLT reference a move_operand now since it has
515 been merged into the normal movsi/movdi patterns. */
516 if (GET_CODE (op) == LO_SUM
517 && GET_CODE (XEXP (op, 0)) == REG
518 && REG_OK_FOR_BASE_P (XEXP (op, 0))
519 && GET_CODE (XEXP (op, 1)) == UNSPEC
520 && GET_MODE (op) == Pmode)
521 return 1;
522
523 /* Since move_operand is only used for source operands, we can always
524 allow scaled indexing! */
525 if (! TARGET_DISABLE_INDEXING
526 && GET_CODE (op) == PLUS
527 && ((GET_CODE (XEXP (op, 0)) == MULT
528 && GET_CODE (XEXP (XEXP (op, 0), 0)) == REG
529 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
530 && INTVAL (XEXP (XEXP (op, 0), 1))
531 == (HOST_WIDE_INT) GET_MODE_SIZE (mode)
532 && GET_CODE (XEXP (op, 1)) == REG)
533 || (GET_CODE (XEXP (op, 1)) == MULT
534 &&GET_CODE (XEXP (XEXP (op, 1), 0)) == REG
535 && GET_CODE (XEXP (XEXP (op, 1), 1)) == CONST_INT
536 && INTVAL (XEXP (XEXP (op, 1), 1))
537 == (HOST_WIDE_INT) GET_MODE_SIZE (mode)
538 && GET_CODE (XEXP (op, 0)) == REG)))
539 return 1;
540
541 return memory_address_p (mode, op);
542 }
543
544 /* Accept REG and any CONST_INT that can be moved in one instruction into a
545 general register. */
546 int
reg_or_cint_move_operand(op,mode)547 reg_or_cint_move_operand (op, mode)
548 rtx op;
549 enum machine_mode mode;
550 {
551 if (register_operand (op, mode))
552 return 1;
553
554 if (GET_CODE (op) == CONST_INT)
555 return cint_ok_for_move (INTVAL (op));
556
557 return 0;
558 }
559
560 int
pic_label_operand(op,mode)561 pic_label_operand (op, mode)
562 rtx op;
563 enum machine_mode mode ATTRIBUTE_UNUSED;
564 {
565 if (!flag_pic)
566 return 0;
567
568 switch (GET_CODE (op))
569 {
570 case LABEL_REF:
571 return 1;
572 case CONST:
573 op = XEXP (op, 0);
574 return (GET_CODE (XEXP (op, 0)) == LABEL_REF
575 && GET_CODE (XEXP (op, 1)) == CONST_INT);
576 default:
577 return 0;
578 }
579 }
580
581 int
fp_reg_operand(op,mode)582 fp_reg_operand (op, mode)
583 rtx op;
584 enum machine_mode mode ATTRIBUTE_UNUSED;
585 {
586 return reg_renumber && FP_REG_P (op);
587 }
588
589
590
591 /* Return truth value of whether OP can be used as an operand in a
592 three operand arithmetic insn that accepts registers of mode MODE
593 or 14-bit signed integers. */
594 int
arith_operand(op,mode)595 arith_operand (op, mode)
596 rtx op;
597 enum machine_mode mode;
598 {
599 return (register_operand (op, mode)
600 || (GET_CODE (op) == CONST_INT && INT_14_BITS (op)));
601 }
602
603 /* Return truth value of whether OP can be used as an operand in a
604 three operand arithmetic insn that accepts registers of mode MODE
605 or 11-bit signed integers. */
606 int
arith11_operand(op,mode)607 arith11_operand (op, mode)
608 rtx op;
609 enum machine_mode mode;
610 {
611 return (register_operand (op, mode)
612 || (GET_CODE (op) == CONST_INT && INT_11_BITS (op)));
613 }
614
615 /* Return truth value of whether OP can be used as an operand in a
616 adddi3 insn. */
617 int
adddi3_operand(op,mode)618 adddi3_operand (op, mode)
619 rtx op;
620 enum machine_mode mode;
621 {
622 return (register_operand (op, mode)
623 || (GET_CODE (op) == CONST_INT
624 && (TARGET_64BIT ? INT_14_BITS (op) : INT_11_BITS (op))));
625 }
626
627 /* A constant integer suitable for use in a PRE_MODIFY memory
628 reference. */
629 int
pre_cint_operand(op,mode)630 pre_cint_operand (op, mode)
631 rtx op;
632 enum machine_mode mode ATTRIBUTE_UNUSED;
633 {
634 return (GET_CODE (op) == CONST_INT
635 && INTVAL (op) >= -0x2000 && INTVAL (op) < 0x10);
636 }
637
638 /* A constant integer suitable for use in a POST_MODIFY memory
639 reference. */
640 int
post_cint_operand(op,mode)641 post_cint_operand (op, mode)
642 rtx op;
643 enum machine_mode mode ATTRIBUTE_UNUSED;
644 {
645 return (GET_CODE (op) == CONST_INT
646 && INTVAL (op) < 0x2000 && INTVAL (op) >= -0x10);
647 }
648
649 int
arith_double_operand(op,mode)650 arith_double_operand (op, mode)
651 rtx op;
652 enum machine_mode mode;
653 {
654 return (register_operand (op, mode)
655 || (GET_CODE (op) == CONST_DOUBLE
656 && GET_MODE (op) == mode
657 && VAL_14_BITS_P (CONST_DOUBLE_LOW (op))
658 && ((CONST_DOUBLE_HIGH (op) >= 0)
659 == ((CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
660 }
661
662 /* Return truth value of whether OP is an integer which fits the
663 range constraining immediate operands in three-address insns, or
664 is an integer register. */
665
666 int
ireg_or_int5_operand(op,mode)667 ireg_or_int5_operand (op, mode)
668 rtx op;
669 enum machine_mode mode ATTRIBUTE_UNUSED;
670 {
671 return ((GET_CODE (op) == CONST_INT && INT_5_BITS (op))
672 || (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32));
673 }
674
675 /* Return nonzero if OP is an integer register, else return zero. */
676 int
ireg_operand(op,mode)677 ireg_operand (op, mode)
678 rtx op;
679 enum machine_mode mode ATTRIBUTE_UNUSED;
680 {
681 return (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32);
682 }
683
684 /* Return truth value of whether OP is an integer which fits the
685 range constraining immediate operands in three-address insns. */
686
687 int
int5_operand(op,mode)688 int5_operand (op, mode)
689 rtx op;
690 enum machine_mode mode ATTRIBUTE_UNUSED;
691 {
692 return (GET_CODE (op) == CONST_INT && INT_5_BITS (op));
693 }
694
695 int
uint5_operand(op,mode)696 uint5_operand (op, mode)
697 rtx op;
698 enum machine_mode mode ATTRIBUTE_UNUSED;
699 {
700 return (GET_CODE (op) == CONST_INT && INT_U5_BITS (op));
701 }
702
703 int
int11_operand(op,mode)704 int11_operand (op, mode)
705 rtx op;
706 enum machine_mode mode ATTRIBUTE_UNUSED;
707 {
708 return (GET_CODE (op) == CONST_INT && INT_11_BITS (op));
709 }
710
711 int
uint32_operand(op,mode)712 uint32_operand (op, mode)
713 rtx op;
714 enum machine_mode mode ATTRIBUTE_UNUSED;
715 {
716 #if HOST_BITS_PER_WIDE_INT > 32
717 /* All allowed constants will fit a CONST_INT. */
718 return (GET_CODE (op) == CONST_INT
719 && (INTVAL (op) >= 0 && INTVAL (op) < (HOST_WIDE_INT) 1 << 32));
720 #else
721 return (GET_CODE (op) == CONST_INT
722 || (GET_CODE (op) == CONST_DOUBLE
723 && CONST_DOUBLE_HIGH (op) == 0));
724 #endif
725 }
726
727 int
arith5_operand(op,mode)728 arith5_operand (op, mode)
729 rtx op;
730 enum machine_mode mode;
731 {
732 return register_operand (op, mode) || int5_operand (op, mode);
733 }
734
735 /* True iff zdepi can be used to generate this CONST_INT.
736 zdepi first sign extends a 5 bit signed number to a given field
737 length, then places this field anywhere in a zero. */
738 int
zdepi_cint_p(x)739 zdepi_cint_p (x)
740 unsigned HOST_WIDE_INT x;
741 {
742 unsigned HOST_WIDE_INT lsb_mask, t;
743
744 /* This might not be obvious, but it's at least fast.
745 This function is critical; we don't have the time loops would take. */
746 lsb_mask = x & -x;
747 t = ((x >> 4) + lsb_mask) & ~(lsb_mask - 1);
748 /* Return true iff t is a power of two. */
749 return ((t & (t - 1)) == 0);
750 }
751
752 /* True iff depi or extru can be used to compute (reg & mask).
753 Accept bit pattern like these:
754 0....01....1
755 1....10....0
756 1..10..01..1 */
757 int
and_mask_p(mask)758 and_mask_p (mask)
759 unsigned HOST_WIDE_INT mask;
760 {
761 mask = ~mask;
762 mask += mask & -mask;
763 return (mask & (mask - 1)) == 0;
764 }
765
766 /* True iff depi or extru can be used to compute (reg & OP). */
767 int
and_operand(op,mode)768 and_operand (op, mode)
769 rtx op;
770 enum machine_mode mode;
771 {
772 return (register_operand (op, mode)
773 || (GET_CODE (op) == CONST_INT && and_mask_p (INTVAL (op))));
774 }
775
776 /* True iff depi can be used to compute (reg | MASK). */
777 int
ior_mask_p(mask)778 ior_mask_p (mask)
779 unsigned HOST_WIDE_INT mask;
780 {
781 mask += mask & -mask;
782 return (mask & (mask - 1)) == 0;
783 }
784
785 /* True iff depi can be used to compute (reg | OP). */
786 int
ior_operand(op,mode)787 ior_operand (op, mode)
788 rtx op;
789 enum machine_mode mode ATTRIBUTE_UNUSED;
790 {
791 return (GET_CODE (op) == CONST_INT && ior_mask_p (INTVAL (op)));
792 }
793
794 int
lhs_lshift_operand(op,mode)795 lhs_lshift_operand (op, mode)
796 rtx op;
797 enum machine_mode mode;
798 {
799 return register_operand (op, mode) || lhs_lshift_cint_operand (op, mode);
800 }
801
802 /* True iff OP is a CONST_INT of the forms 0...0xxxx or 0...01...1xxxx.
803 Such values can be the left hand side x in (x << r), using the zvdepi
804 instruction. */
805 int
lhs_lshift_cint_operand(op,mode)806 lhs_lshift_cint_operand (op, mode)
807 rtx op;
808 enum machine_mode mode ATTRIBUTE_UNUSED;
809 {
810 unsigned HOST_WIDE_INT x;
811 if (GET_CODE (op) != CONST_INT)
812 return 0;
813 x = INTVAL (op) >> 4;
814 return (x & (x + 1)) == 0;
815 }
816
817 int
arith32_operand(op,mode)818 arith32_operand (op, mode)
819 rtx op;
820 enum machine_mode mode;
821 {
822 return register_operand (op, mode) || GET_CODE (op) == CONST_INT;
823 }
824
825 int
pc_or_label_operand(op,mode)826 pc_or_label_operand (op, mode)
827 rtx op;
828 enum machine_mode mode ATTRIBUTE_UNUSED;
829 {
830 return (GET_CODE (op) == PC || GET_CODE (op) == LABEL_REF);
831 }
832
833 /* Legitimize PIC addresses. If the address is already
834 position-independent, we return ORIG. Newly generated
835 position-independent addresses go to REG. If we need more
836 than one register, we lose. */
837
838 rtx
legitimize_pic_address(orig,mode,reg)839 legitimize_pic_address (orig, mode, reg)
840 rtx orig, reg;
841 enum machine_mode mode;
842 {
843 rtx pic_ref = orig;
844
845 /* Labels need special handling. */
846 if (pic_label_operand (orig, mode))
847 {
848 /* We do not want to go through the movXX expanders here since that
849 would create recursion.
850
851 Nor do we really want to call a generator for a named pattern
852 since that requires multiple patterns if we want to support
853 multiple word sizes.
854
855 So instead we just emit the raw set, which avoids the movXX
856 expanders completely. */
857 emit_insn (gen_rtx_SET (VOIDmode, reg, orig));
858 current_function_uses_pic_offset_table = 1;
859 return reg;
860 }
861 if (GET_CODE (orig) == SYMBOL_REF)
862 {
863 if (reg == 0)
864 abort ();
865
866 emit_move_insn (reg,
867 gen_rtx_PLUS (word_mode, pic_offset_table_rtx,
868 gen_rtx_HIGH (word_mode, orig)));
869 pic_ref
870 = gen_rtx_MEM (Pmode,
871 gen_rtx_LO_SUM (Pmode, reg,
872 gen_rtx_UNSPEC (Pmode,
873 gen_rtvec (1, orig),
874 0)));
875
876 current_function_uses_pic_offset_table = 1;
877 RTX_UNCHANGING_P (pic_ref) = 1;
878 emit_move_insn (reg, pic_ref);
879 return reg;
880 }
881 else if (GET_CODE (orig) == CONST)
882 {
883 rtx base;
884
885 if (GET_CODE (XEXP (orig, 0)) == PLUS
886 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
887 return orig;
888
889 if (reg == 0)
890 abort ();
891
892 if (GET_CODE (XEXP (orig, 0)) == PLUS)
893 {
894 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
895 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
896 base == reg ? 0 : reg);
897 }
898 else abort ();
899 if (GET_CODE (orig) == CONST_INT)
900 {
901 if (INT_14_BITS (orig))
902 return plus_constant (base, INTVAL (orig));
903 orig = force_reg (Pmode, orig);
904 }
905 pic_ref = gen_rtx_PLUS (Pmode, base, orig);
906 /* Likewise, should we set special REG_NOTEs here? */
907 }
908 return pic_ref;
909 }
910
911 /* Try machine-dependent ways of modifying an illegitimate address
912 to be legitimate. If we find one, return the new, valid address.
913 This macro is used in only one place: `memory_address' in explow.c.
914
915 OLDX is the address as it was before break_out_memory_refs was called.
916 In some cases it is useful to look at this to decide what needs to be done.
917
918 MODE and WIN are passed so that this macro can use
919 GO_IF_LEGITIMATE_ADDRESS.
920
921 It is always safe for this macro to do nothing. It exists to recognize
922 opportunities to optimize the output.
923
924 For the PA, transform:
925
926 memory(X + <large int>)
927
928 into:
929
930 if (<large int> & mask) >= 16
931 Y = (<large int> & ~mask) + mask + 1 Round up.
932 else
933 Y = (<large int> & ~mask) Round down.
934 Z = X + Y
935 memory (Z + (<large int> - Y));
936
937 This is for CSE to find several similar references, and only use one Z.
938
939 X can either be a SYMBOL_REF or REG, but because combine can not
940 perform a 4->2 combination we do nothing for SYMBOL_REF + D where
941 D will not fit in 14 bits.
942
943 MODE_FLOAT references allow displacements which fit in 5 bits, so use
944 0x1f as the mask.
945
946 MODE_INT references allow displacements which fit in 14 bits, so use
947 0x3fff as the mask.
948
949 This relies on the fact that most mode MODE_FLOAT references will use FP
950 registers and most mode MODE_INT references will use integer registers.
951 (In the rare case of an FP register used in an integer MODE, we depend
952 on secondary reloads to clean things up.)
953
954
955 It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special
956 manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed
957 addressing modes to be used).
958
959 Put X and Z into registers. Then put the entire expression into
960 a register. */
961
962 rtx
hppa_legitimize_address(x,oldx,mode)963 hppa_legitimize_address (x, oldx, mode)
964 rtx x, oldx ATTRIBUTE_UNUSED;
965 enum machine_mode mode;
966 {
967 rtx orig = x;
968
969 if (flag_pic)
970 return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode));
971
972 /* Strip off CONST. */
973 if (GET_CODE (x) == CONST)
974 x = XEXP (x, 0);
975
976 /* Special case. Get the SYMBOL_REF into a register and use indexing.
977 That should always be safe. */
978 if (GET_CODE (x) == PLUS
979 && GET_CODE (XEXP (x, 0)) == REG
980 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
981 {
982 rtx reg = force_reg (Pmode, XEXP (x, 1));
983 return force_reg (Pmode, gen_rtx_PLUS (Pmode, reg, XEXP (x, 0)));
984 }
985
986 /* Note we must reject symbols which represent function addresses
987 since the assembler/linker can't handle arithmetic on plabels. */
988 if (GET_CODE (x) == PLUS
989 && GET_CODE (XEXP (x, 1)) == CONST_INT
990 && ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF
991 && !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0)))
992 || GET_CODE (XEXP (x, 0)) == REG))
993 {
994 rtx int_part, ptr_reg;
995 int newoffset;
996 int offset = INTVAL (XEXP (x, 1));
997 int mask;
998
999 mask = (GET_MODE_CLASS (mode) == MODE_FLOAT
1000 ? (TARGET_PA_20 ? 0x3fff : 0x1f) : 0x3fff);
1001
1002 /* Choose which way to round the offset. Round up if we
1003 are >= halfway to the next boundary. */
1004 if ((offset & mask) >= ((mask + 1) / 2))
1005 newoffset = (offset & ~ mask) + mask + 1;
1006 else
1007 newoffset = (offset & ~ mask);
1008
1009 /* If the newoffset will not fit in 14 bits (ldo), then
1010 handling this would take 4 or 5 instructions (2 to load
1011 the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to
1012 add the new offset and the SYMBOL_REF.) Combine can
1013 not handle 4->2 or 5->2 combinations, so do not create
1014 them. */
1015 if (! VAL_14_BITS_P (newoffset)
1016 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
1017 {
1018 rtx const_part = plus_constant (XEXP (x, 0), newoffset);
1019 rtx tmp_reg
1020 = force_reg (Pmode,
1021 gen_rtx_HIGH (Pmode, const_part));
1022 ptr_reg
1023 = force_reg (Pmode,
1024 gen_rtx_LO_SUM (Pmode,
1025 tmp_reg, const_part));
1026 }
1027 else
1028 {
1029 if (! VAL_14_BITS_P (newoffset))
1030 int_part = force_reg (Pmode, GEN_INT (newoffset));
1031 else
1032 int_part = GEN_INT (newoffset);
1033
1034 ptr_reg = force_reg (Pmode,
1035 gen_rtx_PLUS (Pmode,
1036 force_reg (Pmode, XEXP (x, 0)),
1037 int_part));
1038 }
1039 return plus_constant (ptr_reg, offset - newoffset);
1040 }
1041
1042 /* Handle (plus (mult (a) (shadd_constant)) (b)). */
1043
1044 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT
1045 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1046 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))
1047 && (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == 'o'
1048 || GET_CODE (XEXP (x, 1)) == SUBREG)
1049 && GET_CODE (XEXP (x, 1)) != CONST)
1050 {
1051 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1052 rtx reg1, reg2;
1053
1054 reg1 = XEXP (x, 1);
1055 if (GET_CODE (reg1) != REG)
1056 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1057
1058 reg2 = XEXP (XEXP (x, 0), 0);
1059 if (GET_CODE (reg2) != REG)
1060 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1061
1062 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1063 gen_rtx_MULT (Pmode,
1064 reg2,
1065 GEN_INT (val)),
1066 reg1));
1067 }
1068
1069 /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)).
1070
1071 Only do so for floating point modes since this is more speculative
1072 and we lose if it's an integer store. */
1073 if (GET_CODE (x) == PLUS
1074 && GET_CODE (XEXP (x, 0)) == PLUS
1075 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
1076 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
1077 && shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)))
1078 && (mode == SFmode || mode == DFmode))
1079 {
1080
1081 /* First, try and figure out what to use as a base register. */
1082 rtx reg1, reg2, base, idx, orig_base;
1083
1084 reg1 = XEXP (XEXP (x, 0), 1);
1085 reg2 = XEXP (x, 1);
1086 base = NULL_RTX;
1087 idx = NULL_RTX;
1088
1089 /* Make sure they're both regs. If one was a SYMBOL_REF [+ const],
1090 then emit_move_sequence will turn on REG_POINTER so we'll know
1091 it's a base register below. */
1092 if (GET_CODE (reg1) != REG)
1093 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1094
1095 if (GET_CODE (reg2) != REG)
1096 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1097
1098 /* Figure out what the base and index are. */
1099
1100 if (GET_CODE (reg1) == REG
1101 && REG_POINTER (reg1))
1102 {
1103 base = reg1;
1104 orig_base = XEXP (XEXP (x, 0), 1);
1105 idx = gen_rtx_PLUS (Pmode,
1106 gen_rtx_MULT (Pmode,
1107 XEXP (XEXP (XEXP (x, 0), 0), 0),
1108 XEXP (XEXP (XEXP (x, 0), 0), 1)),
1109 XEXP (x, 1));
1110 }
1111 else if (GET_CODE (reg2) == REG
1112 && REG_POINTER (reg2))
1113 {
1114 base = reg2;
1115 orig_base = XEXP (x, 1);
1116 idx = XEXP (x, 0);
1117 }
1118
1119 if (base == 0)
1120 return orig;
1121
1122 /* If the index adds a large constant, try to scale the
1123 constant so that it can be loaded with only one insn. */
1124 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1125 && VAL_14_BITS_P (INTVAL (XEXP (idx, 1))
1126 / INTVAL (XEXP (XEXP (idx, 0), 1)))
1127 && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0)
1128 {
1129 /* Divide the CONST_INT by the scale factor, then add it to A. */
1130 int val = INTVAL (XEXP (idx, 1));
1131
1132 val /= INTVAL (XEXP (XEXP (idx, 0), 1));
1133 reg1 = XEXP (XEXP (idx, 0), 0);
1134 if (GET_CODE (reg1) != REG)
1135 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1136
1137 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, reg1, GEN_INT (val)));
1138
1139 /* We can now generate a simple scaled indexed address. */
1140 return
1141 force_reg
1142 (Pmode, gen_rtx_PLUS (Pmode,
1143 gen_rtx_MULT (Pmode, reg1,
1144 XEXP (XEXP (idx, 0), 1)),
1145 base));
1146 }
1147
1148 /* If B + C is still a valid base register, then add them. */
1149 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1150 && INTVAL (XEXP (idx, 1)) <= 4096
1151 && INTVAL (XEXP (idx, 1)) >= -4096)
1152 {
1153 int val = INTVAL (XEXP (XEXP (idx, 0), 1));
1154 rtx reg1, reg2;
1155
1156 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, XEXP (idx, 1)));
1157
1158 reg2 = XEXP (XEXP (idx, 0), 0);
1159 if (GET_CODE (reg2) != CONST_INT)
1160 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1161
1162 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1163 gen_rtx_MULT (Pmode,
1164 reg2,
1165 GEN_INT (val)),
1166 reg1));
1167 }
1168
1169 /* Get the index into a register, then add the base + index and
1170 return a register holding the result. */
1171
1172 /* First get A into a register. */
1173 reg1 = XEXP (XEXP (idx, 0), 0);
1174 if (GET_CODE (reg1) != REG)
1175 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1176
1177 /* And get B into a register. */
1178 reg2 = XEXP (idx, 1);
1179 if (GET_CODE (reg2) != REG)
1180 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1181
1182 reg1 = force_reg (Pmode,
1183 gen_rtx_PLUS (Pmode,
1184 gen_rtx_MULT (Pmode, reg1,
1185 XEXP (XEXP (idx, 0), 1)),
1186 reg2));
1187
1188 /* Add the result to our base register and return. */
1189 return force_reg (Pmode, gen_rtx_PLUS (Pmode, base, reg1));
1190
1191 }
1192
1193 /* Uh-oh. We might have an address for x[n-100000]. This needs
1194 special handling to avoid creating an indexed memory address
1195 with x-100000 as the base.
1196
1197 If the constant part is small enough, then it's still safe because
1198 there is a guard page at the beginning and end of the data segment.
1199
1200 Scaled references are common enough that we want to try and rearrange the
1201 terms so that we can use indexing for these addresses too. Only
1202 do the optimization for floatint point modes. */
1203
1204 if (GET_CODE (x) == PLUS
1205 && symbolic_expression_p (XEXP (x, 1)))
1206 {
1207 /* Ugly. We modify things here so that the address offset specified
1208 by the index expression is computed first, then added to x to form
1209 the entire address. */
1210
1211 rtx regx1, regx2, regy1, regy2, y;
1212
1213 /* Strip off any CONST. */
1214 y = XEXP (x, 1);
1215 if (GET_CODE (y) == CONST)
1216 y = XEXP (y, 0);
1217
1218 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1219 {
1220 /* See if this looks like
1221 (plus (mult (reg) (shadd_const))
1222 (const (plus (symbol_ref) (const_int))))
1223
1224 Where const_int is small. In that case the const
1225 expression is a valid pointer for indexing.
1226
1227 If const_int is big, but can be divided evenly by shadd_const
1228 and added to (reg). This allows more scaled indexed addresses. */
1229 if (GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1230 && GET_CODE (XEXP (x, 0)) == MULT
1231 && GET_CODE (XEXP (y, 1)) == CONST_INT
1232 && INTVAL (XEXP (y, 1)) >= -4096
1233 && INTVAL (XEXP (y, 1)) <= 4095
1234 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1235 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1236 {
1237 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1238 rtx reg1, reg2;
1239
1240 reg1 = XEXP (x, 1);
1241 if (GET_CODE (reg1) != REG)
1242 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1243
1244 reg2 = XEXP (XEXP (x, 0), 0);
1245 if (GET_CODE (reg2) != REG)
1246 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1247
1248 return force_reg (Pmode,
1249 gen_rtx_PLUS (Pmode,
1250 gen_rtx_MULT (Pmode,
1251 reg2,
1252 GEN_INT (val)),
1253 reg1));
1254 }
1255 else if ((mode == DFmode || mode == SFmode)
1256 && GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1257 && GET_CODE (XEXP (x, 0)) == MULT
1258 && GET_CODE (XEXP (y, 1)) == CONST_INT
1259 && INTVAL (XEXP (y, 1)) % INTVAL (XEXP (XEXP (x, 0), 1)) == 0
1260 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1261 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1262 {
1263 regx1
1264 = force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1))
1265 / INTVAL (XEXP (XEXP (x, 0), 1))));
1266 regx2 = XEXP (XEXP (x, 0), 0);
1267 if (GET_CODE (regx2) != REG)
1268 regx2 = force_reg (Pmode, force_operand (regx2, 0));
1269 regx2 = force_reg (Pmode, gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1270 regx2, regx1));
1271 return
1272 force_reg (Pmode,
1273 gen_rtx_PLUS (Pmode,
1274 gen_rtx_MULT (Pmode, regx2,
1275 XEXP (XEXP (x, 0), 1)),
1276 force_reg (Pmode, XEXP (y, 0))));
1277 }
1278 else if (GET_CODE (XEXP (y, 1)) == CONST_INT
1279 && INTVAL (XEXP (y, 1)) >= -4096
1280 && INTVAL (XEXP (y, 1)) <= 4095)
1281 {
1282 /* This is safe because of the guard page at the
1283 beginning and end of the data space. Just
1284 return the original address. */
1285 return orig;
1286 }
1287 else
1288 {
1289 /* Doesn't look like one we can optimize. */
1290 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1291 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1292 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1293 regx1 = force_reg (Pmode,
1294 gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1295 regx1, regy2));
1296 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1297 }
1298 }
1299 }
1300
1301 return orig;
1302 }
1303
1304 /* For the HPPA, REG and REG+CONST is cost 0
1305 and addresses involving symbolic constants are cost 2.
1306
1307 PIC addresses are very expensive.
1308
1309 It is no coincidence that this has the same structure
1310 as GO_IF_LEGITIMATE_ADDRESS. */
1311 int
hppa_address_cost(X)1312 hppa_address_cost (X)
1313 rtx X;
1314 {
1315 if (GET_CODE (X) == PLUS)
1316 return 1;
1317 else if (GET_CODE (X) == LO_SUM)
1318 return 1;
1319 else if (GET_CODE (X) == HIGH)
1320 return 2;
1321 return 4;
1322 }
1323
1324 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
1325 new rtx with the correct mode. */
1326 static inline rtx
force_mode(mode,orig)1327 force_mode (mode, orig)
1328 enum machine_mode mode;
1329 rtx orig;
1330 {
1331 if (mode == GET_MODE (orig))
1332 return orig;
1333
1334 if (REGNO (orig) >= FIRST_PSEUDO_REGISTER)
1335 abort ();
1336
1337 return gen_rtx_REG (mode, REGNO (orig));
1338 }
1339
1340 /* Emit insns to move operands[1] into operands[0].
1341
1342 Return 1 if we have written out everything that needs to be done to
1343 do the move. Otherwise, return 0 and the caller will emit the move
1344 normally.
1345
1346 Note SCRATCH_REG may not be in the proper mode depending on how it
1347 will be used. This routine is resposible for creating a new copy
1348 of SCRATCH_REG in the proper mode. */
1349
1350 int
emit_move_sequence(operands,mode,scratch_reg)1351 emit_move_sequence (operands, mode, scratch_reg)
1352 rtx *operands;
1353 enum machine_mode mode;
1354 rtx scratch_reg;
1355 {
1356 register rtx operand0 = operands[0];
1357 register rtx operand1 = operands[1];
1358 register rtx tem;
1359
1360 if (scratch_reg
1361 && reload_in_progress && GET_CODE (operand0) == REG
1362 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1363 operand0 = reg_equiv_mem[REGNO (operand0)];
1364 else if (scratch_reg
1365 && reload_in_progress && GET_CODE (operand0) == SUBREG
1366 && GET_CODE (SUBREG_REG (operand0)) == REG
1367 && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
1368 {
1369 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1370 the code which tracks sets/uses for delete_output_reload. */
1371 rtx temp = gen_rtx_SUBREG (GET_MODE (operand0),
1372 reg_equiv_mem [REGNO (SUBREG_REG (operand0))],
1373 SUBREG_BYTE (operand0));
1374 operand0 = alter_subreg (&temp);
1375 }
1376
1377 if (scratch_reg
1378 && reload_in_progress && GET_CODE (operand1) == REG
1379 && REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
1380 operand1 = reg_equiv_mem[REGNO (operand1)];
1381 else if (scratch_reg
1382 && reload_in_progress && GET_CODE (operand1) == SUBREG
1383 && GET_CODE (SUBREG_REG (operand1)) == REG
1384 && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
1385 {
1386 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1387 the code which tracks sets/uses for delete_output_reload. */
1388 rtx temp = gen_rtx_SUBREG (GET_MODE (operand1),
1389 reg_equiv_mem [REGNO (SUBREG_REG (operand1))],
1390 SUBREG_BYTE (operand1));
1391 operand1 = alter_subreg (&temp);
1392 }
1393
1394 if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
1395 && ((tem = find_replacement (&XEXP (operand0, 0)))
1396 != XEXP (operand0, 0)))
1397 operand0 = gen_rtx_MEM (GET_MODE (operand0), tem);
1398 if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
1399 && ((tem = find_replacement (&XEXP (operand1, 0)))
1400 != XEXP (operand1, 0)))
1401 operand1 = gen_rtx_MEM (GET_MODE (operand1), tem);
1402
1403 /* Handle secondary reloads for loads/stores of FP registers from
1404 REG+D addresses where D does not fit in 5 or 14 bits, including
1405 (subreg (mem (addr))) cases. */
1406 if (fp_reg_operand (operand0, mode)
1407 && ((GET_CODE (operand1) == MEM
1408 && !memory_address_p ((GET_MODE_SIZE (mode) == 4 ? SFmode : DFmode),
1409 XEXP (operand1, 0)))
1410 || ((GET_CODE (operand1) == SUBREG
1411 && GET_CODE (XEXP (operand1, 0)) == MEM
1412 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1413 ? SFmode : DFmode),
1414 XEXP (XEXP (operand1, 0), 0)))))
1415 && scratch_reg)
1416 {
1417 if (GET_CODE (operand1) == SUBREG)
1418 operand1 = XEXP (operand1, 0);
1419
1420 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1421 it in WORD_MODE regardless of what mode it was originally given
1422 to us. */
1423 scratch_reg = force_mode (word_mode, scratch_reg);
1424
1425 /* D might not fit in 14 bits either; for such cases load D into
1426 scratch reg. */
1427 if (!memory_address_p (Pmode, XEXP (operand1, 0)))
1428 {
1429 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1430 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)),
1431 Pmode,
1432 XEXP (XEXP (operand1, 0), 0),
1433 scratch_reg));
1434 }
1435 else
1436 emit_move_insn (scratch_reg, XEXP (operand1, 0));
1437 emit_insn (gen_rtx_SET (VOIDmode, operand0,
1438 gen_rtx_MEM (mode, scratch_reg)));
1439 return 1;
1440 }
1441 else if (fp_reg_operand (operand1, mode)
1442 && ((GET_CODE (operand0) == MEM
1443 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1444 ? SFmode : DFmode),
1445 XEXP (operand0, 0)))
1446 || ((GET_CODE (operand0) == SUBREG)
1447 && GET_CODE (XEXP (operand0, 0)) == MEM
1448 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1449 ? SFmode : DFmode),
1450 XEXP (XEXP (operand0, 0), 0))))
1451 && scratch_reg)
1452 {
1453 if (GET_CODE (operand0) == SUBREG)
1454 operand0 = XEXP (operand0, 0);
1455
1456 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1457 it in WORD_MODE regardless of what mode it was originally given
1458 to us. */
1459 scratch_reg = force_mode (word_mode, scratch_reg);
1460
1461 /* D might not fit in 14 bits either; for such cases load D into
1462 scratch reg. */
1463 if (!memory_address_p (Pmode, XEXP (operand0, 0)))
1464 {
1465 emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
1466 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,
1467 0)),
1468 Pmode,
1469 XEXP (XEXP (operand0, 0),
1470 0),
1471 scratch_reg));
1472 }
1473 else
1474 emit_move_insn (scratch_reg, XEXP (operand0, 0));
1475 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_MEM (mode, scratch_reg),
1476 operand1));
1477 return 1;
1478 }
1479 /* Handle secondary reloads for loads of FP registers from constant
1480 expressions by forcing the constant into memory.
1481
1482 use scratch_reg to hold the address of the memory location.
1483
1484 The proper fix is to change PREFERRED_RELOAD_CLASS to return
1485 NO_REGS when presented with a const_int and an register class
1486 containing only FP registers. Doing so unfortunately creates
1487 more problems than it solves. Fix this for 2.5. */
1488 else if (fp_reg_operand (operand0, mode)
1489 && CONSTANT_P (operand1)
1490 && scratch_reg)
1491 {
1492 rtx xoperands[2];
1493
1494 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1495 it in WORD_MODE regardless of what mode it was originally given
1496 to us. */
1497 scratch_reg = force_mode (word_mode, scratch_reg);
1498
1499 /* Force the constant into memory and put the address of the
1500 memory location into scratch_reg. */
1501 xoperands[0] = scratch_reg;
1502 xoperands[1] = XEXP (force_const_mem (mode, operand1), 0);
1503 emit_move_sequence (xoperands, Pmode, 0);
1504
1505 /* Now load the destination register. */
1506 emit_insn (gen_rtx_SET (mode, operand0,
1507 gen_rtx_MEM (mode, scratch_reg)));
1508 return 1;
1509 }
1510 /* Handle secondary reloads for SAR. These occur when trying to load
1511 the SAR from memory, FP register, or with a constant. */
1512 else if (GET_CODE (operand0) == REG
1513 && REGNO (operand0) < FIRST_PSEUDO_REGISTER
1514 && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS
1515 && (GET_CODE (operand1) == MEM
1516 || GET_CODE (operand1) == CONST_INT
1517 || (GET_CODE (operand1) == REG
1518 && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1)))))
1519 && scratch_reg)
1520 {
1521 /* D might not fit in 14 bits either; for such cases load D into
1522 scratch reg. */
1523 if (GET_CODE (operand1) == MEM
1524 && !memory_address_p (Pmode, XEXP (operand1, 0)))
1525 {
1526 /* We are reloading the address into the scratch register, so we
1527 want to make sure the scratch register is a full register. */
1528 scratch_reg = force_mode (word_mode, scratch_reg);
1529
1530 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1531 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1,
1532 0)),
1533 Pmode,
1534 XEXP (XEXP (operand1, 0),
1535 0),
1536 scratch_reg));
1537
1538 /* Now we are going to load the scratch register from memory,
1539 we want to load it in the same width as the original MEM,
1540 which must be the same as the width of the ultimate destination,
1541 OPERAND0. */
1542 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1543
1544 emit_move_insn (scratch_reg, gen_rtx_MEM (GET_MODE (operand0),
1545 scratch_reg));
1546 }
1547 else
1548 {
1549 /* We want to load the scratch register using the same mode as
1550 the ultimate destination. */
1551 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1552
1553 emit_move_insn (scratch_reg, operand1);
1554 }
1555
1556 /* And emit the insn to set the ultimate destination. We know that
1557 the scratch register has the same mode as the destination at this
1558 point. */
1559 emit_move_insn (operand0, scratch_reg);
1560 return 1;
1561 }
1562 /* Handle most common case: storing into a register. */
1563 else if (register_operand (operand0, mode))
1564 {
1565 if (register_operand (operand1, mode)
1566 || (GET_CODE (operand1) == CONST_INT
1567 && cint_ok_for_move (INTVAL (operand1)))
1568 || (operand1 == CONST0_RTX (mode))
1569 || (GET_CODE (operand1) == HIGH
1570 && !symbolic_operand (XEXP (operand1, 0), VOIDmode))
1571 /* Only `general_operands' can come here, so MEM is ok. */
1572 || GET_CODE (operand1) == MEM)
1573 {
1574 /* Run this case quickly. */
1575 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1576 return 1;
1577 }
1578 }
1579 else if (GET_CODE (operand0) == MEM)
1580 {
1581 if (mode == DFmode && operand1 == CONST0_RTX (mode)
1582 && !(reload_in_progress || reload_completed))
1583 {
1584 rtx temp = gen_reg_rtx (DFmode);
1585
1586 emit_insn (gen_rtx_SET (VOIDmode, temp, operand1));
1587 emit_insn (gen_rtx_SET (VOIDmode, operand0, temp));
1588 return 1;
1589 }
1590 if (register_operand (operand1, mode) || operand1 == CONST0_RTX (mode))
1591 {
1592 /* Run this case quickly. */
1593 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1594 return 1;
1595 }
1596 if (! (reload_in_progress || reload_completed))
1597 {
1598 operands[0] = validize_mem (operand0);
1599 operands[1] = operand1 = force_reg (mode, operand1);
1600 }
1601 }
1602
1603 /* Simplify the source if we need to.
1604 Note we do have to handle function labels here, even though we do
1605 not consider them legitimate constants. Loop optimizations can
1606 call the emit_move_xxx with one as a source. */
1607 if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode))
1608 || function_label_operand (operand1, mode)
1609 || (GET_CODE (operand1) == HIGH
1610 && symbolic_operand (XEXP (operand1, 0), mode)))
1611 {
1612 int ishighonly = 0;
1613
1614 if (GET_CODE (operand1) == HIGH)
1615 {
1616 ishighonly = 1;
1617 operand1 = XEXP (operand1, 0);
1618 }
1619 if (symbolic_operand (operand1, mode))
1620 {
1621 /* Argh. The assembler and linker can't handle arithmetic
1622 involving plabels.
1623
1624 So we force the plabel into memory, load operand0 from
1625 the memory location, then add in the constant part. */
1626 if ((GET_CODE (operand1) == CONST
1627 && GET_CODE (XEXP (operand1, 0)) == PLUS
1628 && function_label_operand (XEXP (XEXP (operand1, 0), 0), Pmode))
1629 || function_label_operand (operand1, mode))
1630 {
1631 rtx temp, const_part;
1632
1633 /* Figure out what (if any) scratch register to use. */
1634 if (reload_in_progress || reload_completed)
1635 {
1636 scratch_reg = scratch_reg ? scratch_reg : operand0;
1637 /* SCRATCH_REG will hold an address and maybe the actual
1638 data. We want it in WORD_MODE regardless of what mode it
1639 was originally given to us. */
1640 scratch_reg = force_mode (word_mode, scratch_reg);
1641 }
1642 else if (flag_pic)
1643 scratch_reg = gen_reg_rtx (Pmode);
1644
1645 if (GET_CODE (operand1) == CONST)
1646 {
1647 /* Save away the constant part of the expression. */
1648 const_part = XEXP (XEXP (operand1, 0), 1);
1649 if (GET_CODE (const_part) != CONST_INT)
1650 abort ();
1651
1652 /* Force the function label into memory. */
1653 temp = force_const_mem (mode, XEXP (XEXP (operand1, 0), 0));
1654 }
1655 else
1656 {
1657 /* No constant part. */
1658 const_part = NULL_RTX;
1659
1660 /* Force the function label into memory. */
1661 temp = force_const_mem (mode, operand1);
1662 }
1663
1664
1665 /* Get the address of the memory location. PIC-ify it if
1666 necessary. */
1667 temp = XEXP (temp, 0);
1668 if (flag_pic)
1669 temp = legitimize_pic_address (temp, mode, scratch_reg);
1670
1671 /* Put the address of the memory location into our destination
1672 register. */
1673 operands[1] = temp;
1674 emit_move_sequence (operands, mode, scratch_reg);
1675
1676 /* Now load from the memory location into our destination
1677 register. */
1678 operands[1] = gen_rtx_MEM (Pmode, operands[0]);
1679 emit_move_sequence (operands, mode, scratch_reg);
1680
1681 /* And add back in the constant part. */
1682 if (const_part != NULL_RTX)
1683 expand_inc (operand0, const_part);
1684
1685 return 1;
1686 }
1687
1688 if (flag_pic)
1689 {
1690 rtx temp;
1691
1692 if (reload_in_progress || reload_completed)
1693 {
1694 temp = scratch_reg ? scratch_reg : operand0;
1695 /* TEMP will hold an address and maybe the actual
1696 data. We want it in WORD_MODE regardless of what mode it
1697 was originally given to us. */
1698 temp = force_mode (word_mode, temp);
1699 }
1700 else
1701 temp = gen_reg_rtx (Pmode);
1702
1703 /* (const (plus (symbol) (const_int))) must be forced to
1704 memory during/after reload if the const_int will not fit
1705 in 14 bits. */
1706 if (GET_CODE (operand1) == CONST
1707 && GET_CODE (XEXP (operand1, 0)) == PLUS
1708 && GET_CODE (XEXP (XEXP (operand1, 0), 1)) == CONST_INT
1709 && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1))
1710 && (reload_completed || reload_in_progress)
1711 && flag_pic)
1712 {
1713 operands[1] = force_const_mem (mode, operand1);
1714 operands[1] = legitimize_pic_address (XEXP (operands[1], 0),
1715 mode, temp);
1716 operands[1] = gen_rtx_MEM (mode, operands[1]);
1717 emit_move_sequence (operands, mode, temp);
1718 }
1719 else
1720 {
1721 operands[1] = legitimize_pic_address (operand1, mode, temp);
1722 emit_insn (gen_rtx_SET (VOIDmode, operand0, operands[1]));
1723 }
1724 }
1725 /* On the HPPA, references to data space are supposed to use dp,
1726 register 27, but showing it in the RTL inhibits various cse
1727 and loop optimizations. */
1728 else
1729 {
1730 rtx temp, set;
1731
1732 if (reload_in_progress || reload_completed)
1733 {
1734 temp = scratch_reg ? scratch_reg : operand0;
1735 /* TEMP will hold an address and maybe the actual
1736 data. We want it in WORD_MODE regardless of what mode it
1737 was originally given to us. */
1738 temp = force_mode (word_mode, temp);
1739 }
1740 else
1741 temp = gen_reg_rtx (mode);
1742
1743 /* Loading a SYMBOL_REF into a register makes that register
1744 safe to be used as the base in an indexed address.
1745
1746 Don't mark hard registers though. That loses. */
1747 if (GET_CODE (operand0) == REG
1748 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1749 REG_POINTER (operand0) = 1;
1750 if (REGNO (temp) >= FIRST_PSEUDO_REGISTER)
1751 REG_POINTER (temp) = 1;
1752 if (ishighonly)
1753 set = gen_rtx_SET (mode, operand0, temp);
1754 else
1755 set = gen_rtx_SET (VOIDmode,
1756 operand0,
1757 gen_rtx_LO_SUM (mode, temp, operand1));
1758
1759 emit_insn (gen_rtx_SET (VOIDmode,
1760 temp,
1761 gen_rtx_HIGH (mode, operand1)));
1762 emit_insn (set);
1763
1764 }
1765 return 1;
1766 }
1767 else if (GET_CODE (operand1) != CONST_INT
1768 || ! cint_ok_for_move (INTVAL (operand1)))
1769 {
1770 rtx extend = NULL_RTX;
1771 rtx temp;
1772
1773 if (TARGET_64BIT && GET_CODE (operand1) == CONST_INT
1774 && HOST_BITS_PER_WIDE_INT > 32
1775 && GET_MODE_BITSIZE (GET_MODE (operand0)) > 32)
1776 {
1777 HOST_WIDE_INT val = INTVAL (operand1);
1778 HOST_WIDE_INT nval;
1779
1780 /* Extract the low order 32 bits of the value and sign extend.
1781 If the new value is the same as the original value, we can
1782 can use the original value as-is. If the new value is
1783 different, we use it and insert the most-significant 32-bits
1784 of the original value into the final result. */
1785 nval = ((val & (((HOST_WIDE_INT) 2 << 31) - 1))
1786 ^ ((HOST_WIDE_INT) 1 << 31)) - ((HOST_WIDE_INT) 1 << 31);
1787 if (val != nval)
1788 {
1789 #if HOST_BITS_PER_WIDE_INT > 32
1790 extend = GEN_INT (val >> 32);
1791 #endif
1792 operand1 = GEN_INT (nval);
1793 }
1794 }
1795
1796 if (reload_in_progress || reload_completed)
1797 temp = operand0;
1798 else
1799 temp = gen_reg_rtx (mode);
1800
1801 /* We don't directly split DImode constants on 32-bit targets
1802 because PLUS uses an 11-bit immediate and the insn sequence
1803 generated is not as efficient as the one using HIGH/LO_SUM. */
1804 if (GET_CODE (operand1) == CONST_INT
1805 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
1806 {
1807 /* Directly break constant into high and low parts. This
1808 provides better optimization opportunities because various
1809 passes recognize constants split with PLUS but not LO_SUM.
1810 We use a 14-bit signed low part except when the addition
1811 of 0x4000 to the high part might change the sign of the
1812 high part. */
1813 HOST_WIDE_INT value = INTVAL (operand1);
1814 HOST_WIDE_INT low = value & 0x3fff;
1815 HOST_WIDE_INT high = value & ~ 0x3fff;
1816
1817 if (low >= 0x2000)
1818 {
1819 if (high == 0x7fffc000 || (mode == HImode && high == 0x4000))
1820 high += 0x2000;
1821 else
1822 high += 0x4000;
1823 }
1824
1825 low = value - high;
1826
1827 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (high)));
1828 operands[1] = gen_rtx_PLUS (mode, temp, GEN_INT (low));
1829 }
1830 else
1831 {
1832 emit_insn (gen_rtx_SET (VOIDmode, temp,
1833 gen_rtx_HIGH (mode, operand1)));
1834 operands[1] = gen_rtx_LO_SUM (mode, temp, operand1);
1835 }
1836
1837 emit_move_insn (operands[0], operands[1]);
1838
1839 if (extend != NULL_RTX)
1840 emit_insn (gen_insv (operands[0], GEN_INT (32), const0_rtx,
1841 extend));
1842
1843 return 1;
1844 }
1845 }
1846 /* Now have insn-emit do whatever it normally does. */
1847 return 0;
1848 }
1849
1850 /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning
1851 it will need a link/runtime reloc). */
1852
1853 int
reloc_needed(exp)1854 reloc_needed (exp)
1855 tree exp;
1856 {
1857 int reloc = 0;
1858
1859 switch (TREE_CODE (exp))
1860 {
1861 case ADDR_EXPR:
1862 return 1;
1863
1864 case PLUS_EXPR:
1865 case MINUS_EXPR:
1866 reloc = reloc_needed (TREE_OPERAND (exp, 0));
1867 reloc |= reloc_needed (TREE_OPERAND (exp, 1));
1868 break;
1869
1870 case NOP_EXPR:
1871 case CONVERT_EXPR:
1872 case NON_LVALUE_EXPR:
1873 reloc = reloc_needed (TREE_OPERAND (exp, 0));
1874 break;
1875
1876 case CONSTRUCTOR:
1877 {
1878 register tree link;
1879 for (link = CONSTRUCTOR_ELTS (exp); link; link = TREE_CHAIN (link))
1880 if (TREE_VALUE (link) != 0)
1881 reloc |= reloc_needed (TREE_VALUE (link));
1882 }
1883 break;
1884
1885 case ERROR_MARK:
1886 break;
1887
1888 default:
1889 break;
1890 }
1891 return reloc;
1892 }
1893
1894 /* Does operand (which is a symbolic_operand) live in text space?
1895 If so, SYMBOL_REF_FLAG, which is set by pa_encode_section_info,
1896 will be true. */
1897
1898 int
read_only_operand(operand,mode)1899 read_only_operand (operand, mode)
1900 rtx operand;
1901 enum machine_mode mode ATTRIBUTE_UNUSED;
1902 {
1903 if (GET_CODE (operand) == CONST)
1904 operand = XEXP (XEXP (operand, 0), 0);
1905 if (flag_pic)
1906 {
1907 if (GET_CODE (operand) == SYMBOL_REF)
1908 return SYMBOL_REF_FLAG (operand) && !CONSTANT_POOL_ADDRESS_P (operand);
1909 }
1910 else
1911 {
1912 if (GET_CODE (operand) == SYMBOL_REF)
1913 return SYMBOL_REF_FLAG (operand) || CONSTANT_POOL_ADDRESS_P (operand);
1914 }
1915 return 1;
1916 }
1917
1918
1919 /* Return the best assembler insn template
1920 for moving operands[1] into operands[0] as a fullword. */
1921 const char *
singlemove_string(operands)1922 singlemove_string (operands)
1923 rtx *operands;
1924 {
1925 HOST_WIDE_INT intval;
1926
1927 if (GET_CODE (operands[0]) == MEM)
1928 return "stw %r1,%0";
1929 if (GET_CODE (operands[1]) == MEM)
1930 return "ldw %1,%0";
1931 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1932 {
1933 long i;
1934 REAL_VALUE_TYPE d;
1935
1936 if (GET_MODE (operands[1]) != SFmode)
1937 abort ();
1938
1939 /* Translate the CONST_DOUBLE to a CONST_INT with the same target
1940 bit pattern. */
1941 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]);
1942 REAL_VALUE_TO_TARGET_SINGLE (d, i);
1943
1944 operands[1] = GEN_INT (i);
1945 /* Fall through to CONST_INT case. */
1946 }
1947 if (GET_CODE (operands[1]) == CONST_INT)
1948 {
1949 intval = INTVAL (operands[1]);
1950
1951 if (VAL_14_BITS_P (intval))
1952 return "ldi %1,%0";
1953 else if ((intval & 0x7ff) == 0)
1954 return "ldil L'%1,%0";
1955 else if (zdepi_cint_p (intval))
1956 return "{zdepi %Z1,%0|depwi,z %Z1,%0}";
1957 else
1958 return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
1959 }
1960 return "copy %1,%0";
1961 }
1962
1963
1964 /* Compute position (in OP[1]) and width (in OP[2])
1965 useful for copying IMM to a register using the zdepi
1966 instructions. Store the immediate value to insert in OP[0]. */
1967 static void
compute_zdepwi_operands(imm,op)1968 compute_zdepwi_operands (imm, op)
1969 unsigned HOST_WIDE_INT imm;
1970 unsigned *op;
1971 {
1972 int lsb, len;
1973
1974 /* Find the least significant set bit in IMM. */
1975 for (lsb = 0; lsb < 32; lsb++)
1976 {
1977 if ((imm & 1) != 0)
1978 break;
1979 imm >>= 1;
1980 }
1981
1982 /* Choose variants based on *sign* of the 5-bit field. */
1983 if ((imm & 0x10) == 0)
1984 len = (lsb <= 28) ? 4 : 32 - lsb;
1985 else
1986 {
1987 /* Find the width of the bitstring in IMM. */
1988 for (len = 5; len < 32; len++)
1989 {
1990 if ((imm & (1 << len)) == 0)
1991 break;
1992 }
1993
1994 /* Sign extend IMM as a 5-bit value. */
1995 imm = (imm & 0xf) - 0x10;
1996 }
1997
1998 op[0] = imm;
1999 op[1] = 31 - lsb;
2000 op[2] = len;
2001 }
2002
2003 /* Compute position (in OP[1]) and width (in OP[2])
2004 useful for copying IMM to a register using the depdi,z
2005 instructions. Store the immediate value to insert in OP[0]. */
2006 void
compute_zdepdi_operands(imm,op)2007 compute_zdepdi_operands (imm, op)
2008 unsigned HOST_WIDE_INT imm;
2009 unsigned *op;
2010 {
2011 HOST_WIDE_INT lsb, len;
2012
2013 /* Find the least significant set bit in IMM. */
2014 for (lsb = 0; lsb < HOST_BITS_PER_WIDE_INT; lsb++)
2015 {
2016 if ((imm & 1) != 0)
2017 break;
2018 imm >>= 1;
2019 }
2020
2021 /* Choose variants based on *sign* of the 5-bit field. */
2022 if ((imm & 0x10) == 0)
2023 len = ((lsb <= HOST_BITS_PER_WIDE_INT - 4)
2024 ? 4 : HOST_BITS_PER_WIDE_INT - lsb);
2025 else
2026 {
2027 /* Find the width of the bitstring in IMM. */
2028 for (len = 5; len < HOST_BITS_PER_WIDE_INT; len++)
2029 {
2030 if ((imm & ((unsigned HOST_WIDE_INT) 1 << len)) == 0)
2031 break;
2032 }
2033
2034 /* Sign extend IMM as a 5-bit value. */
2035 imm = (imm & 0xf) - 0x10;
2036 }
2037
2038 op[0] = imm;
2039 op[1] = 63 - lsb;
2040 op[2] = len;
2041 }
2042
2043 /* Output assembler code to perform a doubleword move insn
2044 with operands OPERANDS. */
2045
2046 const char *
output_move_double(operands)2047 output_move_double (operands)
2048 rtx *operands;
2049 {
2050 enum { REGOP, OFFSOP, MEMOP, CNSTOP, RNDOP } optype0, optype1;
2051 rtx latehalf[2];
2052 rtx addreg0 = 0, addreg1 = 0;
2053
2054 /* First classify both operands. */
2055
2056 if (REG_P (operands[0]))
2057 optype0 = REGOP;
2058 else if (offsettable_memref_p (operands[0]))
2059 optype0 = OFFSOP;
2060 else if (GET_CODE (operands[0]) == MEM)
2061 optype0 = MEMOP;
2062 else
2063 optype0 = RNDOP;
2064
2065 if (REG_P (operands[1]))
2066 optype1 = REGOP;
2067 else if (CONSTANT_P (operands[1]))
2068 optype1 = CNSTOP;
2069 else if (offsettable_memref_p (operands[1]))
2070 optype1 = OFFSOP;
2071 else if (GET_CODE (operands[1]) == MEM)
2072 optype1 = MEMOP;
2073 else
2074 optype1 = RNDOP;
2075
2076 /* Check for the cases that the operand constraints are not
2077 supposed to allow to happen. Abort if we get one,
2078 because generating code for these cases is painful. */
2079
2080 if (optype0 != REGOP && optype1 != REGOP)
2081 abort ();
2082
2083 /* Handle auto decrementing and incrementing loads and stores
2084 specifically, since the structure of the function doesn't work
2085 for them without major modification. Do it better when we learn
2086 this port about the general inc/dec addressing of PA.
2087 (This was written by tege. Chide him if it doesn't work.) */
2088
2089 if (optype0 == MEMOP)
2090 {
2091 /* We have to output the address syntax ourselves, since print_operand
2092 doesn't deal with the addresses we want to use. Fix this later. */
2093
2094 rtx addr = XEXP (operands[0], 0);
2095 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2096 {
2097 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2098
2099 operands[0] = XEXP (addr, 0);
2100 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
2101 abort ();
2102
2103 if (!reg_overlap_mentioned_p (high_reg, addr))
2104 {
2105 /* No overlap between high target register and address
2106 register. (We do this in a non-obvious way to
2107 save a register file writeback) */
2108 if (GET_CODE (addr) == POST_INC)
2109 return "{stws|stw},ma %1,8(%0)\n\tstw %R1,-4(%0)";
2110 return "{stws|stw},ma %1,-8(%0)\n\tstw %R1,12(%0)";
2111 }
2112 else
2113 abort ();
2114 }
2115 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2116 {
2117 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2118
2119 operands[0] = XEXP (addr, 0);
2120 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
2121 abort ();
2122
2123 if (!reg_overlap_mentioned_p (high_reg, addr))
2124 {
2125 /* No overlap between high target register and address
2126 register. (We do this in a non-obvious way to
2127 save a register file writeback) */
2128 if (GET_CODE (addr) == PRE_INC)
2129 return "{stws|stw},mb %1,8(%0)\n\tstw %R1,4(%0)";
2130 return "{stws|stw},mb %1,-8(%0)\n\tstw %R1,4(%0)";
2131 }
2132 else
2133 abort ();
2134 }
2135 }
2136 if (optype1 == MEMOP)
2137 {
2138 /* We have to output the address syntax ourselves, since print_operand
2139 doesn't deal with the addresses we want to use. Fix this later. */
2140
2141 rtx addr = XEXP (operands[1], 0);
2142 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2143 {
2144 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2145
2146 operands[1] = XEXP (addr, 0);
2147 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
2148 abort ();
2149
2150 if (!reg_overlap_mentioned_p (high_reg, addr))
2151 {
2152 /* No overlap between high target register and address
2153 register. (We do this in a non-obvious way to
2154 save a register file writeback) */
2155 if (GET_CODE (addr) == POST_INC)
2156 return "{ldws|ldw},ma 8(%1),%0\n\tldw -4(%1),%R0";
2157 return "{ldws|ldw},ma -8(%1),%0\n\tldw 12(%1),%R0";
2158 }
2159 else
2160 {
2161 /* This is an undefined situation. We should load into the
2162 address register *and* update that register. Probably
2163 we don't need to handle this at all. */
2164 if (GET_CODE (addr) == POST_INC)
2165 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma 8(%1),%0";
2166 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma -8(%1),%0";
2167 }
2168 }
2169 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2170 {
2171 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2172
2173 operands[1] = XEXP (addr, 0);
2174 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
2175 abort ();
2176
2177 if (!reg_overlap_mentioned_p (high_reg, addr))
2178 {
2179 /* No overlap between high target register and address
2180 register. (We do this in a non-obvious way to
2181 save a register file writeback) */
2182 if (GET_CODE (addr) == PRE_INC)
2183 return "{ldws|ldw},mb 8(%1),%0\n\tldw 4(%1),%R0";
2184 return "{ldws|ldw},mb -8(%1),%0\n\tldw 4(%1),%R0";
2185 }
2186 else
2187 {
2188 /* This is an undefined situation. We should load into the
2189 address register *and* update that register. Probably
2190 we don't need to handle this at all. */
2191 if (GET_CODE (addr) == PRE_INC)
2192 return "ldw 12(%1),%R0\n\t{ldws|ldw},mb 8(%1),%0";
2193 return "ldw -4(%1),%R0\n\t{ldws|ldw},mb -8(%1),%0";
2194 }
2195 }
2196 else if (GET_CODE (addr) == PLUS
2197 && GET_CODE (XEXP (addr, 0)) == MULT)
2198 {
2199 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2200
2201 if (!reg_overlap_mentioned_p (high_reg, addr))
2202 {
2203 rtx xoperands[3];
2204
2205 xoperands[0] = high_reg;
2206 xoperands[1] = XEXP (addr, 1);
2207 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2208 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2209 output_asm_insn ("{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0}",
2210 xoperands);
2211 return "ldw 4(%0),%R0\n\tldw 0(%0),%0";
2212 }
2213 else
2214 {
2215 rtx xoperands[3];
2216
2217 xoperands[0] = high_reg;
2218 xoperands[1] = XEXP (addr, 1);
2219 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2220 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2221 output_asm_insn ("{sh%O3addl %2,%1,%R0|shladd,l %2,%O3,%1,%R0}",
2222 xoperands);
2223 return "ldw 0(%R0),%0\n\tldw 4(%R0),%R0";
2224 }
2225 }
2226 }
2227
2228 /* If an operand is an unoffsettable memory ref, find a register
2229 we can increment temporarily to make it refer to the second word. */
2230
2231 if (optype0 == MEMOP)
2232 addreg0 = find_addr_reg (XEXP (operands[0], 0));
2233
2234 if (optype1 == MEMOP)
2235 addreg1 = find_addr_reg (XEXP (operands[1], 0));
2236
2237 /* Ok, we can do one word at a time.
2238 Normally we do the low-numbered word first.
2239
2240 In either case, set up in LATEHALF the operands to use
2241 for the high-numbered word and in some cases alter the
2242 operands in OPERANDS to be suitable for the low-numbered word. */
2243
2244 if (optype0 == REGOP)
2245 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2246 else if (optype0 == OFFSOP)
2247 latehalf[0] = adjust_address (operands[0], SImode, 4);
2248 else
2249 latehalf[0] = operands[0];
2250
2251 if (optype1 == REGOP)
2252 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2253 else if (optype1 == OFFSOP)
2254 latehalf[1] = adjust_address (operands[1], SImode, 4);
2255 else if (optype1 == CNSTOP)
2256 split_double (operands[1], &operands[1], &latehalf[1]);
2257 else
2258 latehalf[1] = operands[1];
2259
2260 /* If the first move would clobber the source of the second one,
2261 do them in the other order.
2262
2263 This can happen in two cases:
2264
2265 mem -> register where the first half of the destination register
2266 is the same register used in the memory's address. Reload
2267 can create such insns.
2268
2269 mem in this case will be either register indirect or register
2270 indirect plus a valid offset.
2271
2272 register -> register move where REGNO(dst) == REGNO(src + 1)
2273 someone (Tim/Tege?) claimed this can happen for parameter loads.
2274
2275 Handle mem -> register case first. */
2276 if (optype0 == REGOP
2277 && (optype1 == MEMOP || optype1 == OFFSOP)
2278 && refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2279 operands[1], 0))
2280 {
2281 /* Do the late half first. */
2282 if (addreg1)
2283 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2284 output_asm_insn (singlemove_string (latehalf), latehalf);
2285
2286 /* Then clobber. */
2287 if (addreg1)
2288 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2289 return singlemove_string (operands);
2290 }
2291
2292 /* Now handle register -> register case. */
2293 if (optype0 == REGOP && optype1 == REGOP
2294 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
2295 {
2296 output_asm_insn (singlemove_string (latehalf), latehalf);
2297 return singlemove_string (operands);
2298 }
2299
2300 /* Normal case: do the two words, low-numbered first. */
2301
2302 output_asm_insn (singlemove_string (operands), operands);
2303
2304 /* Make any unoffsettable addresses point at high-numbered word. */
2305 if (addreg0)
2306 output_asm_insn ("ldo 4(%0),%0", &addreg0);
2307 if (addreg1)
2308 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2309
2310 /* Do that word. */
2311 output_asm_insn (singlemove_string (latehalf), latehalf);
2312
2313 /* Undo the adds we just did. */
2314 if (addreg0)
2315 output_asm_insn ("ldo -4(%0),%0", &addreg0);
2316 if (addreg1)
2317 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2318
2319 return "";
2320 }
2321
2322 const char *
output_fp_move_double(operands)2323 output_fp_move_double (operands)
2324 rtx *operands;
2325 {
2326 if (FP_REG_P (operands[0]))
2327 {
2328 if (FP_REG_P (operands[1])
2329 || operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2330 output_asm_insn ("fcpy,dbl %f1,%0", operands);
2331 else
2332 output_asm_insn ("fldd%F1 %1,%0", operands);
2333 }
2334 else if (FP_REG_P (operands[1]))
2335 {
2336 output_asm_insn ("fstd%F0 %1,%0", operands);
2337 }
2338 else if (operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2339 {
2340 if (GET_CODE (operands[0]) == REG)
2341 {
2342 rtx xoperands[2];
2343 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2344 xoperands[0] = operands[0];
2345 output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands);
2346 }
2347 /* This is a pain. You have to be prepared to deal with an
2348 arbitrary address here including pre/post increment/decrement.
2349
2350 so avoid this in the MD. */
2351 else
2352 abort ();
2353 }
2354 else abort ();
2355 return "";
2356 }
2357
2358 /* Return a REG that occurs in ADDR with coefficient 1.
2359 ADDR can be effectively incremented by incrementing REG. */
2360
2361 static rtx
find_addr_reg(addr)2362 find_addr_reg (addr)
2363 rtx addr;
2364 {
2365 while (GET_CODE (addr) == PLUS)
2366 {
2367 if (GET_CODE (XEXP (addr, 0)) == REG)
2368 addr = XEXP (addr, 0);
2369 else if (GET_CODE (XEXP (addr, 1)) == REG)
2370 addr = XEXP (addr, 1);
2371 else if (CONSTANT_P (XEXP (addr, 0)))
2372 addr = XEXP (addr, 1);
2373 else if (CONSTANT_P (XEXP (addr, 1)))
2374 addr = XEXP (addr, 0);
2375 else
2376 abort ();
2377 }
2378 if (GET_CODE (addr) == REG)
2379 return addr;
2380 abort ();
2381 }
2382
2383 /* Emit code to perform a block move.
2384
2385 OPERANDS[0] is the destination pointer as a REG, clobbered.
2386 OPERANDS[1] is the source pointer as a REG, clobbered.
2387 OPERANDS[2] is a register for temporary storage.
2388 OPERANDS[4] is the size as a CONST_INT
2389 OPERANDS[3] is a register for temporary storage.
2390 OPERANDS[5] is the alignment safe to use, as a CONST_INT.
2391 OPERANDS[6] is another temporary register. */
2392
2393 const char *
output_block_move(operands,size_is_constant)2394 output_block_move (operands, size_is_constant)
2395 rtx *operands;
2396 int size_is_constant ATTRIBUTE_UNUSED;
2397 {
2398 int align = INTVAL (operands[5]);
2399 unsigned long n_bytes = INTVAL (operands[4]);
2400
2401 /* We can't move more than four bytes at a time because the PA
2402 has no longer integer move insns. (Could use fp mem ops?) */
2403 if (align > 4)
2404 align = 4;
2405
2406 /* Note that we know each loop below will execute at least twice
2407 (else we would have open-coded the copy). */
2408 switch (align)
2409 {
2410 case 4:
2411 /* Pre-adjust the loop counter. */
2412 operands[4] = GEN_INT (n_bytes - 8);
2413 output_asm_insn ("ldi %4,%2", operands);
2414
2415 /* Copying loop. */
2416 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2417 output_asm_insn ("{ldws|ldw},ma 4(%1),%6", operands);
2418 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2419 output_asm_insn ("addib,>= -8,%2,.-12", operands);
2420 output_asm_insn ("{stws|stw},ma %6,4(%0)", operands);
2421
2422 /* Handle the residual. There could be up to 7 bytes of
2423 residual to copy! */
2424 if (n_bytes % 8 != 0)
2425 {
2426 operands[4] = GEN_INT (n_bytes % 4);
2427 if (n_bytes % 8 >= 4)
2428 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2429 if (n_bytes % 4 != 0)
2430 output_asm_insn ("ldw 0(%1),%6", operands);
2431 if (n_bytes % 8 >= 4)
2432 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2433 if (n_bytes % 4 != 0)
2434 output_asm_insn ("{stbys|stby},e %6,%4(%0)", operands);
2435 }
2436 return "";
2437
2438 case 2:
2439 /* Pre-adjust the loop counter. */
2440 operands[4] = GEN_INT (n_bytes - 4);
2441 output_asm_insn ("ldi %4,%2", operands);
2442
2443 /* Copying loop. */
2444 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2445 output_asm_insn ("{ldhs|ldh},ma 2(%1),%6", operands);
2446 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2447 output_asm_insn ("addib,>= -4,%2,.-12", operands);
2448 output_asm_insn ("{sths|sth},ma %6,2(%0)", operands);
2449
2450 /* Handle the residual. */
2451 if (n_bytes % 4 != 0)
2452 {
2453 if (n_bytes % 4 >= 2)
2454 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2455 if (n_bytes % 2 != 0)
2456 output_asm_insn ("ldb 0(%1),%6", operands);
2457 if (n_bytes % 4 >= 2)
2458 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2459 if (n_bytes % 2 != 0)
2460 output_asm_insn ("stb %6,0(%0)", operands);
2461 }
2462 return "";
2463
2464 case 1:
2465 /* Pre-adjust the loop counter. */
2466 operands[4] = GEN_INT (n_bytes - 2);
2467 output_asm_insn ("ldi %4,%2", operands);
2468
2469 /* Copying loop. */
2470 output_asm_insn ("{ldbs|ldb},ma 1(%1),%3", operands);
2471 output_asm_insn ("{ldbs|ldb},ma 1(%1),%6", operands);
2472 output_asm_insn ("{stbs|stb},ma %3,1(%0)", operands);
2473 output_asm_insn ("addib,>= -2,%2,.-12", operands);
2474 output_asm_insn ("{stbs|stb},ma %6,1(%0)", operands);
2475
2476 /* Handle the residual. */
2477 if (n_bytes % 2 != 0)
2478 {
2479 output_asm_insn ("ldb 0(%1),%3", operands);
2480 output_asm_insn ("stb %3,0(%0)", operands);
2481 }
2482 return "";
2483
2484 default:
2485 abort ();
2486 }
2487 }
2488
2489 /* Count the number of insns necessary to handle this block move.
2490
2491 Basic structure is the same as emit_block_move, except that we
2492 count insns rather than emit them. */
2493
2494 static int
compute_movstrsi_length(insn)2495 compute_movstrsi_length (insn)
2496 rtx insn;
2497 {
2498 rtx pat = PATTERN (insn);
2499 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 7), 0));
2500 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 6), 0));
2501 unsigned int n_insns = 0;
2502
2503 /* We can't move more than four bytes at a time because the PA
2504 has no longer integer move insns. (Could use fp mem ops?) */
2505 if (align > 4)
2506 align = 4;
2507
2508 /* The basic copying loop. */
2509 n_insns = 6;
2510
2511 /* Residuals. */
2512 if (n_bytes % (2 * align) != 0)
2513 {
2514 if ((n_bytes % (2 * align)) >= align)
2515 n_insns += 2;
2516
2517 if ((n_bytes % align) != 0)
2518 n_insns += 2;
2519 }
2520
2521 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
2522 return n_insns * 4;
2523 }
2524
2525
2526 const char *
output_and(operands)2527 output_and (operands)
2528 rtx *operands;
2529 {
2530 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2531 {
2532 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2533 int ls0, ls1, ms0, p, len;
2534
2535 for (ls0 = 0; ls0 < 32; ls0++)
2536 if ((mask & (1 << ls0)) == 0)
2537 break;
2538
2539 for (ls1 = ls0; ls1 < 32; ls1++)
2540 if ((mask & (1 << ls1)) != 0)
2541 break;
2542
2543 for (ms0 = ls1; ms0 < 32; ms0++)
2544 if ((mask & (1 << ms0)) == 0)
2545 break;
2546
2547 if (ms0 != 32)
2548 abort ();
2549
2550 if (ls1 == 32)
2551 {
2552 len = ls0;
2553
2554 if (len == 0)
2555 abort ();
2556
2557 operands[2] = GEN_INT (len);
2558 return "{extru|extrw,u} %1,31,%2,%0";
2559 }
2560 else
2561 {
2562 /* We could use this `depi' for the case above as well, but `depi'
2563 requires one more register file access than an `extru'. */
2564
2565 p = 31 - ls0;
2566 len = ls1 - ls0;
2567
2568 operands[2] = GEN_INT (p);
2569 operands[3] = GEN_INT (len);
2570 return "{depi|depwi} 0,%2,%3,%0";
2571 }
2572 }
2573 else
2574 return "and %1,%2,%0";
2575 }
2576
2577 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
2578 storing the result in operands[0]. */
2579 const char *
output_64bit_and(operands)2580 output_64bit_and (operands)
2581 rtx *operands;
2582 {
2583 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2584 {
2585 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2586 int ls0, ls1, ms0, p, len;
2587
2588 for (ls0 = 0; ls0 < HOST_BITS_PER_WIDE_INT; ls0++)
2589 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls0)) == 0)
2590 break;
2591
2592 for (ls1 = ls0; ls1 < HOST_BITS_PER_WIDE_INT; ls1++)
2593 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls1)) != 0)
2594 break;
2595
2596 for (ms0 = ls1; ms0 < HOST_BITS_PER_WIDE_INT; ms0++)
2597 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ms0)) == 0)
2598 break;
2599
2600 if (ms0 != HOST_BITS_PER_WIDE_INT)
2601 abort ();
2602
2603 if (ls1 == HOST_BITS_PER_WIDE_INT)
2604 {
2605 len = ls0;
2606
2607 if (len == 0)
2608 abort ();
2609
2610 operands[2] = GEN_INT (len);
2611 return "extrd,u %1,63,%2,%0";
2612 }
2613 else
2614 {
2615 /* We could use this `depi' for the case above as well, but `depi'
2616 requires one more register file access than an `extru'. */
2617
2618 p = 63 - ls0;
2619 len = ls1 - ls0;
2620
2621 operands[2] = GEN_INT (p);
2622 operands[3] = GEN_INT (len);
2623 return "depdi 0,%2,%3,%0";
2624 }
2625 }
2626 else
2627 return "and %1,%2,%0";
2628 }
2629
2630 const char *
output_ior(operands)2631 output_ior (operands)
2632 rtx *operands;
2633 {
2634 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2635 int bs0, bs1, p, len;
2636
2637 if (INTVAL (operands[2]) == 0)
2638 return "copy %1,%0";
2639
2640 for (bs0 = 0; bs0 < 32; bs0++)
2641 if ((mask & (1 << bs0)) != 0)
2642 break;
2643
2644 for (bs1 = bs0; bs1 < 32; bs1++)
2645 if ((mask & (1 << bs1)) == 0)
2646 break;
2647
2648 if (bs1 != 32 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
2649 abort ();
2650
2651 p = 31 - bs0;
2652 len = bs1 - bs0;
2653
2654 operands[2] = GEN_INT (p);
2655 operands[3] = GEN_INT (len);
2656 return "{depi|depwi} -1,%2,%3,%0";
2657 }
2658
2659 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
2660 storing the result in operands[0]. */
2661 const char *
output_64bit_ior(operands)2662 output_64bit_ior (operands)
2663 rtx *operands;
2664 {
2665 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2666 int bs0, bs1, p, len;
2667
2668 if (INTVAL (operands[2]) == 0)
2669 return "copy %1,%0";
2670
2671 for (bs0 = 0; bs0 < HOST_BITS_PER_WIDE_INT; bs0++)
2672 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs0)) != 0)
2673 break;
2674
2675 for (bs1 = bs0; bs1 < HOST_BITS_PER_WIDE_INT; bs1++)
2676 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs1)) == 0)
2677 break;
2678
2679 if (bs1 != HOST_BITS_PER_WIDE_INT
2680 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
2681 abort ();
2682
2683 p = 63 - bs0;
2684 len = bs1 - bs0;
2685
2686 operands[2] = GEN_INT (p);
2687 operands[3] = GEN_INT (len);
2688 return "depdi -1,%2,%3,%0";
2689 }
2690
2691 /* Target hook for assembling integer objects. This code handles
2692 aligned SI and DI integers specially, since function references must
2693 be preceded by P%. */
2694
2695 static bool
pa_assemble_integer(x,size,aligned_p)2696 pa_assemble_integer (x, size, aligned_p)
2697 rtx x;
2698 unsigned int size;
2699 int aligned_p;
2700 {
2701 if (size == UNITS_PER_WORD && aligned_p
2702 && function_label_operand (x, VOIDmode))
2703 {
2704 fputs (size == 8? "\t.dword\tP%" : "\t.word\tP%", asm_out_file);
2705 output_addr_const (asm_out_file, x);
2706 fputc ('\n', asm_out_file);
2707 return true;
2708 }
2709 return default_assemble_integer (x, size, aligned_p);
2710 }
2711
2712 /* Output an ascii string. */
2713 void
output_ascii(file,p,size)2714 output_ascii (file, p, size)
2715 FILE *file;
2716 const char *p;
2717 int size;
2718 {
2719 int i;
2720 int chars_output;
2721 unsigned char partial_output[16]; /* Max space 4 chars can occupy. */
2722
2723 /* The HP assembler can only take strings of 256 characters at one
2724 time. This is a limitation on input line length, *not* the
2725 length of the string. Sigh. Even worse, it seems that the
2726 restriction is in number of input characters (see \xnn &
2727 \whatever). So we have to do this very carefully. */
2728
2729 fputs ("\t.STRING \"", file);
2730
2731 chars_output = 0;
2732 for (i = 0; i < size; i += 4)
2733 {
2734 int co = 0;
2735 int io = 0;
2736 for (io = 0, co = 0; io < MIN (4, size - i); io++)
2737 {
2738 register unsigned int c = (unsigned char) p[i + io];
2739
2740 if (c == '\"' || c == '\\')
2741 partial_output[co++] = '\\';
2742 if (c >= ' ' && c < 0177)
2743 partial_output[co++] = c;
2744 else
2745 {
2746 unsigned int hexd;
2747 partial_output[co++] = '\\';
2748 partial_output[co++] = 'x';
2749 hexd = c / 16 - 0 + '0';
2750 if (hexd > '9')
2751 hexd -= '9' - 'a' + 1;
2752 partial_output[co++] = hexd;
2753 hexd = c % 16 - 0 + '0';
2754 if (hexd > '9')
2755 hexd -= '9' - 'a' + 1;
2756 partial_output[co++] = hexd;
2757 }
2758 }
2759 if (chars_output + co > 243)
2760 {
2761 fputs ("\"\n\t.STRING \"", file);
2762 chars_output = 0;
2763 }
2764 fwrite (partial_output, 1, (size_t) co, file);
2765 chars_output += co;
2766 co = 0;
2767 }
2768 fputs ("\"\n", file);
2769 }
2770
2771 /* Try to rewrite floating point comparisons & branches to avoid
2772 useless add,tr insns.
2773
2774 CHECK_NOTES is nonzero if we should examine REG_DEAD notes
2775 to see if FPCC is dead. CHECK_NOTES is nonzero for the
2776 first attempt to remove useless add,tr insns. It is zero
2777 for the second pass as reorg sometimes leaves bogus REG_DEAD
2778 notes lying around.
2779
2780 When CHECK_NOTES is zero we can only eliminate add,tr insns
2781 when there's a 1:1 correspondence between fcmp and ftest/fbranch
2782 instructions. */
2783 static void
remove_useless_addtr_insns(insns,check_notes)2784 remove_useless_addtr_insns (insns, check_notes)
2785 rtx insns;
2786 int check_notes;
2787 {
2788 rtx insn;
2789 static int pass = 0;
2790
2791 /* This is fairly cheap, so always run it when optimizing. */
2792 if (optimize > 0)
2793 {
2794 int fcmp_count = 0;
2795 int fbranch_count = 0;
2796
2797 /* Walk all the insns in this function looking for fcmp & fbranch
2798 instructions. Keep track of how many of each we find. */
2799 insns = get_insns ();
2800 for (insn = insns; insn; insn = next_insn (insn))
2801 {
2802 rtx tmp;
2803
2804 /* Ignore anything that isn't an INSN or a JUMP_INSN. */
2805 if (GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN)
2806 continue;
2807
2808 tmp = PATTERN (insn);
2809
2810 /* It must be a set. */
2811 if (GET_CODE (tmp) != SET)
2812 continue;
2813
2814 /* If the destination is CCFP, then we've found an fcmp insn. */
2815 tmp = SET_DEST (tmp);
2816 if (GET_CODE (tmp) == REG && REGNO (tmp) == 0)
2817 {
2818 fcmp_count++;
2819 continue;
2820 }
2821
2822 tmp = PATTERN (insn);
2823 /* If this is an fbranch instruction, bump the fbranch counter. */
2824 if (GET_CODE (tmp) == SET
2825 && SET_DEST (tmp) == pc_rtx
2826 && GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE
2827 && GET_CODE (XEXP (SET_SRC (tmp), 0)) == NE
2828 && GET_CODE (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == REG
2829 && REGNO (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == 0)
2830 {
2831 fbranch_count++;
2832 continue;
2833 }
2834 }
2835
2836
2837 /* Find all floating point compare + branch insns. If possible,
2838 reverse the comparison & the branch to avoid add,tr insns. */
2839 for (insn = insns; insn; insn = next_insn (insn))
2840 {
2841 rtx tmp, next;
2842
2843 /* Ignore anything that isn't an INSN. */
2844 if (GET_CODE (insn) != INSN)
2845 continue;
2846
2847 tmp = PATTERN (insn);
2848
2849 /* It must be a set. */
2850 if (GET_CODE (tmp) != SET)
2851 continue;
2852
2853 /* The destination must be CCFP, which is register zero. */
2854 tmp = SET_DEST (tmp);
2855 if (GET_CODE (tmp) != REG || REGNO (tmp) != 0)
2856 continue;
2857
2858 /* INSN should be a set of CCFP.
2859
2860 See if the result of this insn is used in a reversed FP
2861 conditional branch. If so, reverse our condition and
2862 the branch. Doing so avoids useless add,tr insns. */
2863 next = next_insn (insn);
2864 while (next)
2865 {
2866 /* Jumps, calls and labels stop our search. */
2867 if (GET_CODE (next) == JUMP_INSN
2868 || GET_CODE (next) == CALL_INSN
2869 || GET_CODE (next) == CODE_LABEL)
2870 break;
2871
2872 /* As does another fcmp insn. */
2873 if (GET_CODE (next) == INSN
2874 && GET_CODE (PATTERN (next)) == SET
2875 && GET_CODE (SET_DEST (PATTERN (next))) == REG
2876 && REGNO (SET_DEST (PATTERN (next))) == 0)
2877 break;
2878
2879 next = next_insn (next);
2880 }
2881
2882 /* Is NEXT_INSN a branch? */
2883 if (next
2884 && GET_CODE (next) == JUMP_INSN)
2885 {
2886 rtx pattern = PATTERN (next);
2887
2888 /* If it a reversed fp conditional branch (eg uses add,tr)
2889 and CCFP dies, then reverse our conditional and the branch
2890 to avoid the add,tr. */
2891 if (GET_CODE (pattern) == SET
2892 && SET_DEST (pattern) == pc_rtx
2893 && GET_CODE (SET_SRC (pattern)) == IF_THEN_ELSE
2894 && GET_CODE (XEXP (SET_SRC (pattern), 0)) == NE
2895 && GET_CODE (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == REG
2896 && REGNO (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == 0
2897 && GET_CODE (XEXP (SET_SRC (pattern), 1)) == PC
2898 && (fcmp_count == fbranch_count
2899 || (check_notes
2900 && find_regno_note (next, REG_DEAD, 0))))
2901 {
2902 /* Reverse the branch. */
2903 tmp = XEXP (SET_SRC (pattern), 1);
2904 XEXP (SET_SRC (pattern), 1) = XEXP (SET_SRC (pattern), 2);
2905 XEXP (SET_SRC (pattern), 2) = tmp;
2906 INSN_CODE (next) = -1;
2907
2908 /* Reverse our condition. */
2909 tmp = PATTERN (insn);
2910 PUT_CODE (XEXP (tmp, 1),
2911 (reverse_condition_maybe_unordered
2912 (GET_CODE (XEXP (tmp, 1)))));
2913 }
2914 }
2915 }
2916 }
2917
2918 pass = !pass;
2919
2920 }
2921
2922 /* You may have trouble believing this, but this is the 32 bit HP-PA
2923 stack layout. Wow.
2924
2925 Offset Contents
2926
2927 Variable arguments (optional; any number may be allocated)
2928
2929 SP-(4*(N+9)) arg word N
2930 : :
2931 SP-56 arg word 5
2932 SP-52 arg word 4
2933
2934 Fixed arguments (must be allocated; may remain unused)
2935
2936 SP-48 arg word 3
2937 SP-44 arg word 2
2938 SP-40 arg word 1
2939 SP-36 arg word 0
2940
2941 Frame Marker
2942
2943 SP-32 External Data Pointer (DP)
2944 SP-28 External sr4
2945 SP-24 External/stub RP (RP')
2946 SP-20 Current RP
2947 SP-16 Static Link
2948 SP-12 Clean up
2949 SP-8 Calling Stub RP (RP'')
2950 SP-4 Previous SP
2951
2952 Top of Frame
2953
2954 SP-0 Stack Pointer (points to next available address)
2955
2956 */
2957
2958 /* This function saves registers as follows. Registers marked with ' are
2959 this function's registers (as opposed to the previous function's).
2960 If a frame_pointer isn't needed, r4 is saved as a general register;
2961 the space for the frame pointer is still allocated, though, to keep
2962 things simple.
2963
2964
2965 Top of Frame
2966
2967 SP (FP') Previous FP
2968 SP + 4 Alignment filler (sigh)
2969 SP + 8 Space for locals reserved here.
2970 .
2971 .
2972 .
2973 SP + n All call saved register used.
2974 .
2975 .
2976 .
2977 SP + o All call saved fp registers used.
2978 .
2979 .
2980 .
2981 SP + p (SP') points to next available address.
2982
2983 */
2984
2985 /* Global variables set by output_function_prologue(). */
2986 /* Size of frame. Need to know this to emit return insns from
2987 leaf procedures. */
2988 static int actual_fsize;
2989 static int local_fsize, save_fregs;
2990
2991 /* Emit RTL to store REG at the memory location specified by BASE+DISP.
2992 Handle case where DISP > 8k by using the add_high_const patterns.
2993
2994 Note in DISP > 8k case, we will leave the high part of the address
2995 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
2996
2997 static void
store_reg(reg,disp,base)2998 store_reg (reg, disp, base)
2999 int reg, disp, base;
3000 {
3001 rtx insn, dest, src, basereg;
3002
3003 src = gen_rtx_REG (word_mode, reg);
3004 basereg = gen_rtx_REG (Pmode, base);
3005 if (VAL_14_BITS_P (disp))
3006 {
3007 dest = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
3008 insn = emit_move_insn (dest, src);
3009 }
3010 else
3011 {
3012 rtx delta = GEN_INT (disp);
3013 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
3014 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3015 emit_move_insn (tmpreg, high);
3016 dest = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3017 insn = emit_move_insn (dest, src);
3018 if (DO_FRAME_NOTES)
3019 {
3020 REG_NOTES (insn)
3021 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3022 gen_rtx_SET (VOIDmode,
3023 gen_rtx_MEM (word_mode,
3024 gen_rtx_PLUS (word_mode, basereg,
3025 delta)),
3026 src),
3027 REG_NOTES (insn));
3028 }
3029 }
3030
3031 if (DO_FRAME_NOTES)
3032 RTX_FRAME_RELATED_P (insn) = 1;
3033 }
3034
3035 /* Emit RTL to store REG at the memory location specified by BASE and then
3036 add MOD to BASE. MOD must be <= 8k. */
3037
3038 static void
store_reg_modify(base,reg,mod)3039 store_reg_modify (base, reg, mod)
3040 int base, reg, mod;
3041 {
3042 rtx insn, basereg, srcreg, delta;
3043
3044 if (! VAL_14_BITS_P (mod))
3045 abort ();
3046
3047 basereg = gen_rtx_REG (Pmode, base);
3048 srcreg = gen_rtx_REG (word_mode, reg);
3049 delta = GEN_INT (mod);
3050
3051 insn = emit_insn (gen_post_store (basereg, srcreg, delta));
3052 if (DO_FRAME_NOTES)
3053 {
3054 RTX_FRAME_RELATED_P (insn) = 1;
3055
3056 /* RTX_FRAME_RELATED_P must be set on each frame related set
3057 in a parallel with more than one element. Don't set
3058 RTX_FRAME_RELATED_P in the first set if reg is temporary
3059 register 1. The effect of this operation is recorded in
3060 the initial copy. */
3061 if (reg != 1)
3062 {
3063 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 0)) = 1;
3064 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1;
3065 }
3066 else
3067 {
3068 /* The first element of a PARALLEL is always processed if it is
3069 a SET. Thus, we need an expression list for this case. */
3070 REG_NOTES (insn)
3071 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3072 gen_rtx_SET (VOIDmode, basereg,
3073 gen_rtx_PLUS (word_mode, basereg, delta)),
3074 REG_NOTES (insn));
3075 }
3076 }
3077 }
3078
3079 /* Emit RTL to set REG to the value specified by BASE+DISP. Handle case
3080 where DISP > 8k by using the add_high_const patterns. NOTE indicates
3081 whether to add a frame note or not.
3082
3083 In the DISP > 8k case, we leave the high part of the address in %r1.
3084 There is code in expand_hppa_{prologue,epilogue} that knows about this. */
3085
3086 static void
set_reg_plus_d(reg,base,disp,note)3087 set_reg_plus_d (reg, base, disp, note)
3088 int reg, base, disp, note;
3089 {
3090 rtx insn;
3091
3092 if (VAL_14_BITS_P (disp))
3093 {
3094 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3095 plus_constant (gen_rtx_REG (Pmode, base), disp));
3096 }
3097 else
3098 {
3099 rtx basereg = gen_rtx_REG (Pmode, base);
3100 rtx delta = GEN_INT (disp);
3101
3102 emit_move_insn (gen_rtx_REG (Pmode, 1),
3103 gen_rtx_PLUS (Pmode, basereg,
3104 gen_rtx_HIGH (Pmode, delta)));
3105 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3106 gen_rtx_LO_SUM (Pmode, gen_rtx_REG (Pmode, 1),
3107 delta));
3108 }
3109
3110 if (DO_FRAME_NOTES && note)
3111 RTX_FRAME_RELATED_P (insn) = 1;
3112 }
3113
3114 int
compute_frame_size(size,fregs_live)3115 compute_frame_size (size, fregs_live)
3116 int size;
3117 int *fregs_live;
3118 {
3119 int i, fsize;
3120
3121 /* Space for frame pointer + filler. If any frame is allocated
3122 we need to add this in because of STARTING_FRAME_OFFSET.
3123
3124 Similar code also appears in hppa_expand_prologue. Change both
3125 of them at the same time. */
3126 fsize = size + (size || frame_pointer_needed ? STARTING_FRAME_OFFSET : 0);
3127
3128 /* If the current function calls __builtin_eh_return, then we need
3129 to allocate stack space for registers that will hold data for
3130 the exception handler. */
3131 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3132 {
3133 unsigned int i;
3134
3135 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
3136 continue;
3137 fsize += i * UNITS_PER_WORD;
3138 }
3139
3140 /* Account for space used by the callee general register saves. */
3141 for (i = 18; i >= 3; i--)
3142 if (regs_ever_live[i])
3143 fsize += UNITS_PER_WORD;
3144
3145 /* Round the stack. */
3146 fsize = (fsize + 7) & ~7;
3147
3148 /* Account for space used by the callee floating point register saves. */
3149 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3150 if (regs_ever_live[i]
3151 || (! TARGET_64BIT && regs_ever_live[i + 1]))
3152 {
3153 if (fregs_live)
3154 *fregs_live = 1;
3155
3156 /* We always save both halves of the FP register, so always
3157 increment the frame size by 8 bytes. */
3158 fsize += 8;
3159 }
3160
3161 /* The various ABIs include space for the outgoing parameters in the
3162 size of the current function's stack frame. */
3163 fsize += current_function_outgoing_args_size;
3164
3165 /* Allocate space for the fixed frame marker. This space must be
3166 allocated for any function that makes calls or allocates
3167 stack space. */
3168 if (!current_function_is_leaf || fsize)
3169 fsize += TARGET_64BIT ? 48 : 32;
3170
3171 return ((fsize + PREFERRED_STACK_BOUNDARY / 8 - 1)
3172 & ~(PREFERRED_STACK_BOUNDARY / 8 - 1));
3173 }
3174
3175 /* Generate the assembly code for function entry. FILE is a stdio
3176 stream to output the code to. SIZE is an int: how many units of
3177 temporary storage to allocate.
3178
3179 Refer to the array `regs_ever_live' to determine which registers to
3180 save; `regs_ever_live[I]' is nonzero if register number I is ever
3181 used in the function. This function is responsible for knowing
3182 which registers should not be saved even if used. */
3183
3184 /* On HP-PA, move-double insns between fpu and cpu need an 8-byte block
3185 of memory. If any fpu reg is used in the function, we allocate
3186 such a block here, at the bottom of the frame, just in case it's needed.
3187
3188 If this function is a leaf procedure, then we may choose not
3189 to do a "save" insn. The decision about whether or not
3190 to do this is made in regclass.c. */
3191
3192 static void
pa_output_function_prologue(file,size)3193 pa_output_function_prologue (file, size)
3194 FILE *file;
3195 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
3196 {
3197 /* The function's label and associated .PROC must never be
3198 separated and must be output *after* any profiling declarations
3199 to avoid changing spaces/subspaces within a procedure. */
3200 ASM_OUTPUT_LABEL (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
3201 fputs ("\t.PROC\n", file);
3202
3203 /* hppa_expand_prologue does the dirty work now. We just need
3204 to output the assembler directives which denote the start
3205 of a function. */
3206 fprintf (file, "\t.CALLINFO FRAME=%d", actual_fsize);
3207 if (regs_ever_live[2])
3208 fputs (",CALLS,SAVE_RP", file);
3209 else
3210 fputs (",NO_CALLS", file);
3211
3212 /* The SAVE_SP flag is used to indicate that register %r3 is stored
3213 at the beginning of the frame and that it is used as the frame
3214 pointer for the frame. We do this because our current frame
3215 layout doesn't conform to that specified in the the HP runtime
3216 documentation and we need a way to indicate to programs such as
3217 GDB where %r3 is saved. The SAVE_SP flag was chosen because it
3218 isn't used by HP compilers but is supported by the assembler.
3219 However, SAVE_SP is supposed to indicate that the previous stack
3220 pointer has been saved in the frame marker. */
3221 if (frame_pointer_needed)
3222 fputs (",SAVE_SP", file);
3223
3224 /* Pass on information about the number of callee register saves
3225 performed in the prologue.
3226
3227 The compiler is supposed to pass the highest register number
3228 saved, the assembler then has to adjust that number before
3229 entering it into the unwind descriptor (to account for any
3230 caller saved registers with lower register numbers than the
3231 first callee saved register). */
3232 if (gr_saved)
3233 fprintf (file, ",ENTRY_GR=%d", gr_saved + 2);
3234
3235 if (fr_saved)
3236 fprintf (file, ",ENTRY_FR=%d", fr_saved + 11);
3237
3238 fputs ("\n\t.ENTRY\n", file);
3239
3240 remove_useless_addtr_insns (get_insns (), 0);
3241 }
3242
3243 void
hppa_expand_prologue()3244 hppa_expand_prologue ()
3245 {
3246 int size = get_frame_size ();
3247 int merge_sp_adjust_with_store = 0;
3248 int i, offset;
3249 rtx insn, tmpreg;
3250
3251 gr_saved = 0;
3252 fr_saved = 0;
3253 save_fregs = 0;
3254
3255 if (warn_stack_larger_than && size > stack_larger_than_size)
3256 warning ("stack usage is %d bytes", size);
3257
3258 /* Allocate space for frame pointer + filler. If any frame is allocated
3259 we need to add this in because of STARTING_FRAME_OFFSET.
3260
3261 Similar code also appears in compute_frame_size. Change both
3262 of them at the same time. */
3263 local_fsize = size + (size || frame_pointer_needed
3264 ? STARTING_FRAME_OFFSET : 0);
3265
3266 actual_fsize = compute_frame_size (size, &save_fregs);
3267
3268 /* Compute a few things we will use often. */
3269 tmpreg = gen_rtx_REG (word_mode, 1);
3270
3271 /* Save RP first. The calling conventions manual states RP will
3272 always be stored into the caller's frame at sp - 20 or sp - 16
3273 depending on which ABI is in use. */
3274 if (regs_ever_live[2] || current_function_calls_eh_return)
3275 store_reg (2, TARGET_64BIT ? -16 : -20, STACK_POINTER_REGNUM);
3276
3277 /* Allocate the local frame and set up the frame pointer if needed. */
3278 if (actual_fsize != 0)
3279 {
3280 if (frame_pointer_needed)
3281 {
3282 /* Copy the old frame pointer temporarily into %r1. Set up the
3283 new stack pointer, then store away the saved old frame pointer
3284 into the stack at sp and at the same time update the stack
3285 pointer by actual_fsize bytes. Two versions, first
3286 handles small (<8k) frames. The second handles large (>=8k)
3287 frames. */
3288 insn = emit_move_insn (tmpreg, frame_pointer_rtx);
3289 if (DO_FRAME_NOTES)
3290 {
3291 /* We need to record the frame pointer save here since the
3292 new frame pointer is set in the following insn. */
3293 RTX_FRAME_RELATED_P (insn) = 1;
3294 REG_NOTES (insn)
3295 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3296 gen_rtx_SET (VOIDmode,
3297 gen_rtx_MEM (word_mode, stack_pointer_rtx),
3298 frame_pointer_rtx),
3299 REG_NOTES (insn));
3300 }
3301
3302 insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
3303 if (DO_FRAME_NOTES)
3304 RTX_FRAME_RELATED_P (insn) = 1;
3305
3306 if (VAL_14_BITS_P (actual_fsize))
3307 store_reg_modify (STACK_POINTER_REGNUM, 1, actual_fsize);
3308 else
3309 {
3310 /* It is incorrect to store the saved frame pointer at *sp,
3311 then increment sp (writes beyond the current stack boundary).
3312
3313 So instead use stwm to store at *sp and post-increment the
3314 stack pointer as an atomic operation. Then increment sp to
3315 finish allocating the new frame. */
3316 int adjust1 = 8192 - 64;
3317 int adjust2 = actual_fsize - adjust1;
3318
3319 store_reg_modify (STACK_POINTER_REGNUM, 1, adjust1);
3320 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3321 adjust2, 1);
3322 }
3323
3324 /* We set SAVE_SP in frames that need a frame pointer. Thus,
3325 we need to store the previous stack pointer (frame pointer)
3326 into the frame marker on targets that use the HP unwind
3327 library. This allows the HP unwind library to be used to
3328 unwind GCC frames. However, we are not fully compatible
3329 with the HP library because our frame layout differs from
3330 that specified in the HP runtime specification.
3331
3332 We don't want a frame note on this instruction as the frame
3333 marker moves during dynamic stack allocation.
3334
3335 This instruction also serves as a blockage to prevent
3336 register spills from being scheduled before the stack
3337 pointer is raised. This is necessary as we store
3338 registers using the frame pointer as a base register,
3339 and the frame pointer is set before sp is raised. */
3340 if (TARGET_HPUX_UNWIND_LIBRARY)
3341 {
3342 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx,
3343 GEN_INT (TARGET_64BIT ? -8 : -4));
3344
3345 emit_move_insn (gen_rtx_MEM (word_mode, addr),
3346 frame_pointer_rtx);
3347 }
3348 else
3349 emit_insn (gen_blockage ());
3350 }
3351 /* no frame pointer needed. */
3352 else
3353 {
3354 /* In some cases we can perform the first callee register save
3355 and allocating the stack frame at the same time. If so, just
3356 make a note of it and defer allocating the frame until saving
3357 the callee registers. */
3358 if (VAL_14_BITS_P (actual_fsize) && local_fsize == 0)
3359 merge_sp_adjust_with_store = 1;
3360 /* Can not optimize. Adjust the stack frame by actual_fsize
3361 bytes. */
3362 else
3363 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3364 actual_fsize, 1);
3365 }
3366 }
3367
3368 /* Normal register save.
3369
3370 Do not save the frame pointer in the frame_pointer_needed case. It
3371 was done earlier. */
3372 if (frame_pointer_needed)
3373 {
3374 offset = local_fsize;
3375
3376 /* Saving the EH return data registers in the frame is the simplest
3377 way to get the frame unwind information emitted. We put them
3378 just before the general registers. */
3379 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3380 {
3381 unsigned int i, regno;
3382
3383 for (i = 0; ; ++i)
3384 {
3385 regno = EH_RETURN_DATA_REGNO (i);
3386 if (regno == INVALID_REGNUM)
3387 break;
3388
3389 store_reg (regno, offset, FRAME_POINTER_REGNUM);
3390 offset += UNITS_PER_WORD;
3391 }
3392 }
3393
3394 for (i = 18; i >= 4; i--)
3395 if (regs_ever_live[i] && ! call_used_regs[i])
3396 {
3397 store_reg (i, offset, FRAME_POINTER_REGNUM);
3398 offset += UNITS_PER_WORD;
3399 gr_saved++;
3400 }
3401 /* Account for %r3 which is saved in a special place. */
3402 gr_saved++;
3403 }
3404 /* No frame pointer needed. */
3405 else
3406 {
3407 offset = local_fsize - actual_fsize;
3408
3409 /* Saving the EH return data registers in the frame is the simplest
3410 way to get the frame unwind information emitted. */
3411 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3412 {
3413 unsigned int i, regno;
3414
3415 for (i = 0; ; ++i)
3416 {
3417 regno = EH_RETURN_DATA_REGNO (i);
3418 if (regno == INVALID_REGNUM)
3419 break;
3420
3421 /* If merge_sp_adjust_with_store is nonzero, then we can
3422 optimize the first save. */
3423 if (merge_sp_adjust_with_store)
3424 {
3425 store_reg_modify (STACK_POINTER_REGNUM, regno, -offset);
3426 merge_sp_adjust_with_store = 0;
3427 }
3428 else
3429 store_reg (regno, offset, STACK_POINTER_REGNUM);
3430 offset += UNITS_PER_WORD;
3431 }
3432 }
3433
3434 for (i = 18; i >= 3; i--)
3435 if (regs_ever_live[i] && ! call_used_regs[i])
3436 {
3437 /* If merge_sp_adjust_with_store is nonzero, then we can
3438 optimize the first GR save. */
3439 if (merge_sp_adjust_with_store)
3440 {
3441 store_reg_modify (STACK_POINTER_REGNUM, i, -offset);
3442 merge_sp_adjust_with_store = 0;
3443 }
3444 else
3445 store_reg (i, offset, STACK_POINTER_REGNUM);
3446 offset += UNITS_PER_WORD;
3447 gr_saved++;
3448 }
3449
3450 /* If we wanted to merge the SP adjustment with a GR save, but we never
3451 did any GR saves, then just emit the adjustment here. */
3452 if (merge_sp_adjust_with_store)
3453 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3454 actual_fsize, 1);
3455 }
3456
3457 /* The hppa calling conventions say that %r19, the pic offset
3458 register, is saved at sp - 32 (in this function's frame)
3459 when generating PIC code. FIXME: What is the correct thing
3460 to do for functions which make no calls and allocate no
3461 frame? Do we need to allocate a frame, or can we just omit
3462 the save? For now we'll just omit the save. */
3463 if (flag_pic && actual_fsize != 0 && !TARGET_64BIT)
3464 store_reg (PIC_OFFSET_TABLE_REGNUM, -32, STACK_POINTER_REGNUM);
3465
3466 /* Align pointer properly (doubleword boundary). */
3467 offset = (offset + 7) & ~7;
3468
3469 /* Floating point register store. */
3470 if (save_fregs)
3471 {
3472 rtx base;
3473
3474 /* First get the frame or stack pointer to the start of the FP register
3475 save area. */
3476 if (frame_pointer_needed)
3477 {
3478 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
3479 base = frame_pointer_rtx;
3480 }
3481 else
3482 {
3483 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
3484 base = stack_pointer_rtx;
3485 }
3486
3487 /* Now actually save the FP registers. */
3488 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3489 {
3490 if (regs_ever_live[i]
3491 || (! TARGET_64BIT && regs_ever_live[i + 1]))
3492 {
3493 rtx addr, insn, reg;
3494 addr = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
3495 reg = gen_rtx_REG (DFmode, i);
3496 insn = emit_move_insn (addr, reg);
3497 if (DO_FRAME_NOTES)
3498 {
3499 RTX_FRAME_RELATED_P (insn) = 1;
3500 if (TARGET_64BIT)
3501 {
3502 rtx mem = gen_rtx_MEM (DFmode,
3503 plus_constant (base, offset));
3504 REG_NOTES (insn)
3505 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3506 gen_rtx_SET (VOIDmode, mem, reg),
3507 REG_NOTES (insn));
3508 }
3509 else
3510 {
3511 rtx meml = gen_rtx_MEM (SFmode,
3512 plus_constant (base, offset));
3513 rtx memr = gen_rtx_MEM (SFmode,
3514 plus_constant (base, offset + 4));
3515 rtx regl = gen_rtx_REG (SFmode, i);
3516 rtx regr = gen_rtx_REG (SFmode, i + 1);
3517 rtx setl = gen_rtx_SET (VOIDmode, meml, regl);
3518 rtx setr = gen_rtx_SET (VOIDmode, memr, regr);
3519 rtvec vec;
3520
3521 RTX_FRAME_RELATED_P (setl) = 1;
3522 RTX_FRAME_RELATED_P (setr) = 1;
3523 vec = gen_rtvec (2, setl, setr);
3524 REG_NOTES (insn)
3525 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3526 gen_rtx_SEQUENCE (VOIDmode, vec),
3527 REG_NOTES (insn));
3528 }
3529 }
3530 offset += GET_MODE_SIZE (DFmode);
3531 fr_saved++;
3532 }
3533 }
3534 }
3535
3536 /* FIXME: expand_call and expand_millicode_call need to be fixed to
3537 prevent insns with frame notes being scheduled in the delay slot
3538 of calls. This causes problems because the dwarf2 output code
3539 processes the insn list serially. For now, limit the migration
3540 of prologue insns with a blockage. */
3541 if (DO_FRAME_NOTES)
3542 emit_insn (gen_blockage ());
3543 }
3544
3545 /* Emit RTL to load REG from the memory location specified by BASE+DISP.
3546 Handle case where DISP > 8k by using the add_high_const patterns. */
3547
3548 static void
load_reg(reg,disp,base)3549 load_reg (reg, disp, base)
3550 int reg, disp, base;
3551 {
3552 rtx src, dest, basereg;
3553
3554 dest = gen_rtx_REG (word_mode, reg);
3555 basereg = gen_rtx_REG (Pmode, base);
3556 if (VAL_14_BITS_P (disp))
3557 {
3558 src = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
3559 emit_move_insn (dest, src);
3560 }
3561 else
3562 {
3563 rtx delta = GEN_INT (disp);
3564 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
3565 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3566 emit_move_insn (tmpreg, high);
3567 src = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3568 emit_move_insn (dest, src);
3569 }
3570 }
3571
3572 /* This function generates the assembly code for function exit.
3573 Args are as for output_function_prologue ().
3574
3575 The function epilogue should not depend on the current stack
3576 pointer! It should use the frame pointer only. This is mandatory
3577 because of alloca; we also take advantage of it to omit stack
3578 adjustments before returning. */
3579
3580 static void
pa_output_function_epilogue(file,size)3581 pa_output_function_epilogue (file, size)
3582 FILE *file;
3583 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
3584 {
3585 int last_address = 0;
3586 rtx insn = get_last_insn ();
3587
3588 /* hppa_expand_epilogue does the dirty work now. We just need
3589 to output the assembler directives which denote the end
3590 of a function.
3591
3592 To make debuggers happy, emit a nop if the epilogue was completely
3593 eliminated due to a volatile call as the last insn in the
3594 current function. That way the return address (in %r2) will
3595 always point to a valid instruction in the current function. */
3596
3597 /* Get the last real insn. */
3598 if (GET_CODE (insn) == NOTE)
3599 insn = prev_real_insn (insn);
3600
3601 /* If it is a sequence, then look inside. */
3602 if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
3603 insn = XVECEXP (PATTERN (insn), 0, 0);
3604
3605 /* If insn is a CALL_INSN, then it must be a call to a volatile
3606 function (otherwise there would be epilogue insns). */
3607 if (insn && GET_CODE (insn) == CALL_INSN)
3608 {
3609 fputs ("\tnop\n", file);
3610 last_address += 4;
3611 }
3612
3613 fputs ("\t.EXIT\n\t.PROCEND\n", file);
3614
3615 /* Finally, update the total number of code bytes output so far. */
3616 if ((TARGET_PORTABLE_RUNTIME || !TARGET_GAS || !TARGET_SOM)
3617 && !flag_function_sections)
3618 {
3619 if (INSN_ADDRESSES_SET_P ())
3620 {
3621 unsigned long old_total = total_code_bytes;
3622
3623 insn = get_last_nonnote_insn ();
3624 last_address += INSN_ADDRESSES (INSN_UID (insn));
3625 if (INSN_P (insn))
3626 last_address += insn_default_length (insn);
3627
3628 total_code_bytes += last_address;
3629 total_code_bytes += FUNCTION_BOUNDARY / BITS_PER_UNIT;
3630
3631 /* Be prepared to handle overflows. */
3632 if (old_total > total_code_bytes)
3633 total_code_bytes = -1;
3634 }
3635 else
3636 total_code_bytes = -1;
3637 }
3638 }
3639
3640 void
hppa_expand_epilogue()3641 hppa_expand_epilogue ()
3642 {
3643 rtx tmpreg;
3644 int offset, i;
3645 int merge_sp_adjust_with_load = 0;
3646 int ret_off = 0;
3647
3648 /* We will use this often. */
3649 tmpreg = gen_rtx_REG (word_mode, 1);
3650
3651 /* Try to restore RP early to avoid load/use interlocks when
3652 RP gets used in the return (bv) instruction. This appears to still
3653 be necessary even when we schedule the prologue and epilogue. */
3654 if (regs_ever_live [2] || current_function_calls_eh_return)
3655 {
3656 ret_off = TARGET_64BIT ? -16 : -20;
3657 if (frame_pointer_needed)
3658 {
3659 load_reg (2, ret_off, FRAME_POINTER_REGNUM);
3660 ret_off = 0;
3661 }
3662 else
3663 {
3664 /* No frame pointer, and stack is smaller than 8k. */
3665 if (VAL_14_BITS_P (ret_off - actual_fsize))
3666 {
3667 load_reg (2, ret_off - actual_fsize, STACK_POINTER_REGNUM);
3668 ret_off = 0;
3669 }
3670 }
3671 }
3672
3673 /* General register restores. */
3674 if (frame_pointer_needed)
3675 {
3676 offset = local_fsize;
3677
3678 /* If the current function calls __builtin_eh_return, then we need
3679 to restore the saved EH data registers. */
3680 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3681 {
3682 unsigned int i, regno;
3683
3684 for (i = 0; ; ++i)
3685 {
3686 regno = EH_RETURN_DATA_REGNO (i);
3687 if (regno == INVALID_REGNUM)
3688 break;
3689
3690 load_reg (regno, offset, FRAME_POINTER_REGNUM);
3691 offset += UNITS_PER_WORD;
3692 }
3693 }
3694
3695 for (i = 18; i >= 4; i--)
3696 if (regs_ever_live[i] && ! call_used_regs[i])
3697 {
3698 load_reg (i, offset, FRAME_POINTER_REGNUM);
3699 offset += UNITS_PER_WORD;
3700 }
3701 }
3702 else
3703 {
3704 offset = local_fsize - actual_fsize;
3705
3706 /* If the current function calls __builtin_eh_return, then we need
3707 to restore the saved EH data registers. */
3708 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3709 {
3710 unsigned int i, regno;
3711
3712 for (i = 0; ; ++i)
3713 {
3714 regno = EH_RETURN_DATA_REGNO (i);
3715 if (regno == INVALID_REGNUM)
3716 break;
3717
3718 /* Only for the first load.
3719 merge_sp_adjust_with_load holds the register load
3720 with which we will merge the sp adjustment. */
3721 if (merge_sp_adjust_with_load == 0
3722 && local_fsize == 0
3723 && VAL_14_BITS_P (-actual_fsize))
3724 merge_sp_adjust_with_load = regno;
3725 else
3726 load_reg (regno, offset, STACK_POINTER_REGNUM);
3727 offset += UNITS_PER_WORD;
3728 }
3729 }
3730
3731 for (i = 18; i >= 3; i--)
3732 {
3733 if (regs_ever_live[i] && ! call_used_regs[i])
3734 {
3735 /* Only for the first load.
3736 merge_sp_adjust_with_load holds the register load
3737 with which we will merge the sp adjustment. */
3738 if (merge_sp_adjust_with_load == 0
3739 && local_fsize == 0
3740 && VAL_14_BITS_P (-actual_fsize))
3741 merge_sp_adjust_with_load = i;
3742 else
3743 load_reg (i, offset, STACK_POINTER_REGNUM);
3744 offset += UNITS_PER_WORD;
3745 }
3746 }
3747 }
3748
3749 /* Align pointer properly (doubleword boundary). */
3750 offset = (offset + 7) & ~7;
3751
3752 /* FP register restores. */
3753 if (save_fregs)
3754 {
3755 /* Adjust the register to index off of. */
3756 if (frame_pointer_needed)
3757 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
3758 else
3759 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
3760
3761 /* Actually do the restores now. */
3762 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3763 if (regs_ever_live[i]
3764 || (! TARGET_64BIT && regs_ever_live[i + 1]))
3765 {
3766 rtx src = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
3767 rtx dest = gen_rtx_REG (DFmode, i);
3768 emit_move_insn (dest, src);
3769 }
3770 }
3771
3772 /* Emit a blockage insn here to keep these insns from being moved to
3773 an earlier spot in the epilogue, or into the main instruction stream.
3774
3775 This is necessary as we must not cut the stack back before all the
3776 restores are finished. */
3777 emit_insn (gen_blockage ());
3778
3779 /* Reset stack pointer (and possibly frame pointer). The stack
3780 pointer is initially set to fp + 64 to avoid a race condition. */
3781 if (frame_pointer_needed)
3782 {
3783 rtx delta = GEN_INT (-64);
3784
3785 set_reg_plus_d (STACK_POINTER_REGNUM, FRAME_POINTER_REGNUM, 64, 0);
3786 emit_insn (gen_pre_load (frame_pointer_rtx, stack_pointer_rtx, delta));
3787 }
3788 /* If we were deferring a callee register restore, do it now. */
3789 else if (merge_sp_adjust_with_load)
3790 {
3791 rtx delta = GEN_INT (-actual_fsize);
3792 rtx dest = gen_rtx_REG (word_mode, merge_sp_adjust_with_load);
3793
3794 emit_insn (gen_pre_load (dest, stack_pointer_rtx, delta));
3795 }
3796 else if (actual_fsize != 0)
3797 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3798 - actual_fsize, 0);
3799
3800 /* If we haven't restored %r2 yet (no frame pointer, and a stack
3801 frame greater than 8k), do so now. */
3802 if (ret_off != 0)
3803 load_reg (2, ret_off, STACK_POINTER_REGNUM);
3804
3805 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3806 {
3807 rtx sa = EH_RETURN_STACKADJ_RTX;
3808
3809 emit_insn (gen_blockage ());
3810 emit_insn (TARGET_64BIT
3811 ? gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, sa)
3812 : gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, sa));
3813 }
3814 }
3815
3816 rtx
hppa_pic_save_rtx()3817 hppa_pic_save_rtx ()
3818 {
3819 return get_hard_reg_initial_val (word_mode, PIC_OFFSET_TABLE_REGNUM);
3820 }
3821
3822 void
hppa_profile_hook(label_no)3823 hppa_profile_hook (label_no)
3824 int label_no;
3825 {
3826 rtx begin_label_rtx, call_insn;
3827 char begin_label_name[16];
3828
3829 ASM_GENERATE_INTERNAL_LABEL (begin_label_name, FUNC_BEGIN_PROLOG_LABEL,
3830 label_no);
3831 begin_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (begin_label_name));
3832
3833 if (TARGET_64BIT)
3834 emit_move_insn (arg_pointer_rtx,
3835 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
3836 GEN_INT (64)));
3837
3838 emit_move_insn (gen_rtx_REG (word_mode, 26), gen_rtx_REG (word_mode, 2));
3839
3840 #ifndef NO_PROFILE_COUNTERS
3841 {
3842 rtx count_label_rtx, addr, r24;
3843 char count_label_name[16];
3844
3845 ASM_GENERATE_INTERNAL_LABEL (count_label_name, "LP", label_no);
3846 count_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (count_label_name));
3847
3848 addr = force_reg (Pmode, count_label_rtx);
3849 r24 = gen_rtx_REG (Pmode, 24);
3850 emit_move_insn (r24, addr);
3851
3852 /* %r25 is set from within the output pattern. */
3853 call_insn =
3854 emit_call_insn (gen_call_profiler (gen_rtx_SYMBOL_REF (Pmode, "_mcount"),
3855 GEN_INT (TARGET_64BIT ? 24 : 12),
3856 begin_label_rtx));
3857
3858 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), r24);
3859 }
3860 #else
3861 /* %r25 is set from within the output pattern. */
3862 call_insn =
3863 emit_call_insn (gen_call_profiler (gen_rtx_SYMBOL_REF (Pmode, "_mcount"),
3864 GEN_INT (TARGET_64BIT ? 16 : 8),
3865 begin_label_rtx));
3866 #endif
3867
3868 /* Indicate the _mcount call cannot throw, nor will it execute a
3869 non-local goto. */
3870 REG_NOTES (call_insn)
3871 = gen_rtx_EXPR_LIST (REG_EH_REGION, constm1_rtx, REG_NOTES (call_insn));
3872
3873 if (flag_pic)
3874 {
3875 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
3876 if (TARGET_64BIT)
3877 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
3878
3879 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
3880 }
3881 }
3882
3883 /* Fetch the return address for the frame COUNT steps up from
3884 the current frame, after the prologue. FRAMEADDR is the
3885 frame pointer of the COUNT frame.
3886
3887 We want to ignore any export stub remnants here. To handle this,
3888 we examine the code at the return address, and if it is an export
3889 stub, we return a memory rtx for the stub return address stored
3890 at frame-24.
3891
3892 The value returned is used in two different ways:
3893
3894 1. To find a function's caller.
3895
3896 2. To change the return address for a function.
3897
3898 This function handles most instances of case 1; however, it will
3899 fail if there are two levels of stubs to execute on the return
3900 path. The only way I believe that can happen is if the return value
3901 needs a parameter relocation, which never happens for C code.
3902
3903 This function handles most instances of case 2; however, it will
3904 fail if we did not originally have stub code on the return path
3905 but will need stub code on the new return path. This can happen if
3906 the caller & callee are both in the main program, but the new
3907 return location is in a shared library. */
3908
3909 rtx
return_addr_rtx(count,frameaddr)3910 return_addr_rtx (count, frameaddr)
3911 int count;
3912 rtx frameaddr;
3913 {
3914 rtx label;
3915 rtx rp;
3916 rtx saved_rp;
3917 rtx ins;
3918
3919 if (count != 0)
3920 return NULL_RTX;
3921
3922 rp = get_hard_reg_initial_val (Pmode, 2);
3923
3924 if (TARGET_64BIT || TARGET_NO_SPACE_REGS)
3925 return rp;
3926
3927 saved_rp = gen_reg_rtx (Pmode);
3928 emit_move_insn (saved_rp, rp);
3929
3930 /* Get pointer to the instruction stream. We have to mask out the
3931 privilege level from the two low order bits of the return address
3932 pointer here so that ins will point to the start of the first
3933 instruction that would have been executed if we returned. */
3934 ins = copy_to_reg (gen_rtx_AND (Pmode, rp, MASK_RETURN_ADDR));
3935 label = gen_label_rtx ();
3936
3937 /* Check the instruction stream at the normal return address for the
3938 export stub:
3939
3940 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp
3941 0x004010a1 | stub+12: ldsid (sr0,rp),r1
3942 0x00011820 | stub+16: mtsp r1,sr0
3943 0xe0400002 | stub+20: be,n 0(sr0,rp)
3944
3945 If it is an export stub, than our return address is really in
3946 -24[frameaddr]. */
3947
3948 emit_cmp_insn (gen_rtx_MEM (SImode, ins), GEN_INT (0x4bc23fd1), NE,
3949 NULL_RTX, SImode, 1);
3950 emit_jump_insn (gen_bne (label));
3951
3952 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 4)),
3953 GEN_INT (0x004010a1), NE, NULL_RTX, SImode, 1);
3954 emit_jump_insn (gen_bne (label));
3955
3956 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 8)),
3957 GEN_INT (0x00011820), NE, NULL_RTX, SImode, 1);
3958 emit_jump_insn (gen_bne (label));
3959
3960 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 12)),
3961 GEN_INT (0xe0400002), NE, NULL_RTX, SImode, 1);
3962
3963 /* If there is no export stub then just use the value saved from
3964 the return pointer register. */
3965
3966 emit_jump_insn (gen_bne (label));
3967
3968 /* Here we know that our return address points to an export
3969 stub. We don't want to return the address of the export stub,
3970 but rather the return address of the export stub. That return
3971 address is stored at -24[frameaddr]. */
3972
3973 emit_move_insn (saved_rp,
3974 gen_rtx_MEM (Pmode,
3975 memory_address (Pmode,
3976 plus_constant (frameaddr,
3977 -24))));
3978
3979 emit_label (label);
3980 return saved_rp;
3981 }
3982
3983 /* This is only valid once reload has completed because it depends on
3984 knowing exactly how much (if any) frame there is and...
3985
3986 It's only valid if there is no frame marker to de-allocate and...
3987
3988 It's only valid if %r2 hasn't been saved into the caller's frame
3989 (we're not profiling and %r2 isn't live anywhere). */
3990 int
hppa_can_use_return_insn_p()3991 hppa_can_use_return_insn_p ()
3992 {
3993 return (reload_completed
3994 && (compute_frame_size (get_frame_size (), 0) ? 0 : 1)
3995 && ! regs_ever_live[2]
3996 && ! frame_pointer_needed);
3997 }
3998
3999 void
emit_bcond_fp(code,operand0)4000 emit_bcond_fp (code, operand0)
4001 enum rtx_code code;
4002 rtx operand0;
4003 {
4004 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
4005 gen_rtx_IF_THEN_ELSE (VOIDmode,
4006 gen_rtx_fmt_ee (code,
4007 VOIDmode,
4008 gen_rtx_REG (CCFPmode, 0),
4009 const0_rtx),
4010 gen_rtx_LABEL_REF (VOIDmode, operand0),
4011 pc_rtx)));
4012
4013 }
4014
4015 rtx
gen_cmp_fp(code,operand0,operand1)4016 gen_cmp_fp (code, operand0, operand1)
4017 enum rtx_code code;
4018 rtx operand0, operand1;
4019 {
4020 return gen_rtx_SET (VOIDmode, gen_rtx_REG (CCFPmode, 0),
4021 gen_rtx_fmt_ee (code, CCFPmode, operand0, operand1));
4022 }
4023
4024 /* Adjust the cost of a scheduling dependency. Return the new cost of
4025 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
4026
4027 static int
pa_adjust_cost(insn,link,dep_insn,cost)4028 pa_adjust_cost (insn, link, dep_insn, cost)
4029 rtx insn;
4030 rtx link;
4031 rtx dep_insn;
4032 int cost;
4033 {
4034 enum attr_type attr_type;
4035
4036 /* Don't adjust costs for a pa8000 chip, also do not adjust any
4037 true dependencies as they are described with bypasses now. */
4038 if (pa_cpu >= PROCESSOR_8000 || REG_NOTE_KIND (link) == 0)
4039 return cost;
4040
4041 if (! recog_memoized (insn))
4042 return 0;
4043
4044 attr_type = get_attr_type (insn);
4045
4046 if (REG_NOTE_KIND (link) == REG_DEP_ANTI)
4047 {
4048 /* Anti dependency; DEP_INSN reads a register that INSN writes some
4049 cycles later. */
4050
4051 if (attr_type == TYPE_FPLOAD)
4052 {
4053 rtx pat = PATTERN (insn);
4054 rtx dep_pat = PATTERN (dep_insn);
4055 if (GET_CODE (pat) == PARALLEL)
4056 {
4057 /* This happens for the fldXs,mb patterns. */
4058 pat = XVECEXP (pat, 0, 0);
4059 }
4060 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4061 /* If this happens, we have to extend this to schedule
4062 optimally. Return 0 for now. */
4063 return 0;
4064
4065 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4066 {
4067 if (! recog_memoized (dep_insn))
4068 return 0;
4069 switch (get_attr_type (dep_insn))
4070 {
4071 case TYPE_FPALU:
4072 case TYPE_FPMULSGL:
4073 case TYPE_FPMULDBL:
4074 case TYPE_FPDIVSGL:
4075 case TYPE_FPDIVDBL:
4076 case TYPE_FPSQRTSGL:
4077 case TYPE_FPSQRTDBL:
4078 /* A fpload can't be issued until one cycle before a
4079 preceding arithmetic operation has finished if
4080 the target of the fpload is any of the sources
4081 (or destination) of the arithmetic operation. */
4082 return insn_default_latency (dep_insn) - 1;
4083
4084 default:
4085 return 0;
4086 }
4087 }
4088 }
4089 else if (attr_type == TYPE_FPALU)
4090 {
4091 rtx pat = PATTERN (insn);
4092 rtx dep_pat = PATTERN (dep_insn);
4093 if (GET_CODE (pat) == PARALLEL)
4094 {
4095 /* This happens for the fldXs,mb patterns. */
4096 pat = XVECEXP (pat, 0, 0);
4097 }
4098 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4099 /* If this happens, we have to extend this to schedule
4100 optimally. Return 0 for now. */
4101 return 0;
4102
4103 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4104 {
4105 if (! recog_memoized (dep_insn))
4106 return 0;
4107 switch (get_attr_type (dep_insn))
4108 {
4109 case TYPE_FPDIVSGL:
4110 case TYPE_FPDIVDBL:
4111 case TYPE_FPSQRTSGL:
4112 case TYPE_FPSQRTDBL:
4113 /* An ALU flop can't be issued until two cycles before a
4114 preceding divide or sqrt operation has finished if
4115 the target of the ALU flop is any of the sources
4116 (or destination) of the divide or sqrt operation. */
4117 return insn_default_latency (dep_insn) - 2;
4118
4119 default:
4120 return 0;
4121 }
4122 }
4123 }
4124
4125 /* For other anti dependencies, the cost is 0. */
4126 return 0;
4127 }
4128 else if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
4129 {
4130 /* Output dependency; DEP_INSN writes a register that INSN writes some
4131 cycles later. */
4132 if (attr_type == TYPE_FPLOAD)
4133 {
4134 rtx pat = PATTERN (insn);
4135 rtx dep_pat = PATTERN (dep_insn);
4136 if (GET_CODE (pat) == PARALLEL)
4137 {
4138 /* This happens for the fldXs,mb patterns. */
4139 pat = XVECEXP (pat, 0, 0);
4140 }
4141 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4142 /* If this happens, we have to extend this to schedule
4143 optimally. Return 0 for now. */
4144 return 0;
4145
4146 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4147 {
4148 if (! recog_memoized (dep_insn))
4149 return 0;
4150 switch (get_attr_type (dep_insn))
4151 {
4152 case TYPE_FPALU:
4153 case TYPE_FPMULSGL:
4154 case TYPE_FPMULDBL:
4155 case TYPE_FPDIVSGL:
4156 case TYPE_FPDIVDBL:
4157 case TYPE_FPSQRTSGL:
4158 case TYPE_FPSQRTDBL:
4159 /* A fpload can't be issued until one cycle before a
4160 preceding arithmetic operation has finished if
4161 the target of the fpload is the destination of the
4162 arithmetic operation.
4163
4164 Exception: For PA7100LC, PA7200 and PA7300, the cost
4165 is 3 cycles, unless they bundle together. We also
4166 pay the penalty if the second insn is a fpload. */
4167 return insn_default_latency (dep_insn) - 1;
4168
4169 default:
4170 return 0;
4171 }
4172 }
4173 }
4174 else if (attr_type == TYPE_FPALU)
4175 {
4176 rtx pat = PATTERN (insn);
4177 rtx dep_pat = PATTERN (dep_insn);
4178 if (GET_CODE (pat) == PARALLEL)
4179 {
4180 /* This happens for the fldXs,mb patterns. */
4181 pat = XVECEXP (pat, 0, 0);
4182 }
4183 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4184 /* If this happens, we have to extend this to schedule
4185 optimally. Return 0 for now. */
4186 return 0;
4187
4188 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4189 {
4190 if (! recog_memoized (dep_insn))
4191 return 0;
4192 switch (get_attr_type (dep_insn))
4193 {
4194 case TYPE_FPDIVSGL:
4195 case TYPE_FPDIVDBL:
4196 case TYPE_FPSQRTSGL:
4197 case TYPE_FPSQRTDBL:
4198 /* An ALU flop can't be issued until two cycles before a
4199 preceding divide or sqrt operation has finished if
4200 the target of the ALU flop is also the target of
4201 the divide or sqrt operation. */
4202 return insn_default_latency (dep_insn) - 2;
4203
4204 default:
4205 return 0;
4206 }
4207 }
4208 }
4209
4210 /* For other output dependencies, the cost is 0. */
4211 return 0;
4212 }
4213 else
4214 abort ();
4215 }
4216
4217 /* Adjust scheduling priorities. We use this to try and keep addil
4218 and the next use of %r1 close together. */
4219 static int
pa_adjust_priority(insn,priority)4220 pa_adjust_priority (insn, priority)
4221 rtx insn;
4222 int priority;
4223 {
4224 rtx set = single_set (insn);
4225 rtx src, dest;
4226 if (set)
4227 {
4228 src = SET_SRC (set);
4229 dest = SET_DEST (set);
4230 if (GET_CODE (src) == LO_SUM
4231 && symbolic_operand (XEXP (src, 1), VOIDmode)
4232 && ! read_only_operand (XEXP (src, 1), VOIDmode))
4233 priority >>= 3;
4234
4235 else if (GET_CODE (src) == MEM
4236 && GET_CODE (XEXP (src, 0)) == LO_SUM
4237 && symbolic_operand (XEXP (XEXP (src, 0), 1), VOIDmode)
4238 && ! read_only_operand (XEXP (XEXP (src, 0), 1), VOIDmode))
4239 priority >>= 1;
4240
4241 else if (GET_CODE (dest) == MEM
4242 && GET_CODE (XEXP (dest, 0)) == LO_SUM
4243 && symbolic_operand (XEXP (XEXP (dest, 0), 1), VOIDmode)
4244 && ! read_only_operand (XEXP (XEXP (dest, 0), 1), VOIDmode))
4245 priority >>= 3;
4246 }
4247 return priority;
4248 }
4249
4250 /* The 700 can only issue a single insn at a time.
4251 The 7XXX processors can issue two insns at a time.
4252 The 8000 can issue 4 insns at a time. */
4253 static int
pa_issue_rate()4254 pa_issue_rate ()
4255 {
4256 switch (pa_cpu)
4257 {
4258 case PROCESSOR_700: return 1;
4259 case PROCESSOR_7100: return 2;
4260 case PROCESSOR_7100LC: return 2;
4261 case PROCESSOR_7200: return 2;
4262 case PROCESSOR_7300: return 2;
4263 case PROCESSOR_8000: return 4;
4264
4265 default:
4266 abort ();
4267 }
4268 }
4269
4270
4271
4272 /* Return any length adjustment needed by INSN which already has its length
4273 computed as LENGTH. Return zero if no adjustment is necessary.
4274
4275 For the PA: function calls, millicode calls, and backwards short
4276 conditional branches with unfilled delay slots need an adjustment by +1
4277 (to account for the NOP which will be inserted into the instruction stream).
4278
4279 Also compute the length of an inline block move here as it is too
4280 complicated to express as a length attribute in pa.md. */
4281 int
pa_adjust_insn_length(insn,length)4282 pa_adjust_insn_length (insn, length)
4283 rtx insn;
4284 int length;
4285 {
4286 rtx pat = PATTERN (insn);
4287
4288 /* Call insns which are *not* indirect and have unfilled delay slots. */
4289 if (GET_CODE (insn) == CALL_INSN)
4290 {
4291
4292 if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL
4293 && GET_CODE (XEXP (XEXP (XVECEXP (pat, 0, 0), 0), 0)) == SYMBOL_REF)
4294 return 4;
4295 else if (GET_CODE (XVECEXP (pat, 0, 0)) == SET
4296 && GET_CODE (XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0))
4297 == SYMBOL_REF)
4298 return 4;
4299 else
4300 return 0;
4301 }
4302 /* Jumps inside switch tables which have unfilled delay slots
4303 also need adjustment. */
4304 else if (GET_CODE (insn) == JUMP_INSN
4305 && simplejump_p (insn)
4306 && GET_MODE (insn) == SImode)
4307 return 4;
4308 /* Millicode insn with an unfilled delay slot. */
4309 else if (GET_CODE (insn) == INSN
4310 && GET_CODE (pat) != SEQUENCE
4311 && GET_CODE (pat) != USE
4312 && GET_CODE (pat) != CLOBBER
4313 && get_attr_type (insn) == TYPE_MILLI)
4314 return 4;
4315 /* Block move pattern. */
4316 else if (GET_CODE (insn) == INSN
4317 && GET_CODE (pat) == PARALLEL
4318 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
4319 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
4320 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM
4321 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode
4322 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode)
4323 return compute_movstrsi_length (insn) - 4;
4324 /* Conditional branch with an unfilled delay slot. */
4325 else if (GET_CODE (insn) == JUMP_INSN && ! simplejump_p (insn))
4326 {
4327 /* Adjust a short backwards conditional with an unfilled delay slot. */
4328 if (GET_CODE (pat) == SET
4329 && length == 4
4330 && ! forward_branch_p (insn))
4331 return 4;
4332 else if (GET_CODE (pat) == PARALLEL
4333 && get_attr_type (insn) == TYPE_PARALLEL_BRANCH
4334 && length == 4)
4335 return 4;
4336 /* Adjust dbra insn with short backwards conditional branch with
4337 unfilled delay slot -- only for case where counter is in a
4338 general register register. */
4339 else if (GET_CODE (pat) == PARALLEL
4340 && GET_CODE (XVECEXP (pat, 0, 1)) == SET
4341 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG
4342 && ! FP_REG_P (XEXP (XVECEXP (pat, 0, 1), 0))
4343 && length == 4
4344 && ! forward_branch_p (insn))
4345 return 4;
4346 else
4347 return 0;
4348 }
4349 return 0;
4350 }
4351
4352 /* Print operand X (an rtx) in assembler syntax to file FILE.
4353 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
4354 For `%' followed by punctuation, CODE is the punctuation and X is null. */
4355
4356 void
print_operand(file,x,code)4357 print_operand (file, x, code)
4358 FILE *file;
4359 rtx x;
4360 int code;
4361 {
4362 switch (code)
4363 {
4364 case '#':
4365 /* Output a 'nop' if there's nothing for the delay slot. */
4366 if (dbr_sequence_length () == 0)
4367 fputs ("\n\tnop", file);
4368 return;
4369 case '*':
4370 /* Output an nullification completer if there's nothing for the */
4371 /* delay slot or nullification is requested. */
4372 if (dbr_sequence_length () == 0 ||
4373 (final_sequence &&
4374 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))))
4375 fputs (",n", file);
4376 return;
4377 case 'R':
4378 /* Print out the second register name of a register pair.
4379 I.e., R (6) => 7. */
4380 fputs (reg_names[REGNO (x) + 1], file);
4381 return;
4382 case 'r':
4383 /* A register or zero. */
4384 if (x == const0_rtx
4385 || (x == CONST0_RTX (DFmode))
4386 || (x == CONST0_RTX (SFmode)))
4387 {
4388 fputs ("%r0", file);
4389 return;
4390 }
4391 else
4392 break;
4393 case 'f':
4394 /* A register or zero (floating point). */
4395 if (x == const0_rtx
4396 || (x == CONST0_RTX (DFmode))
4397 || (x == CONST0_RTX (SFmode)))
4398 {
4399 fputs ("%fr0", file);
4400 return;
4401 }
4402 else
4403 break;
4404 case 'A':
4405 {
4406 rtx xoperands[2];
4407
4408 xoperands[0] = XEXP (XEXP (x, 0), 0);
4409 xoperands[1] = XVECEXP (XEXP (XEXP (x, 0), 1), 0, 0);
4410 output_global_address (file, xoperands[1], 0);
4411 fprintf (file, "(%s)", reg_names [REGNO (xoperands[0])]);
4412 return;
4413 }
4414
4415 case 'C': /* Plain (C)ondition */
4416 case 'X':
4417 switch (GET_CODE (x))
4418 {
4419 case EQ:
4420 fputs ("=", file); break;
4421 case NE:
4422 fputs ("<>", file); break;
4423 case GT:
4424 fputs (">", file); break;
4425 case GE:
4426 fputs (">=", file); break;
4427 case GEU:
4428 fputs (">>=", file); break;
4429 case GTU:
4430 fputs (">>", file); break;
4431 case LT:
4432 fputs ("<", file); break;
4433 case LE:
4434 fputs ("<=", file); break;
4435 case LEU:
4436 fputs ("<<=", file); break;
4437 case LTU:
4438 fputs ("<<", file); break;
4439 default:
4440 abort ();
4441 }
4442 return;
4443 case 'N': /* Condition, (N)egated */
4444 switch (GET_CODE (x))
4445 {
4446 case EQ:
4447 fputs ("<>", file); break;
4448 case NE:
4449 fputs ("=", file); break;
4450 case GT:
4451 fputs ("<=", file); break;
4452 case GE:
4453 fputs ("<", file); break;
4454 case GEU:
4455 fputs ("<<", file); break;
4456 case GTU:
4457 fputs ("<<=", file); break;
4458 case LT:
4459 fputs (">=", file); break;
4460 case LE:
4461 fputs (">", file); break;
4462 case LEU:
4463 fputs (">>", file); break;
4464 case LTU:
4465 fputs (">>=", file); break;
4466 default:
4467 abort ();
4468 }
4469 return;
4470 /* For floating point comparisons. Note that the output
4471 predicates are the complement of the desired mode. */
4472 case 'Y':
4473 switch (GET_CODE (x))
4474 {
4475 case EQ:
4476 fputs ("!=", file); break;
4477 case NE:
4478 fputs ("=", file); break;
4479 case GT:
4480 fputs ("!>", file); break;
4481 case GE:
4482 fputs ("!>=", file); break;
4483 case LT:
4484 fputs ("!<", file); break;
4485 case LE:
4486 fputs ("!<=", file); break;
4487 case LTGT:
4488 fputs ("!<>", file); break;
4489 case UNLE:
4490 fputs (">", file); break;
4491 case UNLT:
4492 fputs (">=", file); break;
4493 case UNGE:
4494 fputs ("<", file); break;
4495 case UNGT:
4496 fputs ("<=", file); break;
4497 case UNEQ:
4498 fputs ("<>", file); break;
4499 case UNORDERED:
4500 fputs ("<=>", file); break;
4501 case ORDERED:
4502 fputs ("!<=>", file); break;
4503 default:
4504 abort ();
4505 }
4506 return;
4507 case 'S': /* Condition, operands are (S)wapped. */
4508 switch (GET_CODE (x))
4509 {
4510 case EQ:
4511 fputs ("=", file); break;
4512 case NE:
4513 fputs ("<>", file); break;
4514 case GT:
4515 fputs ("<", file); break;
4516 case GE:
4517 fputs ("<=", file); break;
4518 case GEU:
4519 fputs ("<<=", file); break;
4520 case GTU:
4521 fputs ("<<", file); break;
4522 case LT:
4523 fputs (">", file); break;
4524 case LE:
4525 fputs (">=", file); break;
4526 case LEU:
4527 fputs (">>=", file); break;
4528 case LTU:
4529 fputs (">>", file); break;
4530 default:
4531 abort ();
4532 }
4533 return;
4534 case 'B': /* Condition, (B)oth swapped and negate. */
4535 switch (GET_CODE (x))
4536 {
4537 case EQ:
4538 fputs ("<>", file); break;
4539 case NE:
4540 fputs ("=", file); break;
4541 case GT:
4542 fputs (">=", file); break;
4543 case GE:
4544 fputs (">", file); break;
4545 case GEU:
4546 fputs (">>", file); break;
4547 case GTU:
4548 fputs (">>=", file); break;
4549 case LT:
4550 fputs ("<=", file); break;
4551 case LE:
4552 fputs ("<", file); break;
4553 case LEU:
4554 fputs ("<<", file); break;
4555 case LTU:
4556 fputs ("<<=", file); break;
4557 default:
4558 abort ();
4559 }
4560 return;
4561 case 'k':
4562 if (GET_CODE (x) == CONST_INT)
4563 {
4564 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~INTVAL (x));
4565 return;
4566 }
4567 abort ();
4568 case 'Q':
4569 if (GET_CODE (x) == CONST_INT)
4570 {
4571 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - (INTVAL (x) & 63));
4572 return;
4573 }
4574 abort ();
4575 case 'L':
4576 if (GET_CODE (x) == CONST_INT)
4577 {
4578 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - (INTVAL (x) & 31));
4579 return;
4580 }
4581 abort ();
4582 case 'O':
4583 if (GET_CODE (x) == CONST_INT && exact_log2 (INTVAL (x)) >= 0)
4584 {
4585 fprintf (file, "%d", exact_log2 (INTVAL (x)));
4586 return;
4587 }
4588 abort ();
4589 case 'p':
4590 if (GET_CODE (x) == CONST_INT)
4591 {
4592 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 63 - (INTVAL (x) & 63));
4593 return;
4594 }
4595 abort ();
4596 case 'P':
4597 if (GET_CODE (x) == CONST_INT)
4598 {
4599 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 31 - (INTVAL (x) & 31));
4600 return;
4601 }
4602 abort ();
4603 case 'I':
4604 if (GET_CODE (x) == CONST_INT)
4605 fputs ("i", file);
4606 return;
4607 case 'M':
4608 case 'F':
4609 switch (GET_CODE (XEXP (x, 0)))
4610 {
4611 case PRE_DEC:
4612 case PRE_INC:
4613 if (ASSEMBLER_DIALECT == 0)
4614 fputs ("s,mb", file);
4615 else
4616 fputs (",mb", file);
4617 break;
4618 case POST_DEC:
4619 case POST_INC:
4620 if (ASSEMBLER_DIALECT == 0)
4621 fputs ("s,ma", file);
4622 else
4623 fputs (",ma", file);
4624 break;
4625 case PLUS:
4626 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
4627 || GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
4628 {
4629 if (ASSEMBLER_DIALECT == 0)
4630 fputs ("x,s", file);
4631 else
4632 fputs (",s", file);
4633 }
4634 else if (code == 'F' && ASSEMBLER_DIALECT == 0)
4635 fputs ("s", file);
4636 break;
4637 default:
4638 if (code == 'F' && ASSEMBLER_DIALECT == 0)
4639 fputs ("s", file);
4640 break;
4641 }
4642 return;
4643 case 'G':
4644 output_global_address (file, x, 0);
4645 return;
4646 case 'H':
4647 output_global_address (file, x, 1);
4648 return;
4649 case 0: /* Don't do anything special */
4650 break;
4651 case 'Z':
4652 {
4653 unsigned op[3];
4654 compute_zdepwi_operands (INTVAL (x), op);
4655 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
4656 return;
4657 }
4658 case 'z':
4659 {
4660 unsigned op[3];
4661 compute_zdepdi_operands (INTVAL (x), op);
4662 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
4663 return;
4664 }
4665 case 'c':
4666 /* We can get here from a .vtable_inherit due to our
4667 CONSTANT_ADDRESS_P rejecting perfectly good constant
4668 addresses. */
4669 break;
4670 default:
4671 abort ();
4672 }
4673 if (GET_CODE (x) == REG)
4674 {
4675 fputs (reg_names [REGNO (x)], file);
4676 if (TARGET_64BIT && FP_REG_P (x) && GET_MODE_SIZE (GET_MODE (x)) <= 4)
4677 {
4678 fputs ("R", file);
4679 return;
4680 }
4681 if (FP_REG_P (x)
4682 && GET_MODE_SIZE (GET_MODE (x)) <= 4
4683 && (REGNO (x) & 1) == 0)
4684 fputs ("L", file);
4685 }
4686 else if (GET_CODE (x) == MEM)
4687 {
4688 int size = GET_MODE_SIZE (GET_MODE (x));
4689 rtx base = NULL_RTX;
4690 switch (GET_CODE (XEXP (x, 0)))
4691 {
4692 case PRE_DEC:
4693 case POST_DEC:
4694 base = XEXP (XEXP (x, 0), 0);
4695 fprintf (file, "-%d(%s)", size, reg_names [REGNO (base)]);
4696 break;
4697 case PRE_INC:
4698 case POST_INC:
4699 base = XEXP (XEXP (x, 0), 0);
4700 fprintf (file, "%d(%s)", size, reg_names [REGNO (base)]);
4701 break;
4702 default:
4703 if (GET_CODE (XEXP (x, 0)) == PLUS
4704 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT)
4705 fprintf (file, "%s(%s)",
4706 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0))],
4707 reg_names [REGNO (XEXP (XEXP (x, 0), 1))]);
4708 else if (GET_CODE (XEXP (x, 0)) == PLUS
4709 && GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
4710 fprintf (file, "%s(%s)",
4711 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))],
4712 reg_names [REGNO (XEXP (XEXP (x, 0), 0))]);
4713 else
4714 output_address (XEXP (x, 0));
4715 break;
4716 }
4717 }
4718 else
4719 output_addr_const (file, x);
4720 }
4721
4722 /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */
4723
4724 void
output_global_address(file,x,round_constant)4725 output_global_address (file, x, round_constant)
4726 FILE *file;
4727 rtx x;
4728 int round_constant;
4729 {
4730
4731 /* Imagine (high (const (plus ...))). */
4732 if (GET_CODE (x) == HIGH)
4733 x = XEXP (x, 0);
4734
4735 if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x, VOIDmode))
4736 assemble_name (file, XSTR (x, 0));
4737 else if (GET_CODE (x) == SYMBOL_REF && !flag_pic)
4738 {
4739 assemble_name (file, XSTR (x, 0));
4740 fputs ("-$global$", file);
4741 }
4742 else if (GET_CODE (x) == CONST)
4743 {
4744 const char *sep = "";
4745 int offset = 0; /* assembler wants -$global$ at end */
4746 rtx base = NULL_RTX;
4747
4748 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)
4749 {
4750 base = XEXP (XEXP (x, 0), 0);
4751 output_addr_const (file, base);
4752 }
4753 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == CONST_INT)
4754 offset = INTVAL (XEXP (XEXP (x, 0), 0));
4755 else abort ();
4756
4757 if (GET_CODE (XEXP (XEXP (x, 0), 1)) == SYMBOL_REF)
4758 {
4759 base = XEXP (XEXP (x, 0), 1);
4760 output_addr_const (file, base);
4761 }
4762 else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
4763 offset = INTVAL (XEXP (XEXP (x, 0), 1));
4764 else abort ();
4765
4766 /* How bogus. The compiler is apparently responsible for
4767 rounding the constant if it uses an LR field selector.
4768
4769 The linker and/or assembler seem a better place since
4770 they have to do this kind of thing already.
4771
4772 If we fail to do this, HP's optimizing linker may eliminate
4773 an addil, but not update the ldw/stw/ldo instruction that
4774 uses the result of the addil. */
4775 if (round_constant)
4776 offset = ((offset + 0x1000) & ~0x1fff);
4777
4778 if (GET_CODE (XEXP (x, 0)) == PLUS)
4779 {
4780 if (offset < 0)
4781 {
4782 offset = -offset;
4783 sep = "-";
4784 }
4785 else
4786 sep = "+";
4787 }
4788 else if (GET_CODE (XEXP (x, 0)) == MINUS
4789 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF))
4790 sep = "-";
4791 else abort ();
4792
4793 if (!read_only_operand (base, VOIDmode) && !flag_pic)
4794 fputs ("-$global$", file);
4795 if (offset)
4796 fprintf (file, "%s%d", sep, offset);
4797 }
4798 else
4799 output_addr_const (file, x);
4800 }
4801
4802 static struct deferred_plabel *
get_plabel(fname)4803 get_plabel (fname)
4804 const char *fname;
4805 {
4806 size_t i;
4807
4808 /* See if we have already put this function on the list of deferred
4809 plabels. This list is generally small, so a liner search is not
4810 too ugly. If it proves too slow replace it with something faster. */
4811 for (i = 0; i < n_deferred_plabels; i++)
4812 if (strcmp (fname, deferred_plabels[i].name) == 0)
4813 break;
4814
4815 /* If the deferred plabel list is empty, or this entry was not found
4816 on the list, create a new entry on the list. */
4817 if (deferred_plabels == NULL || i == n_deferred_plabels)
4818 {
4819 const char *real_name;
4820
4821 if (deferred_plabels == 0)
4822 deferred_plabels = (struct deferred_plabel *)
4823 ggc_alloc (sizeof (struct deferred_plabel));
4824 else
4825 deferred_plabels = (struct deferred_plabel *)
4826 ggc_realloc (deferred_plabels,
4827 ((n_deferred_plabels + 1)
4828 * sizeof (struct deferred_plabel)));
4829
4830 i = n_deferred_plabels++;
4831 deferred_plabels[i].internal_label = gen_label_rtx ();
4832 deferred_plabels[i].name = ggc_strdup (fname);
4833
4834 /* Gross. We have just implicitly taken the address of this function,
4835 mark it as such. */
4836 real_name = (*targetm.strip_name_encoding) (fname);
4837 TREE_SYMBOL_REFERENCED (get_identifier (real_name)) = 1;
4838 }
4839
4840 return &deferred_plabels[i];
4841 }
4842
4843 void
output_deferred_plabels(file)4844 output_deferred_plabels (file)
4845 FILE *file;
4846 {
4847 size_t i;
4848 /* If we have deferred plabels, then we need to switch into the data
4849 section and align it to a 4 byte boundary before we output the
4850 deferred plabels. */
4851 if (n_deferred_plabels)
4852 {
4853 data_section ();
4854 ASM_OUTPUT_ALIGN (file, TARGET_64BIT ? 3 : 2);
4855 }
4856
4857 /* Now output the deferred plabels. */
4858 for (i = 0; i < n_deferred_plabels; i++)
4859 {
4860 rtx label = deferred_plabels[i].internal_label;
4861
4862 ASM_OUTPUT_INTERNAL_LABEL (file, "L", CODE_LABEL_NUMBER (label));
4863 assemble_integer (gen_rtx_SYMBOL_REF (Pmode, deferred_plabels[i].name),
4864 TARGET_64BIT ? 8 : 4, TARGET_64BIT ? 64 : 32, 1);
4865 }
4866 }
4867
4868 /* HP's millicode routines mean something special to the assembler.
4869 Keep track of which ones we have used. */
4870
4871 enum millicodes { remI, remU, divI, divU, mulI, end1000 };
4872 static void import_milli PARAMS ((enum millicodes));
4873 static char imported[(int) end1000];
4874 static const char * const milli_names[] = {"remI", "remU", "divI", "divU", "mulI"};
4875 static const char import_string[] = ".IMPORT $$....,MILLICODE";
4876 #define MILLI_START 10
4877
4878 static void
import_milli(code)4879 import_milli (code)
4880 enum millicodes code;
4881 {
4882 char str[sizeof (import_string)];
4883
4884 if (!imported[(int) code])
4885 {
4886 imported[(int) code] = 1;
4887 strcpy (str, import_string);
4888 strncpy (str + MILLI_START, milli_names[(int) code], 4);
4889 output_asm_insn (str, 0);
4890 }
4891 }
4892
4893 /* The register constraints have put the operands and return value in
4894 the proper registers. */
4895
4896 const char *
output_mul_insn(unsignedp,insn)4897 output_mul_insn (unsignedp, insn)
4898 int unsignedp ATTRIBUTE_UNUSED;
4899 rtx insn;
4900 {
4901 import_milli (mulI);
4902 return output_millicode_call (insn, gen_rtx_SYMBOL_REF (Pmode, "$$mulI"));
4903 }
4904
4905 /* Emit the rtl for doing a division by a constant. */
4906
4907 /* Do magic division millicodes exist for this value? */
4908 static const int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0,
4909 1, 1};
4910
4911 /* We'll use an array to keep track of the magic millicodes and
4912 whether or not we've used them already. [n][0] is signed, [n][1] is
4913 unsigned. */
4914
4915 static int div_milli[16][2];
4916
4917 int
div_operand(op,mode)4918 div_operand (op, mode)
4919 rtx op;
4920 enum machine_mode mode;
4921 {
4922 return (mode == SImode
4923 && ((GET_CODE (op) == REG && REGNO (op) == 25)
4924 || (GET_CODE (op) == CONST_INT && INTVAL (op) > 0
4925 && INTVAL (op) < 16 && magic_milli[INTVAL (op)])));
4926 }
4927
4928 int
emit_hpdiv_const(operands,unsignedp)4929 emit_hpdiv_const (operands, unsignedp)
4930 rtx *operands;
4931 int unsignedp;
4932 {
4933 if (GET_CODE (operands[2]) == CONST_INT
4934 && INTVAL (operands[2]) > 0
4935 && INTVAL (operands[2]) < 16
4936 && magic_milli[INTVAL (operands[2])])
4937 {
4938 rtx ret = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
4939
4940 emit_move_insn (gen_rtx_REG (SImode, 26), operands[1]);
4941 emit
4942 (gen_rtx
4943 (PARALLEL, VOIDmode,
4944 gen_rtvec (6, gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, 29),
4945 gen_rtx_fmt_ee (unsignedp ? UDIV : DIV,
4946 SImode,
4947 gen_rtx_REG (SImode, 26),
4948 operands[2])),
4949 gen_rtx_CLOBBER (VOIDmode, operands[4]),
4950 gen_rtx_CLOBBER (VOIDmode, operands[3]),
4951 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 26)),
4952 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 25)),
4953 gen_rtx_CLOBBER (VOIDmode, ret))));
4954 emit_move_insn (operands[0], gen_rtx_REG (SImode, 29));
4955 return 1;
4956 }
4957 return 0;
4958 }
4959
4960 const char *
output_div_insn(operands,unsignedp,insn)4961 output_div_insn (operands, unsignedp, insn)
4962 rtx *operands;
4963 int unsignedp;
4964 rtx insn;
4965 {
4966 int divisor;
4967
4968 /* If the divisor is a constant, try to use one of the special
4969 opcodes .*/
4970 if (GET_CODE (operands[0]) == CONST_INT)
4971 {
4972 static char buf[100];
4973 divisor = INTVAL (operands[0]);
4974 if (!div_milli[divisor][unsignedp])
4975 {
4976 div_milli[divisor][unsignedp] = 1;
4977 if (unsignedp)
4978 output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands);
4979 else
4980 output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands);
4981 }
4982 if (unsignedp)
4983 {
4984 sprintf (buf, "$$divU_");
4985 sprintf (buf + 7, HOST_WIDE_INT_PRINT_DEC, INTVAL (operands[0]));
4986 return output_millicode_call (insn,
4987 gen_rtx_SYMBOL_REF (SImode, buf));
4988 }
4989 else
4990 {
4991 sprintf (buf, "$$divI_");
4992 sprintf (buf + 7, HOST_WIDE_INT_PRINT_DEC, INTVAL (operands[0]));
4993 return output_millicode_call (insn,
4994 gen_rtx_SYMBOL_REF (SImode, buf));
4995 }
4996 }
4997 /* Divisor isn't a special constant. */
4998 else
4999 {
5000 if (unsignedp)
5001 {
5002 import_milli (divU);
5003 return output_millicode_call (insn,
5004 gen_rtx_SYMBOL_REF (SImode, "$$divU"));
5005 }
5006 else
5007 {
5008 import_milli (divI);
5009 return output_millicode_call (insn,
5010 gen_rtx_SYMBOL_REF (SImode, "$$divI"));
5011 }
5012 }
5013 }
5014
5015 /* Output a $$rem millicode to do mod. */
5016
5017 const char *
output_mod_insn(unsignedp,insn)5018 output_mod_insn (unsignedp, insn)
5019 int unsignedp;
5020 rtx insn;
5021 {
5022 if (unsignedp)
5023 {
5024 import_milli (remU);
5025 return output_millicode_call (insn,
5026 gen_rtx_SYMBOL_REF (SImode, "$$remU"));
5027 }
5028 else
5029 {
5030 import_milli (remI);
5031 return output_millicode_call (insn,
5032 gen_rtx_SYMBOL_REF (SImode, "$$remI"));
5033 }
5034 }
5035
5036 void
output_arg_descriptor(call_insn)5037 output_arg_descriptor (call_insn)
5038 rtx call_insn;
5039 {
5040 const char *arg_regs[4];
5041 enum machine_mode arg_mode;
5042 rtx link;
5043 int i, output_flag = 0;
5044 int regno;
5045
5046 /* We neither need nor want argument location descriptors for the
5047 64bit runtime environment or the ELF32 environment. */
5048 if (TARGET_64BIT || TARGET_ELF32)
5049 return;
5050
5051 for (i = 0; i < 4; i++)
5052 arg_regs[i] = 0;
5053
5054 /* Specify explicitly that no argument relocations should take place
5055 if using the portable runtime calling conventions. */
5056 if (TARGET_PORTABLE_RUNTIME)
5057 {
5058 fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n",
5059 asm_out_file);
5060 return;
5061 }
5062
5063 if (GET_CODE (call_insn) != CALL_INSN)
5064 abort ();
5065 for (link = CALL_INSN_FUNCTION_USAGE (call_insn); link; link = XEXP (link, 1))
5066 {
5067 rtx use = XEXP (link, 0);
5068
5069 if (! (GET_CODE (use) == USE
5070 && GET_CODE (XEXP (use, 0)) == REG
5071 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
5072 continue;
5073
5074 arg_mode = GET_MODE (XEXP (use, 0));
5075 regno = REGNO (XEXP (use, 0));
5076 if (regno >= 23 && regno <= 26)
5077 {
5078 arg_regs[26 - regno] = "GR";
5079 if (arg_mode == DImode)
5080 arg_regs[25 - regno] = "GR";
5081 }
5082 else if (regno >= 32 && regno <= 39)
5083 {
5084 if (arg_mode == SFmode)
5085 arg_regs[(regno - 32) / 2] = "FR";
5086 else
5087 {
5088 #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED
5089 arg_regs[(regno - 34) / 2] = "FR";
5090 arg_regs[(regno - 34) / 2 + 1] = "FU";
5091 #else
5092 arg_regs[(regno - 34) / 2] = "FU";
5093 arg_regs[(regno - 34) / 2 + 1] = "FR";
5094 #endif
5095 }
5096 }
5097 }
5098 fputs ("\t.CALL ", asm_out_file);
5099 for (i = 0; i < 4; i++)
5100 {
5101 if (arg_regs[i])
5102 {
5103 if (output_flag++)
5104 fputc (',', asm_out_file);
5105 fprintf (asm_out_file, "ARGW%d=%s", i, arg_regs[i]);
5106 }
5107 }
5108 fputc ('\n', asm_out_file);
5109 }
5110
5111 /* Return the class of any secondary reload register that is needed to
5112 move IN into a register in class CLASS using mode MODE.
5113
5114 Profiling has showed this routine and its descendants account for
5115 a significant amount of compile time (~7%). So it has been
5116 optimized to reduce redundant computations and eliminate useless
5117 function calls.
5118
5119 It might be worthwhile to try and make this a leaf function too. */
5120
5121 enum reg_class
secondary_reload_class(class,mode,in)5122 secondary_reload_class (class, mode, in)
5123 enum reg_class class;
5124 enum machine_mode mode;
5125 rtx in;
5126 {
5127 int regno, is_symbolic;
5128
5129 /* Trying to load a constant into a FP register during PIC code
5130 generation will require %r1 as a scratch register. */
5131 if (flag_pic
5132 && GET_MODE_CLASS (mode) == MODE_INT
5133 && FP_REG_CLASS_P (class)
5134 && (GET_CODE (in) == CONST_INT || GET_CODE (in) == CONST_DOUBLE))
5135 return R1_REGS;
5136
5137 /* Profiling showed the PA port spends about 1.3% of its compilation
5138 time in true_regnum from calls inside secondary_reload_class. */
5139
5140 if (GET_CODE (in) == REG)
5141 {
5142 regno = REGNO (in);
5143 if (regno >= FIRST_PSEUDO_REGISTER)
5144 regno = true_regnum (in);
5145 }
5146 else if (GET_CODE (in) == SUBREG)
5147 regno = true_regnum (in);
5148 else
5149 regno = -1;
5150
5151 /* If we have something like (mem (mem (...)), we can safely assume the
5152 inner MEM will end up in a general register after reloading, so there's
5153 no need for a secondary reload. */
5154 if (GET_CODE (in) == MEM
5155 && GET_CODE (XEXP (in, 0)) == MEM)
5156 return NO_REGS;
5157
5158 /* Handle out of range displacement for integer mode loads/stores of
5159 FP registers. */
5160 if (((regno >= FIRST_PSEUDO_REGISTER || regno == -1)
5161 && GET_MODE_CLASS (mode) == MODE_INT
5162 && FP_REG_CLASS_P (class))
5163 || (class == SHIFT_REGS && (regno <= 0 || regno >= 32)))
5164 return GENERAL_REGS;
5165
5166 /* A SAR<->FP register copy requires a secondary register (GPR) as
5167 well as secondary memory. */
5168 if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER
5169 && ((REGNO_REG_CLASS (regno) == SHIFT_REGS && FP_REG_CLASS_P (class))
5170 || (class == SHIFT_REGS && FP_REG_CLASS_P (REGNO_REG_CLASS (regno)))))
5171 return GENERAL_REGS;
5172
5173 if (GET_CODE (in) == HIGH)
5174 in = XEXP (in, 0);
5175
5176 /* Profiling has showed GCC spends about 2.6% of its compilation
5177 time in symbolic_operand from calls inside secondary_reload_class.
5178
5179 We use an inline copy and only compute its return value once to avoid
5180 useless work. */
5181 switch (GET_CODE (in))
5182 {
5183 rtx tmp;
5184
5185 case SYMBOL_REF:
5186 case LABEL_REF:
5187 is_symbolic = 1;
5188 break;
5189 case CONST:
5190 tmp = XEXP (in, 0);
5191 is_symbolic = ((GET_CODE (XEXP (tmp, 0)) == SYMBOL_REF
5192 || GET_CODE (XEXP (tmp, 0)) == LABEL_REF)
5193 && GET_CODE (XEXP (tmp, 1)) == CONST_INT);
5194 break;
5195
5196 default:
5197 is_symbolic = 0;
5198 break;
5199 }
5200
5201 if (!flag_pic
5202 && is_symbolic
5203 && read_only_operand (in, VOIDmode))
5204 return NO_REGS;
5205
5206 if (class != R1_REGS && is_symbolic)
5207 return R1_REGS;
5208
5209 return NO_REGS;
5210 }
5211
5212 enum direction
function_arg_padding(mode,type)5213 function_arg_padding (mode, type)
5214 enum machine_mode mode;
5215 tree type;
5216 {
5217 if (mode == BLKmode
5218 || (TARGET_64BIT && type && AGGREGATE_TYPE_P (type)))
5219 {
5220 /* Return none if justification is not required. */
5221 if (type
5222 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
5223 && (int_size_in_bytes (type) * BITS_PER_UNIT) % PARM_BOUNDARY == 0)
5224 return none;
5225
5226 /* The directions set here are ignored when a BLKmode argument larger
5227 than a word is placed in a register. Different code is used for
5228 the stack and registers. This makes it difficult to have a
5229 consistent data representation for both the stack and registers.
5230 For both runtimes, the justification and padding for arguments on
5231 the stack and in registers should be identical. */
5232 if (TARGET_64BIT)
5233 /* The 64-bit runtime specifies left justification for aggregates. */
5234 return upward;
5235 else
5236 /* The 32-bit runtime architecture specifies right justification.
5237 When the argument is passed on the stack, the argument is padded
5238 with garbage on the left. The HP compiler pads with zeros. */
5239 return downward;
5240 }
5241
5242 if (GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
5243 return downward;
5244 else
5245 return none;
5246 }
5247
5248
5249 /* Do what is necessary for `va_start'. We look at the current function
5250 to determine if stdargs or varargs is used and fill in an initial
5251 va_list. A pointer to this constructor is returned. */
5252
5253 struct rtx_def *
hppa_builtin_saveregs()5254 hppa_builtin_saveregs ()
5255 {
5256 rtx offset, dest;
5257 tree fntype = TREE_TYPE (current_function_decl);
5258 int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
5259 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
5260 != void_type_node)))
5261 ? UNITS_PER_WORD : 0);
5262
5263 if (argadj)
5264 offset = plus_constant (current_function_arg_offset_rtx, argadj);
5265 else
5266 offset = current_function_arg_offset_rtx;
5267
5268 if (TARGET_64BIT)
5269 {
5270 int i, off;
5271
5272 /* Adjust for varargs/stdarg differences. */
5273 if (argadj)
5274 offset = plus_constant (current_function_arg_offset_rtx, -argadj);
5275 else
5276 offset = current_function_arg_offset_rtx;
5277
5278 /* We need to save %r26 .. %r19 inclusive starting at offset -64
5279 from the incoming arg pointer and growing to larger addresses. */
5280 for (i = 26, off = -64; i >= 19; i--, off += 8)
5281 emit_move_insn (gen_rtx_MEM (word_mode,
5282 plus_constant (arg_pointer_rtx, off)),
5283 gen_rtx_REG (word_mode, i));
5284
5285 /* The incoming args pointer points just beyond the flushback area;
5286 normally this is not a serious concern. However, when we are doing
5287 varargs/stdargs we want to make the arg pointer point to the start
5288 of the incoming argument area. */
5289 emit_move_insn (virtual_incoming_args_rtx,
5290 plus_constant (arg_pointer_rtx, -64));
5291
5292 /* Now return a pointer to the first anonymous argument. */
5293 return copy_to_reg (expand_binop (Pmode, add_optab,
5294 virtual_incoming_args_rtx,
5295 offset, 0, 0, OPTAB_LIB_WIDEN));
5296 }
5297
5298 /* Store general registers on the stack. */
5299 dest = gen_rtx_MEM (BLKmode,
5300 plus_constant (current_function_internal_arg_pointer,
5301 -16));
5302 set_mem_alias_set (dest, get_varargs_alias_set ());
5303 set_mem_align (dest, BITS_PER_WORD);
5304 move_block_from_reg (23, dest, 4, 4 * UNITS_PER_WORD);
5305
5306 /* move_block_from_reg will emit code to store the argument registers
5307 individually as scalar stores.
5308
5309 However, other insns may later load from the same addresses for
5310 a structure load (passing a struct to a varargs routine).
5311
5312 The alias code assumes that such aliasing can never happen, so we
5313 have to keep memory referencing insns from moving up beyond the
5314 last argument register store. So we emit a blockage insn here. */
5315 emit_insn (gen_blockage ());
5316
5317 return copy_to_reg (expand_binop (Pmode, add_optab,
5318 current_function_internal_arg_pointer,
5319 offset, 0, 0, OPTAB_LIB_WIDEN));
5320 }
5321
5322 void
hppa_va_start(valist,nextarg)5323 hppa_va_start (valist, nextarg)
5324 tree valist;
5325 rtx nextarg;
5326 {
5327 nextarg = expand_builtin_saveregs ();
5328 std_expand_builtin_va_start (valist, nextarg);
5329 }
5330
5331 rtx
hppa_va_arg(valist,type)5332 hppa_va_arg (valist, type)
5333 tree valist, type;
5334 {
5335 HOST_WIDE_INT size = int_size_in_bytes (type);
5336 HOST_WIDE_INT ofs;
5337 tree t, ptr, pptr;
5338
5339 if (TARGET_64BIT)
5340 {
5341 /* Every argument in PA64 is supposed to be passed by value
5342 (including large structs). However, as a GCC extension, we
5343 pass zero and variable sized arguments by reference. Empty
5344 structures are a GCC extension not supported by the HP
5345 compilers. Thus, passing them by reference isn't likely
5346 to conflict with the ABI. For variable sized arguments,
5347 GCC doesn't have the infrastructure to allocate these to
5348 registers. */
5349
5350 /* Arguments with a size greater than 8 must be aligned 0 MOD 16. */
5351
5352 if (size > UNITS_PER_WORD)
5353 {
5354 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
5355 build_int_2 (2 * UNITS_PER_WORD - 1, 0));
5356 t = build (BIT_AND_EXPR, TREE_TYPE (t), t,
5357 build_int_2 (-2 * UNITS_PER_WORD, -1));
5358 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
5359 TREE_SIDE_EFFECTS (t) = 1;
5360 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5361 }
5362
5363 if (size > 0)
5364 return std_expand_builtin_va_arg (valist, type);
5365 else
5366 {
5367 ptr = build_pointer_type (type);
5368
5369 /* Args grow upward. */
5370 t = build (POSTINCREMENT_EXPR, TREE_TYPE (valist), valist,
5371 build_int_2 (POINTER_SIZE / BITS_PER_UNIT, 0));
5372 TREE_SIDE_EFFECTS (t) = 1;
5373
5374 pptr = build_pointer_type (ptr);
5375 t = build1 (NOP_EXPR, pptr, t);
5376 TREE_SIDE_EFFECTS (t) = 1;
5377
5378 t = build1 (INDIRECT_REF, ptr, t);
5379 TREE_SIDE_EFFECTS (t) = 1;
5380 }
5381 }
5382 else /* !TARGET_64BIT */
5383 {
5384 ptr = build_pointer_type (type);
5385
5386 /* "Large" and variable sized types are passed by reference. */
5387 if (size > 8 || size <= 0)
5388 {
5389 /* Args grow downward. */
5390 t = build (PREDECREMENT_EXPR, TREE_TYPE (valist), valist,
5391 build_int_2 (POINTER_SIZE / BITS_PER_UNIT, 0));
5392 TREE_SIDE_EFFECTS (t) = 1;
5393
5394 pptr = build_pointer_type (ptr);
5395 t = build1 (NOP_EXPR, pptr, t);
5396 TREE_SIDE_EFFECTS (t) = 1;
5397
5398 t = build1 (INDIRECT_REF, ptr, t);
5399 TREE_SIDE_EFFECTS (t) = 1;
5400 }
5401 else
5402 {
5403 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
5404 build_int_2 (-size, -1));
5405
5406 /* Copied from va-pa.h, but we probably don't need to align to
5407 word size, since we generate and preserve that invariant. */
5408 t = build (BIT_AND_EXPR, TREE_TYPE (valist), t,
5409 build_int_2 ((size > 4 ? -8 : -4), -1));
5410
5411 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
5412 TREE_SIDE_EFFECTS (t) = 1;
5413
5414 ofs = (8 - size) % 4;
5415 if (ofs)
5416 {
5417 t = build (PLUS_EXPR, TREE_TYPE (valist), t,
5418 build_int_2 (ofs, 0));
5419 TREE_SIDE_EFFECTS (t) = 1;
5420 }
5421
5422 t = build1 (NOP_EXPR, ptr, t);
5423 TREE_SIDE_EFFECTS (t) = 1;
5424 }
5425 }
5426
5427 /* Calculate! */
5428 return expand_expr (t, NULL_RTX, VOIDmode, EXPAND_NORMAL);
5429 }
5430
5431
5432
5433 /* This routine handles all the normal conditional branch sequences we
5434 might need to generate. It handles compare immediate vs compare
5435 register, nullification of delay slots, varying length branches,
5436 negated branches, and all combinations of the above. It returns the
5437 output appropriate to emit the branch corresponding to all given
5438 parameters. */
5439
5440 const char *
output_cbranch(operands,nullify,length,negated,insn)5441 output_cbranch (operands, nullify, length, negated, insn)
5442 rtx *operands;
5443 int nullify, length, negated;
5444 rtx insn;
5445 {
5446 static char buf[100];
5447 int useskip = 0;
5448 rtx xoperands[5];
5449
5450 /* A conditional branch to the following instruction (eg the delay slot)
5451 is asking for a disaster. This can happen when not optimizing and
5452 when jump optimization fails.
5453
5454 While it is usually safe to emit nothing, this can fail if the
5455 preceding instruction is a nullified branch with an empty delay
5456 slot and the same branch target as this branch. We could check
5457 for this but jump optimization should eliminate nop jumps. It
5458 is always safe to emit a nop. */
5459 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
5460 return "nop";
5461
5462 /* If this is a long branch with its delay slot unfilled, set `nullify'
5463 as it can nullify the delay slot and save a nop. */
5464 if (length == 8 && dbr_sequence_length () == 0)
5465 nullify = 1;
5466
5467 /* If this is a short forward conditional branch which did not get
5468 its delay slot filled, the delay slot can still be nullified. */
5469 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5470 nullify = forward_branch_p (insn);
5471
5472 /* A forward branch over a single nullified insn can be done with a
5473 comclr instruction. This avoids a single cycle penalty due to
5474 mis-predicted branch if we fall through (branch not taken). */
5475 if (length == 4
5476 && next_real_insn (insn) != 0
5477 && get_attr_length (next_real_insn (insn)) == 4
5478 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
5479 && nullify)
5480 useskip = 1;
5481
5482 switch (length)
5483 {
5484 /* All short conditional branches except backwards with an unfilled
5485 delay slot. */
5486 case 4:
5487 if (useskip)
5488 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
5489 else
5490 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5491 if (GET_MODE (operands[1]) == DImode)
5492 strcat (buf, "*");
5493 if (negated)
5494 strcat (buf, "%B3");
5495 else
5496 strcat (buf, "%S3");
5497 if (useskip)
5498 strcat (buf, " %2,%r1,%%r0");
5499 else if (nullify)
5500 strcat (buf, ",n %2,%r1,%0");
5501 else
5502 strcat (buf, " %2,%r1,%0");
5503 break;
5504
5505 /* All long conditionals. Note an short backward branch with an
5506 unfilled delay slot is treated just like a long backward branch
5507 with an unfilled delay slot. */
5508 case 8:
5509 /* Handle weird backwards branch with a filled delay slot
5510 with is nullified. */
5511 if (dbr_sequence_length () != 0
5512 && ! forward_branch_p (insn)
5513 && nullify)
5514 {
5515 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5516 if (GET_MODE (operands[1]) == DImode)
5517 strcat (buf, "*");
5518 if (negated)
5519 strcat (buf, "%S3");
5520 else
5521 strcat (buf, "%B3");
5522 strcat (buf, ",n %2,%r1,.+12\n\tb %0");
5523 }
5524 /* Handle short backwards branch with an unfilled delay slot.
5525 Using a comb;nop rather than comiclr;bl saves 1 cycle for both
5526 taken and untaken branches. */
5527 else if (dbr_sequence_length () == 0
5528 && ! forward_branch_p (insn)
5529 && INSN_ADDRESSES_SET_P ()
5530 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5531 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5532 {
5533 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5534 if (GET_MODE (operands[1]) == DImode)
5535 strcat (buf, "*");
5536 if (negated)
5537 strcat (buf, "%B3 %2,%r1,%0%#");
5538 else
5539 strcat (buf, "%S3 %2,%r1,%0%#");
5540 }
5541 else
5542 {
5543 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
5544 if (GET_MODE (operands[1]) == DImode)
5545 strcat (buf, "*");
5546 if (negated)
5547 strcat (buf, "%S3");
5548 else
5549 strcat (buf, "%B3");
5550 if (nullify)
5551 strcat (buf, " %2,%r1,%%r0\n\tb,n %0");
5552 else
5553 strcat (buf, " %2,%r1,%%r0\n\tb %0");
5554 }
5555 break;
5556
5557 case 20:
5558 case 28:
5559 xoperands[0] = operands[0];
5560 xoperands[1] = operands[1];
5561 xoperands[2] = operands[2];
5562 xoperands[3] = operands[3];
5563
5564 /* The reversed conditional branch must branch over one additional
5565 instruction if the delay slot is filled. If the delay slot
5566 is empty, the instruction after the reversed condition branch
5567 must be nullified. */
5568 nullify = dbr_sequence_length () == 0;
5569 xoperands[4] = nullify ? GEN_INT (length) : GEN_INT (length + 4);
5570
5571 /* Create a reversed conditional branch which branches around
5572 the following insns. */
5573 if (GET_MODE (operands[1]) != DImode)
5574 {
5575 if (nullify)
5576 {
5577 if (negated)
5578 strcpy (buf,
5579 "{com%I2b,%S3,n %2,%r1,.+%4|cmp%I2b,%S3,n %2,%r1,.+%4}");
5580 else
5581 strcpy (buf,
5582 "{com%I2b,%B3,n %2,%r1,.+%4|cmp%I2b,%B3,n %2,%r1,.+%4}");
5583 }
5584 else
5585 {
5586 if (negated)
5587 strcpy (buf,
5588 "{com%I2b,%S3 %2,%r1,.+%4|cmp%I2b,%S3 %2,%r1,.+%4}");
5589 else
5590 strcpy (buf,
5591 "{com%I2b,%B3 %2,%r1,.+%4|cmp%I2b,%B3 %2,%r1,.+%4}");
5592 }
5593 }
5594 else
5595 {
5596 if (nullify)
5597 {
5598 if (negated)
5599 strcpy (buf,
5600 "{com%I2b,*%S3,n %2,%r1,.+%4|cmp%I2b,*%S3,n %2,%r1,.+%4}");
5601 else
5602 strcpy (buf,
5603 "{com%I2b,*%B3,n %2,%r1,.+%4|cmp%I2b,*%B3,n %2,%r1,.+%4}");
5604 }
5605 else
5606 {
5607 if (negated)
5608 strcpy (buf,
5609 "{com%I2b,*%S3 %2,%r1,.+%4|cmp%I2b,*%S3 %2,%r1,.+%4}");
5610 else
5611 strcpy (buf,
5612 "{com%I2b,*%B3 %2,%r1,.+%4|cmp%I2b,*%B3 %2,%r1,.+%4}");
5613 }
5614 }
5615
5616 output_asm_insn (buf, xoperands);
5617 return output_lbranch (operands[0], insn);
5618
5619 default:
5620 abort ();
5621 }
5622 return buf;
5623 }
5624
5625 /* This routine handles long unconditional branches that exceed the
5626 maximum range of a simple branch instruction. */
5627
5628 const char *
output_lbranch(dest,insn)5629 output_lbranch (dest, insn)
5630 rtx dest, insn;
5631 {
5632 rtx xoperands[2];
5633
5634 xoperands[0] = dest;
5635
5636 /* First, free up the delay slot. */
5637 if (dbr_sequence_length () != 0)
5638 {
5639 /* We can't handle a jump in the delay slot. */
5640 if (GET_CODE (NEXT_INSN (insn)) == JUMP_INSN)
5641 abort ();
5642
5643 final_scan_insn (NEXT_INSN (insn), asm_out_file,
5644 optimize, 0, 0);
5645
5646 /* Now delete the delay insn. */
5647 PUT_CODE (NEXT_INSN (insn), NOTE);
5648 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
5649 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
5650 }
5651
5652 /* Output an insn to save %r1. The runtime documentation doesn't
5653 specify whether the "Clean Up" slot in the callers frame can
5654 be clobbered by the callee. It isn't copied by HP's builtin
5655 alloca, so this suggests that it can be clobbered if necessary.
5656 The "Static Link" location is copied by HP builtin alloca, so
5657 we avoid using it. Using the cleanup slot might be a problem
5658 if we have to interoperate with languages that pass cleanup
5659 information. However, it should be possible to handle these
5660 situations with GCC's asm feature.
5661
5662 The "Current RP" slot is reserved for the called procedure, so
5663 we try to use it when we don't have a frame of our own. It's
5664 rather unlikely that we won't have a frame when we need to emit
5665 a very long branch.
5666
5667 Really the way to go long term is a register scavenger; goto
5668 the target of the jump and find a register which we can use
5669 as a scratch to hold the value in %r1. Then, we wouldn't have
5670 to free up the delay slot or clobber a slot that may be needed
5671 for other purposes. */
5672 if (TARGET_64BIT)
5673 {
5674 if (actual_fsize == 0 && !regs_ever_live[2])
5675 /* Use the return pointer slot in the frame marker. */
5676 output_asm_insn ("std %%r1,-16(%%r30)", xoperands);
5677 else
5678 /* Use the slot at -40 in the frame marker since HP builtin
5679 alloca doesn't copy it. */
5680 output_asm_insn ("std %%r1,-40(%%r30)", xoperands);
5681 }
5682 else
5683 {
5684 if (actual_fsize == 0 && !regs_ever_live[2])
5685 /* Use the return pointer slot in the frame marker. */
5686 output_asm_insn ("stw %%r1,-20(%%r30)", xoperands);
5687 else
5688 /* Use the "Clean Up" slot in the frame marker. In GCC,
5689 the only other use of this location is for copying a
5690 floating point double argument from a floating-point
5691 register to two general registers. The copy is done
5692 as an "atomic" operation when outputing a call, so it
5693 won't interfere with our using the location here. */
5694 output_asm_insn ("stw %%r1,-12(%%r30)", xoperands);
5695 }
5696
5697 if (flag_pic)
5698 {
5699 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
5700 if (TARGET_SOM || !TARGET_GAS)
5701 {
5702 xoperands[1] = gen_label_rtx ();
5703 output_asm_insn ("addil L'%l0-%l1,%%r1", xoperands);
5704 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5705 CODE_LABEL_NUMBER (xoperands[1]));
5706 output_asm_insn ("ldo R'%l0-%l1(%%r1),%%r1", xoperands);
5707 }
5708 else
5709 {
5710 output_asm_insn ("addil L'%l0-$PIC_pcrel$0+4,%%r1", xoperands);
5711 output_asm_insn ("ldo R'%l0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
5712 }
5713 output_asm_insn ("bv %%r0(%%r1)", xoperands);
5714 }
5715 else
5716 /* Now output a very long branch to the original target. */
5717 output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", xoperands);
5718
5719 /* Now restore the value of %r1 in the delay slot. */
5720 if (TARGET_64BIT)
5721 {
5722 if (actual_fsize == 0 && !regs_ever_live[2])
5723 return "ldd -16(%%r30),%%r1";
5724 else
5725 return "ldd -40(%%r30),%%r1";
5726 }
5727 else
5728 {
5729 if (actual_fsize == 0 && !regs_ever_live[2])
5730 return "ldw -20(%%r30),%%r1";
5731 else
5732 return "ldw -12(%%r30),%%r1";
5733 }
5734 }
5735
5736 /* This routine handles all the branch-on-bit conditional branch sequences we
5737 might need to generate. It handles nullification of delay slots,
5738 varying length branches, negated branches and all combinations of the
5739 above. it returns the appropriate output template to emit the branch. */
5740
5741 const char *
output_bb(operands,nullify,length,negated,insn,which)5742 output_bb (operands, nullify, length, negated, insn, which)
5743 rtx *operands ATTRIBUTE_UNUSED;
5744 int nullify, length, negated;
5745 rtx insn;
5746 int which;
5747 {
5748 static char buf[100];
5749 int useskip = 0;
5750
5751 /* A conditional branch to the following instruction (eg the delay slot) is
5752 asking for a disaster. I do not think this can happen as this pattern
5753 is only used when optimizing; jump optimization should eliminate the
5754 jump. But be prepared just in case. */
5755
5756 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
5757 return "nop";
5758
5759 /* If this is a long branch with its delay slot unfilled, set `nullify'
5760 as it can nullify the delay slot and save a nop. */
5761 if (length == 8 && dbr_sequence_length () == 0)
5762 nullify = 1;
5763
5764 /* If this is a short forward conditional branch which did not get
5765 its delay slot filled, the delay slot can still be nullified. */
5766 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5767 nullify = forward_branch_p (insn);
5768
5769 /* A forward branch over a single nullified insn can be done with a
5770 extrs instruction. This avoids a single cycle penalty due to
5771 mis-predicted branch if we fall through (branch not taken). */
5772
5773 if (length == 4
5774 && next_real_insn (insn) != 0
5775 && get_attr_length (next_real_insn (insn)) == 4
5776 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
5777 && nullify)
5778 useskip = 1;
5779
5780 switch (length)
5781 {
5782
5783 /* All short conditional branches except backwards with an unfilled
5784 delay slot. */
5785 case 4:
5786 if (useskip)
5787 strcpy (buf, "{extrs,|extrw,s,}");
5788 else
5789 strcpy (buf, "bb,");
5790 if (useskip && GET_MODE (operands[0]) == DImode)
5791 strcpy (buf, "extrd,s,*");
5792 else if (GET_MODE (operands[0]) == DImode)
5793 strcpy (buf, "bb,*");
5794 if ((which == 0 && negated)
5795 || (which == 1 && ! negated))
5796 strcat (buf, ">=");
5797 else
5798 strcat (buf, "<");
5799 if (useskip)
5800 strcat (buf, " %0,%1,1,%%r0");
5801 else if (nullify && negated)
5802 strcat (buf, ",n %0,%1,%3");
5803 else if (nullify && ! negated)
5804 strcat (buf, ",n %0,%1,%2");
5805 else if (! nullify && negated)
5806 strcat (buf, "%0,%1,%3");
5807 else if (! nullify && ! negated)
5808 strcat (buf, " %0,%1,%2");
5809 break;
5810
5811 /* All long conditionals. Note an short backward branch with an
5812 unfilled delay slot is treated just like a long backward branch
5813 with an unfilled delay slot. */
5814 case 8:
5815 /* Handle weird backwards branch with a filled delay slot
5816 with is nullified. */
5817 if (dbr_sequence_length () != 0
5818 && ! forward_branch_p (insn)
5819 && nullify)
5820 {
5821 strcpy (buf, "bb,");
5822 if (GET_MODE (operands[0]) == DImode)
5823 strcat (buf, "*");
5824 if ((which == 0 && negated)
5825 || (which == 1 && ! negated))
5826 strcat (buf, "<");
5827 else
5828 strcat (buf, ">=");
5829 if (negated)
5830 strcat (buf, ",n %0,%1,.+12\n\tb %3");
5831 else
5832 strcat (buf, ",n %0,%1,.+12\n\tb %2");
5833 }
5834 /* Handle short backwards branch with an unfilled delay slot.
5835 Using a bb;nop rather than extrs;bl saves 1 cycle for both
5836 taken and untaken branches. */
5837 else if (dbr_sequence_length () == 0
5838 && ! forward_branch_p (insn)
5839 && INSN_ADDRESSES_SET_P ()
5840 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5841 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5842 {
5843 strcpy (buf, "bb,");
5844 if (GET_MODE (operands[0]) == DImode)
5845 strcat (buf, "*");
5846 if ((which == 0 && negated)
5847 || (which == 1 && ! negated))
5848 strcat (buf, ">=");
5849 else
5850 strcat (buf, "<");
5851 if (negated)
5852 strcat (buf, " %0,%1,%3%#");
5853 else
5854 strcat (buf, " %0,%1,%2%#");
5855 }
5856 else
5857 {
5858 strcpy (buf, "{extrs,|extrw,s,}");
5859 if (GET_MODE (operands[0]) == DImode)
5860 strcpy (buf, "extrd,s,*");
5861 if ((which == 0 && negated)
5862 || (which == 1 && ! negated))
5863 strcat (buf, "<");
5864 else
5865 strcat (buf, ">=");
5866 if (nullify && negated)
5867 strcat (buf, " %0,%1,1,%%r0\n\tb,n %3");
5868 else if (nullify && ! negated)
5869 strcat (buf, " %0,%1,1,%%r0\n\tb,n %2");
5870 else if (negated)
5871 strcat (buf, " %0,%1,1,%%r0\n\tb %3");
5872 else
5873 strcat (buf, " %0,%1,1,%%r0\n\tb %2");
5874 }
5875 break;
5876
5877 default:
5878 abort ();
5879 }
5880 return buf;
5881 }
5882
5883 /* This routine handles all the branch-on-variable-bit conditional branch
5884 sequences we might need to generate. It handles nullification of delay
5885 slots, varying length branches, negated branches and all combinations
5886 of the above. it returns the appropriate output template to emit the
5887 branch. */
5888
5889 const char *
output_bvb(operands,nullify,length,negated,insn,which)5890 output_bvb (operands, nullify, length, negated, insn, which)
5891 rtx *operands ATTRIBUTE_UNUSED;
5892 int nullify, length, negated;
5893 rtx insn;
5894 int which;
5895 {
5896 static char buf[100];
5897 int useskip = 0;
5898
5899 /* A conditional branch to the following instruction (eg the delay slot) is
5900 asking for a disaster. I do not think this can happen as this pattern
5901 is only used when optimizing; jump optimization should eliminate the
5902 jump. But be prepared just in case. */
5903
5904 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
5905 return "nop";
5906
5907 /* If this is a long branch with its delay slot unfilled, set `nullify'
5908 as it can nullify the delay slot and save a nop. */
5909 if (length == 8 && dbr_sequence_length () == 0)
5910 nullify = 1;
5911
5912 /* If this is a short forward conditional branch which did not get
5913 its delay slot filled, the delay slot can still be nullified. */
5914 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5915 nullify = forward_branch_p (insn);
5916
5917 /* A forward branch over a single nullified insn can be done with a
5918 extrs instruction. This avoids a single cycle penalty due to
5919 mis-predicted branch if we fall through (branch not taken). */
5920
5921 if (length == 4
5922 && next_real_insn (insn) != 0
5923 && get_attr_length (next_real_insn (insn)) == 4
5924 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
5925 && nullify)
5926 useskip = 1;
5927
5928 switch (length)
5929 {
5930
5931 /* All short conditional branches except backwards with an unfilled
5932 delay slot. */
5933 case 4:
5934 if (useskip)
5935 strcpy (buf, "{vextrs,|extrw,s,}");
5936 else
5937 strcpy (buf, "{bvb,|bb,}");
5938 if (useskip && GET_MODE (operands[0]) == DImode)
5939 strcpy (buf, "extrd,s,*");
5940 else if (GET_MODE (operands[0]) == DImode)
5941 strcpy (buf, "bb,*");
5942 if ((which == 0 && negated)
5943 || (which == 1 && ! negated))
5944 strcat (buf, ">=");
5945 else
5946 strcat (buf, "<");
5947 if (useskip)
5948 strcat (buf, "{ %0,1,%%r0| %0,%%sar,1,%%r0}");
5949 else if (nullify && negated)
5950 strcat (buf, "{,n %0,%3|,n %0,%%sar,%3}");
5951 else if (nullify && ! negated)
5952 strcat (buf, "{,n %0,%2|,n %0,%%sar,%2}");
5953 else if (! nullify && negated)
5954 strcat (buf, "{%0,%3|%0,%%sar,%3}");
5955 else if (! nullify && ! negated)
5956 strcat (buf, "{ %0,%2| %0,%%sar,%2}");
5957 break;
5958
5959 /* All long conditionals. Note an short backward branch with an
5960 unfilled delay slot is treated just like a long backward branch
5961 with an unfilled delay slot. */
5962 case 8:
5963 /* Handle weird backwards branch with a filled delay slot
5964 with is nullified. */
5965 if (dbr_sequence_length () != 0
5966 && ! forward_branch_p (insn)
5967 && nullify)
5968 {
5969 strcpy (buf, "{bvb,|bb,}");
5970 if (GET_MODE (operands[0]) == DImode)
5971 strcat (buf, "*");
5972 if ((which == 0 && negated)
5973 || (which == 1 && ! negated))
5974 strcat (buf, "<");
5975 else
5976 strcat (buf, ">=");
5977 if (negated)
5978 strcat (buf, "{,n %0,.+12\n\tb %3|,n %0,%%sar,.+12\n\tb %3}");
5979 else
5980 strcat (buf, "{,n %0,.+12\n\tb %2|,n %0,%%sar,.+12\n\tb %2}");
5981 }
5982 /* Handle short backwards branch with an unfilled delay slot.
5983 Using a bb;nop rather than extrs;bl saves 1 cycle for both
5984 taken and untaken branches. */
5985 else if (dbr_sequence_length () == 0
5986 && ! forward_branch_p (insn)
5987 && INSN_ADDRESSES_SET_P ()
5988 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5989 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5990 {
5991 strcpy (buf, "{bvb,|bb,}");
5992 if (GET_MODE (operands[0]) == DImode)
5993 strcat (buf, "*");
5994 if ((which == 0 && negated)
5995 || (which == 1 && ! negated))
5996 strcat (buf, ">=");
5997 else
5998 strcat (buf, "<");
5999 if (negated)
6000 strcat (buf, "{ %0,%3%#| %0,%%sar,%3%#}");
6001 else
6002 strcat (buf, "{ %0,%2%#| %0,%%sar,%2%#}");
6003 }
6004 else
6005 {
6006 strcpy (buf, "{vextrs,|extrw,s,}");
6007 if (GET_MODE (operands[0]) == DImode)
6008 strcpy (buf, "extrd,s,*");
6009 if ((which == 0 && negated)
6010 || (which == 1 && ! negated))
6011 strcat (buf, "<");
6012 else
6013 strcat (buf, ">=");
6014 if (nullify && negated)
6015 strcat (buf, "{ %0,1,%%r0\n\tb,n %3| %0,%%sar,1,%%r0\n\tb,n %3}");
6016 else if (nullify && ! negated)
6017 strcat (buf, "{ %0,1,%%r0\n\tb,n %2| %0,%%sar,1,%%r0\n\tb,n %2}");
6018 else if (negated)
6019 strcat (buf, "{ %0,1,%%r0\n\tb %3| %0,%%sar,1,%%r0\n\tb %3}");
6020 else
6021 strcat (buf, "{ %0,1,%%r0\n\tb %2| %0,%%sar,1,%%r0\n\tb %2}");
6022 }
6023 break;
6024
6025 default:
6026 abort ();
6027 }
6028 return buf;
6029 }
6030
6031 /* Return the output template for emitting a dbra type insn.
6032
6033 Note it may perform some output operations on its own before
6034 returning the final output string. */
6035 const char *
output_dbra(operands,insn,which_alternative)6036 output_dbra (operands, insn, which_alternative)
6037 rtx *operands;
6038 rtx insn;
6039 int which_alternative;
6040 {
6041
6042 /* A conditional branch to the following instruction (eg the delay slot) is
6043 asking for a disaster. Be prepared! */
6044
6045 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6046 {
6047 if (which_alternative == 0)
6048 return "ldo %1(%0),%0";
6049 else if (which_alternative == 1)
6050 {
6051 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)", operands);
6052 output_asm_insn ("ldw -16(%%r30),%4", operands);
6053 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
6054 return "{fldws|fldw} -16(%%r30),%0";
6055 }
6056 else
6057 {
6058 output_asm_insn ("ldw %0,%4", operands);
6059 return "ldo %1(%4),%4\n\tstw %4,%0";
6060 }
6061 }
6062
6063 if (which_alternative == 0)
6064 {
6065 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6066 int length = get_attr_length (insn);
6067
6068 /* If this is a long branch with its delay slot unfilled, set `nullify'
6069 as it can nullify the delay slot and save a nop. */
6070 if (length == 8 && dbr_sequence_length () == 0)
6071 nullify = 1;
6072
6073 /* If this is a short forward conditional branch which did not get
6074 its delay slot filled, the delay slot can still be nullified. */
6075 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6076 nullify = forward_branch_p (insn);
6077
6078 /* Handle short versions first. */
6079 if (length == 4 && nullify)
6080 return "addib,%C2,n %1,%0,%3";
6081 else if (length == 4 && ! nullify)
6082 return "addib,%C2 %1,%0,%3";
6083 else if (length == 8)
6084 {
6085 /* Handle weird backwards branch with a fulled delay slot
6086 which is nullified. */
6087 if (dbr_sequence_length () != 0
6088 && ! forward_branch_p (insn)
6089 && nullify)
6090 return "addib,%N2,n %1,%0,.+12\n\tb %3";
6091 /* Handle short backwards branch with an unfilled delay slot.
6092 Using a addb;nop rather than addi;bl saves 1 cycle for both
6093 taken and untaken branches. */
6094 else if (dbr_sequence_length () == 0
6095 && ! forward_branch_p (insn)
6096 && INSN_ADDRESSES_SET_P ()
6097 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6098 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6099 return "addib,%C2 %1,%0,%3%#";
6100
6101 /* Handle normal cases. */
6102 if (nullify)
6103 return "addi,%N2 %1,%0,%0\n\tb,n %3";
6104 else
6105 return "addi,%N2 %1,%0,%0\n\tb %3";
6106 }
6107 else
6108 abort ();
6109 }
6110 /* Deal with gross reload from FP register case. */
6111 else if (which_alternative == 1)
6112 {
6113 /* Move loop counter from FP register to MEM then into a GR,
6114 increment the GR, store the GR into MEM, and finally reload
6115 the FP register from MEM from within the branch's delay slot. */
6116 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)\n\tldw -16(%%r30),%4",
6117 operands);
6118 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
6119 if (get_attr_length (insn) == 24)
6120 return "{comb|cmpb},%S2 %%r0,%4,%3\n\t{fldws|fldw} -16(%%r30),%0";
6121 else
6122 return "{comclr|cmpclr},%B2 %%r0,%4,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
6123 }
6124 /* Deal with gross reload from memory case. */
6125 else
6126 {
6127 /* Reload loop counter from memory, the store back to memory
6128 happens in the branch's delay slot. */
6129 output_asm_insn ("ldw %0,%4", operands);
6130 if (get_attr_length (insn) == 12)
6131 return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
6132 else
6133 return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0";
6134 }
6135 }
6136
6137 /* Return the output template for emitting a dbra type insn.
6138
6139 Note it may perform some output operations on its own before
6140 returning the final output string. */
6141 const char *
output_movb(operands,insn,which_alternative,reverse_comparison)6142 output_movb (operands, insn, which_alternative, reverse_comparison)
6143 rtx *operands;
6144 rtx insn;
6145 int which_alternative;
6146 int reverse_comparison;
6147 {
6148
6149 /* A conditional branch to the following instruction (eg the delay slot) is
6150 asking for a disaster. Be prepared! */
6151
6152 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6153 {
6154 if (which_alternative == 0)
6155 return "copy %1,%0";
6156 else if (which_alternative == 1)
6157 {
6158 output_asm_insn ("stw %1,-16(%%r30)", operands);
6159 return "{fldws|fldw} -16(%%r30),%0";
6160 }
6161 else if (which_alternative == 2)
6162 return "stw %1,%0";
6163 else
6164 return "mtsar %r1";
6165 }
6166
6167 /* Support the second variant. */
6168 if (reverse_comparison)
6169 PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2])));
6170
6171 if (which_alternative == 0)
6172 {
6173 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6174 int length = get_attr_length (insn);
6175
6176 /* If this is a long branch with its delay slot unfilled, set `nullify'
6177 as it can nullify the delay slot and save a nop. */
6178 if (length == 8 && dbr_sequence_length () == 0)
6179 nullify = 1;
6180
6181 /* If this is a short forward conditional branch which did not get
6182 its delay slot filled, the delay slot can still be nullified. */
6183 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6184 nullify = forward_branch_p (insn);
6185
6186 /* Handle short versions first. */
6187 if (length == 4 && nullify)
6188 return "movb,%C2,n %1,%0,%3";
6189 else if (length == 4 && ! nullify)
6190 return "movb,%C2 %1,%0,%3";
6191 else if (length == 8)
6192 {
6193 /* Handle weird backwards branch with a filled delay slot
6194 which is nullified. */
6195 if (dbr_sequence_length () != 0
6196 && ! forward_branch_p (insn)
6197 && nullify)
6198 return "movb,%N2,n %1,%0,.+12\n\tb %3";
6199
6200 /* Handle short backwards branch with an unfilled delay slot.
6201 Using a movb;nop rather than or;bl saves 1 cycle for both
6202 taken and untaken branches. */
6203 else if (dbr_sequence_length () == 0
6204 && ! forward_branch_p (insn)
6205 && INSN_ADDRESSES_SET_P ()
6206 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6207 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6208 return "movb,%C2 %1,%0,%3%#";
6209 /* Handle normal cases. */
6210 if (nullify)
6211 return "or,%N2 %1,%%r0,%0\n\tb,n %3";
6212 else
6213 return "or,%N2 %1,%%r0,%0\n\tb %3";
6214 }
6215 else
6216 abort ();
6217 }
6218 /* Deal with gross reload from FP register case. */
6219 else if (which_alternative == 1)
6220 {
6221 /* Move loop counter from FP register to MEM then into a GR,
6222 increment the GR, store the GR into MEM, and finally reload
6223 the FP register from MEM from within the branch's delay slot. */
6224 output_asm_insn ("stw %1,-16(%%r30)", operands);
6225 if (get_attr_length (insn) == 12)
6226 return "{comb|cmpb},%S2 %%r0,%1,%3\n\t{fldws|fldw} -16(%%r30),%0";
6227 else
6228 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
6229 }
6230 /* Deal with gross reload from memory case. */
6231 else if (which_alternative == 2)
6232 {
6233 /* Reload loop counter from memory, the store back to memory
6234 happens in the branch's delay slot. */
6235 if (get_attr_length (insn) == 8)
6236 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tstw %1,%0";
6237 else
6238 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0";
6239 }
6240 /* Handle SAR as a destination. */
6241 else
6242 {
6243 if (get_attr_length (insn) == 8)
6244 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tmtsar %r1";
6245 else
6246 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tbl %3\n\tmtsar %r1";
6247 }
6248 }
6249
6250 /* Copy any FP arguments in INSN into integer registers. */
6251 static void
copy_fp_args(insn)6252 copy_fp_args (insn)
6253 rtx insn;
6254 {
6255 rtx link;
6256 rtx xoperands[2];
6257
6258 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
6259 {
6260 int arg_mode, regno;
6261 rtx use = XEXP (link, 0);
6262
6263 if (! (GET_CODE (use) == USE
6264 && GET_CODE (XEXP (use, 0)) == REG
6265 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
6266 continue;
6267
6268 arg_mode = GET_MODE (XEXP (use, 0));
6269 regno = REGNO (XEXP (use, 0));
6270
6271 /* Is it a floating point register? */
6272 if (regno >= 32 && regno <= 39)
6273 {
6274 /* Copy the FP register into an integer register via memory. */
6275 if (arg_mode == SFmode)
6276 {
6277 xoperands[0] = XEXP (use, 0);
6278 xoperands[1] = gen_rtx_REG (SImode, 26 - (regno - 32) / 2);
6279 output_asm_insn ("{fstws|fstw} %0,-16(%%sr0,%%r30)", xoperands);
6280 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
6281 }
6282 else
6283 {
6284 xoperands[0] = XEXP (use, 0);
6285 xoperands[1] = gen_rtx_REG (DImode, 25 - (regno - 34) / 2);
6286 output_asm_insn ("{fstds|fstd} %0,-16(%%sr0,%%r30)", xoperands);
6287 output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands);
6288 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
6289 }
6290 }
6291 }
6292 }
6293
6294 /* Compute length of the FP argument copy sequence for INSN. */
6295 static int
length_fp_args(insn)6296 length_fp_args (insn)
6297 rtx insn;
6298 {
6299 int length = 0;
6300 rtx link;
6301
6302 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
6303 {
6304 int arg_mode, regno;
6305 rtx use = XEXP (link, 0);
6306
6307 if (! (GET_CODE (use) == USE
6308 && GET_CODE (XEXP (use, 0)) == REG
6309 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
6310 continue;
6311
6312 arg_mode = GET_MODE (XEXP (use, 0));
6313 regno = REGNO (XEXP (use, 0));
6314
6315 /* Is it a floating point register? */
6316 if (regno >= 32 && regno <= 39)
6317 {
6318 if (arg_mode == SFmode)
6319 length += 8;
6320 else
6321 length += 12;
6322 }
6323 }
6324
6325 return length;
6326 }
6327
6328 /* Return the attribute length for the millicode call instruction INSN.
6329 The length must match the code generated by output_millicode_call.
6330 We include the delay slot in the returned length as it is better to
6331 over estimate the length than to under estimate it. */
6332
6333 int
attr_length_millicode_call(insn)6334 attr_length_millicode_call (insn)
6335 rtx insn;
6336 {
6337 unsigned long distance = -1;
6338
6339 if (INSN_ADDRESSES_SET_P ())
6340 {
6341 distance = (total_code_bytes + insn_current_reference_address (insn));
6342 if (distance < total_code_bytes)
6343 distance = -1;
6344 }
6345
6346 if (TARGET_64BIT)
6347 {
6348 if (!TARGET_LONG_CALLS && distance < 7600000)
6349 return 8;
6350
6351 return 20;
6352 }
6353 else if (TARGET_PORTABLE_RUNTIME)
6354 return 24;
6355 else
6356 {
6357 if (!TARGET_LONG_CALLS && distance < 240000)
6358 return 8;
6359
6360 if (TARGET_LONG_ABS_CALL && !flag_pic)
6361 return 12;
6362
6363 return 24;
6364 }
6365 }
6366
6367 /* INSN is a function call. It may have an unconditional jump
6368 in its delay slot.
6369
6370 CALL_DEST is the routine we are calling. */
6371
6372 const char *
output_millicode_call(insn,call_dest)6373 output_millicode_call (insn, call_dest)
6374 rtx insn;
6375 rtx call_dest;
6376 {
6377 int attr_length = get_attr_length (insn);
6378 int seq_length = dbr_sequence_length ();
6379 int distance;
6380 rtx seq_insn;
6381 rtx xoperands[3];
6382
6383 xoperands[0] = call_dest;
6384 xoperands[2] = gen_rtx_REG (Pmode, TARGET_64BIT ? 2 : 31);
6385
6386 /* Handle the common case where we are sure that the branch will
6387 reach the beginning of the $CODE$ subspace. The within reach
6388 form of the $$sh_func_adrs call has a length of 28. Because
6389 it has an attribute type of multi, it never has a non-zero
6390 sequence length. The length of the $$sh_func_adrs is the same
6391 as certain out of reach PIC calls to other routines. */
6392 if (!TARGET_LONG_CALLS
6393 && ((seq_length == 0
6394 && (attr_length == 12
6395 || (attr_length == 28 && get_attr_type (insn) == TYPE_MULTI)))
6396 || (seq_length != 0 && attr_length == 8)))
6397 {
6398 output_asm_insn ("{bl|b,l} %0,%2", xoperands);
6399 }
6400 else
6401 {
6402 if (TARGET_64BIT)
6403 {
6404 /* It might seem that one insn could be saved by accessing
6405 the millicode function using the linkage table. However,
6406 this doesn't work in shared libraries and other dynamically
6407 loaded objects. Using a pc-relative sequence also avoids
6408 problems related to the implicit use of the gp register. */
6409 output_asm_insn ("b,l .+8,%%r1", xoperands);
6410
6411 if (TARGET_GAS)
6412 {
6413 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
6414 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
6415 }
6416 else
6417 {
6418 xoperands[1] = gen_label_rtx ();
6419 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
6420 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
6421 CODE_LABEL_NUMBER (xoperands[1]));
6422 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
6423 }
6424
6425 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
6426 }
6427 else if (TARGET_PORTABLE_RUNTIME)
6428 {
6429 /* Pure portable runtime doesn't allow be/ble; we also don't
6430 have PIC support in the assembler/linker, so this sequence
6431 is needed. */
6432
6433 /* Get the address of our target into %r1. */
6434 output_asm_insn ("ldil L'%0,%%r1", xoperands);
6435 output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands);
6436
6437 /* Get our return address into %r31. */
6438 output_asm_insn ("{bl|b,l} .+8,%%r31", xoperands);
6439 output_asm_insn ("addi 8,%%r31,%%r31", xoperands);
6440
6441 /* Jump to our target address in %r1. */
6442 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6443 }
6444 else if (!flag_pic)
6445 {
6446 output_asm_insn ("ldil L'%0,%%r1", xoperands);
6447 if (TARGET_PA_20)
6448 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31", xoperands);
6449 else
6450 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands);
6451 }
6452 else
6453 {
6454 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6455 output_asm_insn ("addi 16,%%r1,%%r31", xoperands);
6456
6457 if (TARGET_SOM || !TARGET_GAS)
6458 {
6459 /* The HP assembler can generate relocations for the
6460 difference of two symbols. GAS can do this for a
6461 millicode symbol but not an arbitrary external
6462 symbol when generating SOM output. */
6463 xoperands[1] = gen_label_rtx ();
6464 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
6465 CODE_LABEL_NUMBER (xoperands[1]));
6466 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
6467 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
6468 }
6469 else
6470 {
6471 output_asm_insn ("addil L'%0-$PIC_pcrel$0+8,%%r1", xoperands);
6472 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+12(%%r1),%%r1",
6473 xoperands);
6474 }
6475
6476 /* Jump to our target address in %r1. */
6477 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6478 }
6479 }
6480
6481 if (seq_length == 0)
6482 output_asm_insn ("nop", xoperands);
6483
6484 /* We are done if there isn't a jump in the delay slot. */
6485 if (seq_length == 0 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
6486 return "";
6487
6488 /* This call has an unconditional jump in its delay slot. */
6489 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
6490
6491 /* See if the return address can be adjusted. Use the containing
6492 sequence insn's address. */
6493 if (INSN_ADDRESSES_SET_P ())
6494 {
6495 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
6496 distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
6497 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8);
6498
6499 if (VAL_14_BITS_P (distance))
6500 {
6501 xoperands[1] = gen_label_rtx ();
6502 output_asm_insn ("ldo %0-%1(%2),%2", xoperands);
6503 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
6504 CODE_LABEL_NUMBER (xoperands[1]));
6505 }
6506 else
6507 /* ??? This branch may not reach its target. */
6508 output_asm_insn ("nop\n\tb,n %0", xoperands);
6509 }
6510 else
6511 /* ??? This branch may not reach its target. */
6512 output_asm_insn ("nop\n\tb,n %0", xoperands);
6513
6514 /* Delete the jump. */
6515 PUT_CODE (NEXT_INSN (insn), NOTE);
6516 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6517 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6518
6519 return "";
6520 }
6521
6522 /* Return the attribute length of the call instruction INSN. The SIBCALL
6523 flag indicates whether INSN is a regular call or a sibling call. The
6524 length must match the code generated by output_call. We include the delay
6525 slot in the returned length as it is better to over estimate the length
6526 than to under estimate it. */
6527
6528 int
attr_length_call(insn,sibcall)6529 attr_length_call (insn, sibcall)
6530 rtx insn;
6531 int sibcall;
6532 {
6533 unsigned long distance = -1;
6534
6535 if (INSN_ADDRESSES_SET_P ())
6536 {
6537 distance = (total_code_bytes + insn_current_reference_address (insn));
6538 if (distance < total_code_bytes)
6539 distance = -1;
6540 }
6541
6542 if (TARGET_64BIT)
6543 {
6544 if (!TARGET_LONG_CALLS
6545 && ((!sibcall && distance < 7600000) || distance < 240000))
6546 return 8;
6547
6548 return (sibcall ? 28 : 24);
6549 }
6550 else
6551 {
6552 if (!TARGET_LONG_CALLS
6553 && ((TARGET_PA_20 && !sibcall && distance < 7600000)
6554 || distance < 240000))
6555 return 8;
6556
6557 if (TARGET_LONG_ABS_CALL && !flag_pic)
6558 return 12;
6559
6560 if ((TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
6561 || (TARGET_GAS && TARGET_LONG_PIC_PCREL_CALL))
6562 {
6563 if (TARGET_PA_20)
6564 return 20;
6565
6566 return 28;
6567 }
6568 else
6569 {
6570 int length = 0;
6571
6572 if (TARGET_SOM)
6573 length += length_fp_args (insn);
6574
6575 if (flag_pic)
6576 length += 4;
6577
6578 if (TARGET_PA_20)
6579 return (length + 32);
6580
6581 if (!TARGET_NO_SPACE_REGS)
6582 length += 8;
6583
6584 if (!sibcall)
6585 length += 8;
6586
6587 return (length + 32);
6588 }
6589 }
6590 }
6591
6592 /* INSN is a function call. It may have an unconditional jump
6593 in its delay slot.
6594
6595 CALL_DEST is the routine we are calling. */
6596
6597 const char *
output_call(insn,call_dest,sibcall)6598 output_call (insn, call_dest, sibcall)
6599 rtx insn;
6600 rtx call_dest;
6601 int sibcall;
6602 {
6603 int delay_insn_deleted = 0;
6604 int delay_slot_filled = 0;
6605 int seq_length = dbr_sequence_length ();
6606 rtx xoperands[2];
6607
6608 xoperands[0] = call_dest;
6609
6610 /* Handle the common case where we're sure that the branch will reach
6611 the beginning of the $CODE$ subspace. */
6612 if (!TARGET_LONG_CALLS && attr_length_call (insn, sibcall) == 8)
6613 {
6614 xoperands[1] = gen_rtx_REG (word_mode, sibcall ? 0 : 2);
6615 output_asm_insn ("{bl|b,l} %0,%1", xoperands);
6616 }
6617 else
6618 {
6619 if (TARGET_64BIT)
6620 {
6621 /* ??? As far as I can tell, the HP linker doesn't support the
6622 long pc-relative sequence described in the 64-bit runtime
6623 architecture. So, we use a slightly longer indirect call. */
6624 struct deferred_plabel *p = get_plabel (XSTR (call_dest, 0));
6625
6626 xoperands[0] = p->internal_label;
6627 xoperands[1] = gen_label_rtx ();
6628
6629 /* If this isn't a sibcall, we put the load of %r27 into the
6630 delay slot. We can't do this in a sibcall as we don't
6631 have a second call-clobbered scratch register available. */
6632 if (seq_length != 0
6633 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
6634 && !sibcall)
6635 {
6636 final_scan_insn (NEXT_INSN (insn), asm_out_file,
6637 optimize, 0, 0);
6638
6639 /* Now delete the delay insn. */
6640 PUT_CODE (NEXT_INSN (insn), NOTE);
6641 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6642 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6643 delay_insn_deleted = 1;
6644 }
6645
6646 output_asm_insn ("addil LT'%0,%%r27", xoperands);
6647 output_asm_insn ("ldd RT'%0(%%r1),%%r1", xoperands);
6648 output_asm_insn ("ldd 0(%%r1),%%r1", xoperands);
6649
6650 if (sibcall)
6651 {
6652 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands);
6653 output_asm_insn ("ldd 16(%%r1),%%r1", xoperands);
6654 output_asm_insn ("bve (%%r1)", xoperands);
6655 }
6656 else
6657 {
6658 output_asm_insn ("ldd 16(%%r1),%%r2", xoperands);
6659 output_asm_insn ("bve,l (%%r2),%%r2", xoperands);
6660 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands);
6661 delay_slot_filled = 1;
6662 }
6663 }
6664 else
6665 {
6666 int indirect_call = 0;
6667
6668 /* Emit a long call. There are several different sequences
6669 of increasing length and complexity. In most cases,
6670 they don't allow an instruction in the delay slot. */
6671 if (!(TARGET_LONG_ABS_CALL && !flag_pic)
6672 && !(TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
6673 && !(TARGET_GAS && TARGET_LONG_PIC_PCREL_CALL))
6674 indirect_call = 1;
6675
6676 if (seq_length != 0
6677 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
6678 && !sibcall
6679 && (!TARGET_PA_20 || indirect_call))
6680 {
6681 /* A non-jump insn in the delay slot. By definition we can
6682 emit this insn before the call (and in fact before argument
6683 relocating. */
6684 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0, 0);
6685
6686 /* Now delete the delay insn. */
6687 PUT_CODE (NEXT_INSN (insn), NOTE);
6688 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6689 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6690 delay_insn_deleted = 1;
6691 }
6692
6693 if (TARGET_LONG_ABS_CALL && !flag_pic)
6694 {
6695 /* This is the best sequence for making long calls in
6696 non-pic code. Unfortunately, GNU ld doesn't provide
6697 the stub needed for external calls, and GAS's support
6698 for this with the SOM linker is buggy. */
6699 output_asm_insn ("ldil L'%0,%%r1", xoperands);
6700 if (sibcall)
6701 output_asm_insn ("be R'%0(%%sr4,%%r1)", xoperands);
6702 else
6703 {
6704 if (TARGET_PA_20)
6705 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31",
6706 xoperands);
6707 else
6708 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands);
6709
6710 output_asm_insn ("copy %%r31,%%r2", xoperands);
6711 delay_slot_filled = 1;
6712 }
6713 }
6714 else
6715 {
6716 if (TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
6717 {
6718 /* The HP assembler and linker can handle relocations
6719 for the difference of two symbols. GAS and the HP
6720 linker can't do this when one of the symbols is
6721 external. */
6722 xoperands[1] = gen_label_rtx ();
6723 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6724 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
6725 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
6726 CODE_LABEL_NUMBER (xoperands[1]));
6727 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
6728 }
6729 else if (TARGET_GAS && TARGET_LONG_PIC_PCREL_CALL)
6730 {
6731 /* GAS currently can't generate the relocations that
6732 are needed for the SOM linker under HP-UX using this
6733 sequence. The GNU linker doesn't generate the stubs
6734 that are needed for external calls on TARGET_ELF32
6735 with this sequence. For now, we have to use a
6736 longer plabel sequence when using GAS. */
6737 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6738 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1",
6739 xoperands);
6740 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1",
6741 xoperands);
6742 }
6743 else
6744 {
6745 /* Emit a long plabel-based call sequence. This is
6746 essentially an inline implementation of $$dyncall.
6747 We don't actually try to call $$dyncall as this is
6748 as difficult as calling the function itself. */
6749 struct deferred_plabel *p = get_plabel (XSTR (call_dest, 0));
6750
6751 xoperands[0] = p->internal_label;
6752 xoperands[1] = gen_label_rtx ();
6753
6754 /* Since the call is indirect, FP arguments in registers
6755 need to be copied to the general registers. Then, the
6756 argument relocation stub will copy them back. */
6757 if (TARGET_SOM)
6758 copy_fp_args (insn);
6759
6760 if (flag_pic)
6761 {
6762 output_asm_insn ("addil LT'%0,%%r19", xoperands);
6763 output_asm_insn ("ldw RT'%0(%%r1),%%r1", xoperands);
6764 output_asm_insn ("ldw 0(%%r1),%%r1", xoperands);
6765 }
6766 else
6767 {
6768 output_asm_insn ("addil LR'%0-$global$,%%r27",
6769 xoperands);
6770 output_asm_insn ("ldw RR'%0-$global$(%%r1),%%r1",
6771 xoperands);
6772 }
6773
6774 output_asm_insn ("bb,>=,n %%r1,30,.+16", xoperands);
6775 output_asm_insn ("depi 0,31,2,%%r1", xoperands);
6776 output_asm_insn ("ldw 4(%%sr0,%%r1),%%r19", xoperands);
6777 output_asm_insn ("ldw 0(%%sr0,%%r1),%%r1", xoperands);
6778
6779 if (!sibcall && !TARGET_PA_20)
6780 {
6781 output_asm_insn ("{bl|b,l} .+8,%%r2", xoperands);
6782 if (TARGET_NO_SPACE_REGS)
6783 output_asm_insn ("addi 8,%%r2,%%r2", xoperands);
6784 else
6785 output_asm_insn ("addi 16,%%r2,%%r2", xoperands);
6786 }
6787 }
6788
6789 if (TARGET_PA_20)
6790 {
6791 if (sibcall)
6792 output_asm_insn ("bve (%%r1)", xoperands);
6793 else
6794 {
6795 if (indirect_call)
6796 {
6797 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
6798 output_asm_insn ("stw %%r2,-24(%%sp)", xoperands);
6799 delay_slot_filled = 1;
6800 }
6801 else
6802 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
6803 }
6804 }
6805 else
6806 {
6807 if (!TARGET_NO_SPACE_REGS)
6808 output_asm_insn ("ldsid (%%r1),%%r31\n\tmtsp %%r31,%%sr0",
6809 xoperands);
6810
6811 if (sibcall)
6812 {
6813 if (TARGET_NO_SPACE_REGS)
6814 output_asm_insn ("be 0(%%sr4,%%r1)", xoperands);
6815 else
6816 output_asm_insn ("be 0(%%sr0,%%r1)", xoperands);
6817 }
6818 else
6819 {
6820 if (TARGET_NO_SPACE_REGS)
6821 output_asm_insn ("ble 0(%%sr4,%%r1)", xoperands);
6822 else
6823 output_asm_insn ("ble 0(%%sr0,%%r1)", xoperands);
6824
6825 if (indirect_call)
6826 output_asm_insn ("stw %%r31,-24(%%sp)", xoperands);
6827 else
6828 output_asm_insn ("copy %%r31,%%r2", xoperands);
6829 delay_slot_filled = 1;
6830 }
6831 }
6832 }
6833 }
6834 }
6835
6836 if (seq_length == 0 || (delay_insn_deleted && !delay_slot_filled))
6837 output_asm_insn ("nop", xoperands);
6838
6839 /* We are done if there isn't a jump in the delay slot. */
6840 if (seq_length == 0
6841 || delay_insn_deleted
6842 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
6843 return "";
6844
6845 /* A sibcall should never have a branch in the delay slot. */
6846 if (sibcall)
6847 abort ();
6848
6849 /* This call has an unconditional jump in its delay slot. */
6850 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
6851
6852 if (!delay_slot_filled && INSN_ADDRESSES_SET_P ())
6853 {
6854 /* See if the return address can be adjusted. Use the containing
6855 sequence insn's address. */
6856 rtx seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
6857 int distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
6858 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8);
6859
6860 if (VAL_14_BITS_P (distance))
6861 {
6862 xoperands[1] = gen_label_rtx ();
6863 output_asm_insn ("ldo %0-%1(%%r2),%%r2", xoperands);
6864 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
6865 CODE_LABEL_NUMBER (xoperands[1]));
6866 }
6867 else
6868 /* ??? This branch may not reach its target. */
6869 output_asm_insn ("nop\n\tb,n %0", xoperands);
6870 }
6871 else
6872 /* ??? This branch may not reach its target. */
6873 output_asm_insn ("b,n %0", xoperands);
6874
6875 /* Delete the jump. */
6876 PUT_CODE (NEXT_INSN (insn), NOTE);
6877 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6878 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6879
6880 return "";
6881 }
6882
6883 /* Return the attribute length of the indirect call instruction INSN.
6884 The length must match the code generated by output_indirect call.
6885 The returned length includes the delay slot. Currently, the delay
6886 slot of an indirect call sequence is not exposed and it is used by
6887 the sequence itself. */
6888
6889 int
attr_length_indirect_call(insn)6890 attr_length_indirect_call (insn)
6891 rtx insn;
6892 {
6893 unsigned long distance = -1;
6894
6895 if (INSN_ADDRESSES_SET_P ())
6896 {
6897 distance = (total_code_bytes + insn_current_reference_address (insn));
6898 if (distance < total_code_bytes)
6899 distance = -1;
6900 }
6901
6902 if (TARGET_64BIT)
6903 return 12;
6904
6905 if (TARGET_FAST_INDIRECT_CALLS
6906 || (!TARGET_PORTABLE_RUNTIME
6907 && ((TARGET_PA_20 && distance < 7600000) || distance < 240000)))
6908 return 8;
6909
6910 if (flag_pic)
6911 return 24;
6912
6913 if (TARGET_PORTABLE_RUNTIME)
6914 return 20;
6915
6916 /* Out of reach, can use ble. */
6917 return 12;
6918 }
6919
6920 const char *
output_indirect_call(insn,call_dest)6921 output_indirect_call (insn, call_dest)
6922 rtx insn;
6923 rtx call_dest;
6924 {
6925 rtx xoperands[1];
6926
6927 if (TARGET_64BIT)
6928 {
6929 xoperands[0] = call_dest;
6930 output_asm_insn ("ldd 16(%0),%%r2", xoperands);
6931 output_asm_insn ("bve,l (%%r2),%%r2\n\tldd 24(%0),%%r27", xoperands);
6932 return "";
6933 }
6934
6935 /* First the special case for kernels, level 0 systems, etc. */
6936 if (TARGET_FAST_INDIRECT_CALLS)
6937 return "ble 0(%%sr4,%%r22)\n\tcopy %%r31,%%r2";
6938
6939 /* Now the normal case -- we can reach $$dyncall directly or
6940 we're sure that we can get there via a long-branch stub.
6941
6942 No need to check target flags as the length uniquely identifies
6943 the remaining cases. */
6944 if (attr_length_indirect_call (insn) == 8)
6945 {
6946 /* The HP linker substitutes a BLE for millicode calls using
6947 the short PIC PCREL form. Thus, we must use %r31 as the
6948 link register when generating PA 1.x code. */
6949 if (TARGET_PA_20)
6950 return ".CALL\tARGW0=GR\n\tb,l $$dyncall,%%r2\n\tcopy %%r2,%%r31";
6951 else
6952 return ".CALL\tARGW0=GR\n\tbl $$dyncall,%%r31\n\tcopy %%r31,%%r2";
6953 }
6954
6955 /* Long millicode call, but we are not generating PIC or portable runtime
6956 code. */
6957 if (attr_length_indirect_call (insn) == 12)
6958 return ".CALL\tARGW0=GR\n\tldil L'$$dyncall,%%r2\n\tble R'$$dyncall(%%sr4,%%r2)\n\tcopy %%r31,%%r2";
6959
6960 /* Long millicode call for portable runtime. */
6961 if (attr_length_indirect_call (insn) == 20)
6962 return "ldil L'$$dyncall,%%r31\n\tldo R'$$dyncall(%%r31),%%r31\n\tblr %%r0,%%r2\n\tbv,n %%r0(%%r31)\n\tnop";
6963
6964 /* We need a long PIC call to $$dyncall. */
6965 xoperands[0] = NULL_RTX;
6966 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6967 if (TARGET_SOM || !TARGET_GAS)
6968 {
6969 xoperands[0] = gen_label_rtx ();
6970 output_asm_insn ("addil L'$$dyncall-%0,%%r1", xoperands);
6971 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
6972 CODE_LABEL_NUMBER (xoperands[0]));
6973 output_asm_insn ("ldo R'$$dyncall-%0(%%r1),%%r1", xoperands);
6974 }
6975 else
6976 {
6977 output_asm_insn ("addil L'$$dyncall-$PIC_pcrel$0+4,%%r1", xoperands);
6978 output_asm_insn ("ldo R'$$dyncall-$PIC_pcrel$0+8(%%r1),%%r1",
6979 xoperands);
6980 }
6981 output_asm_insn ("blr %%r0,%%r2", xoperands);
6982 output_asm_insn ("bv,n %%r0(%%r1)\n\tnop", xoperands);
6983 return "";
6984 }
6985
6986 /* Return the total length of the save and restore instructions needed for
6987 the data linkage table pointer (i.e., the PIC register) across the call instruction INSN. No-return calls do not require a save and restore. In addition, we may be able to avoid the save and restore for calls within the same translation unit. */
6988
6989 int
attr_length_save_restore_dltp(insn)6990 attr_length_save_restore_dltp (insn)
6991 rtx insn;
6992 {
6993 if (find_reg_note (insn, REG_NORETURN, NULL_RTX))
6994 return 0;
6995
6996 return 8;
6997 }
6998
6999 /* In HPUX 8.0's shared library scheme, special relocations are needed
7000 for function labels if they might be passed to a function
7001 in a shared library (because shared libraries don't live in code
7002 space), and special magic is needed to construct their address. */
7003
7004 void
hppa_encode_label(sym)7005 hppa_encode_label (sym)
7006 rtx sym;
7007 {
7008 const char *str = XSTR (sym, 0);
7009 int len = strlen (str) + 1;
7010 char *newstr, *p;
7011
7012 p = newstr = alloca (len + 1);
7013 *p++ = '@';
7014 strcpy (p, str);
7015
7016 XSTR (sym, 0) = ggc_alloc_string (newstr, len);
7017 }
7018
7019 static void
pa_encode_section_info(decl,first)7020 pa_encode_section_info (decl, first)
7021 tree decl;
7022 int first;
7023 {
7024 if (first && TEXT_SPACE_P (decl))
7025 {
7026 rtx rtl;
7027 if (TREE_CODE (decl) == FUNCTION_DECL
7028 || TREE_CODE (decl) == VAR_DECL)
7029 rtl = DECL_RTL (decl);
7030 else
7031 rtl = TREE_CST_RTL (decl);
7032 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
7033 if (TREE_CODE (decl) == FUNCTION_DECL)
7034 hppa_encode_label (XEXP (DECL_RTL (decl), 0));
7035 }
7036 }
7037
7038 /* This is sort of inverse to pa_encode_section_info. */
7039
7040 static const char *
pa_strip_name_encoding(str)7041 pa_strip_name_encoding (str)
7042 const char *str;
7043 {
7044 str += (*str == '@');
7045 str += (*str == '*');
7046 return str;
7047 }
7048
7049 int
function_label_operand(op,mode)7050 function_label_operand (op, mode)
7051 rtx op;
7052 enum machine_mode mode ATTRIBUTE_UNUSED;
7053 {
7054 return GET_CODE (op) == SYMBOL_REF && FUNCTION_NAME_P (XSTR (op, 0));
7055 }
7056
7057 /* Returns 1 if OP is a function label involved in a simple addition
7058 with a constant. Used to keep certain patterns from matching
7059 during instruction combination. */
7060 int
is_function_label_plus_const(op)7061 is_function_label_plus_const (op)
7062 rtx op;
7063 {
7064 /* Strip off any CONST. */
7065 if (GET_CODE (op) == CONST)
7066 op = XEXP (op, 0);
7067
7068 return (GET_CODE (op) == PLUS
7069 && function_label_operand (XEXP (op, 0), Pmode)
7070 && GET_CODE (XEXP (op, 1)) == CONST_INT);
7071 }
7072
7073 /* Output assembly code for a thunk to FUNCTION. */
7074
7075 static void
pa_asm_output_mi_thunk(file,thunk_fndecl,delta,vcall_offset,function)7076 pa_asm_output_mi_thunk (file, thunk_fndecl, delta, vcall_offset, function)
7077 FILE *file;
7078 tree thunk_fndecl;
7079 HOST_WIDE_INT delta;
7080 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED;
7081 tree function;
7082 {
7083 const char *target_name = XSTR (XEXP (DECL_RTL (function), 0), 0);
7084 static unsigned int current_thunk_number;
7085 char label[16];
7086 const char *lab;
7087 ASM_GENERATE_INTERNAL_LABEL (label, "LTHN", current_thunk_number);
7088 lab = (*targetm.strip_name_encoding) (label);
7089 target_name = (*targetm.strip_name_encoding) (target_name);
7090 /* FIXME: total_code_bytes is not handled correctly in files with
7091 mi thunks. */
7092 pa_output_function_prologue (file, 0);
7093 if (VAL_14_BITS_P (delta))
7094 {
7095 if (!TARGET_64BIT && !TARGET_PORTABLE_RUNTIME && flag_pic)
7096 {
7097 fprintf (file, "\taddil LT'%s,%%r19\n", lab);
7098 fprintf (file, "\tldw RT'%s(%%r1),%%r22\n", lab);
7099 fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n");
7100 fprintf (file, "\tbb,>=,n %%r22,30,.+16\n");
7101 fprintf (file, "\tdepi 0,31,2,%%r22\n");
7102 fprintf (file, "\tldw 4(%%sr0,%%r22),%%r19\n");
7103 fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n");
7104 if (TARGET_NO_SPACE_REGS)
7105 fprintf (file, "\tbe 0(%%sr4,%%r22)\n\tldo ");
7106 else
7107 {
7108 fprintf (file, "\tldsid (%%sr0,%%r22),%%r1\n");
7109 fprintf (file, "\tmtsp %%r1,%%sr0\n");
7110 fprintf (file, "\tbe 0(%%sr0,%%r22)\n\tldo ");
7111 }
7112 fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta);
7113 fprintf (file, "(%%r26),%%r26\n");
7114 }
7115 else
7116 {
7117 fprintf (file, "\tb %s\n\tldo ", target_name);
7118 fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta);
7119 fprintf (file, "(%%r26),%%r26\n");
7120 }
7121 }
7122 else
7123 {
7124 if (!TARGET_64BIT && !TARGET_PORTABLE_RUNTIME && flag_pic)
7125 {
7126 fprintf (file, "\taddil L'");
7127 fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta);
7128 fprintf (file, ",%%r26\n\tldo R'");
7129 fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta);
7130 fprintf (file, "(%%r1),%%r26\n");
7131 fprintf (file, "\taddil LT'%s,%%r19\n", lab);
7132 fprintf (file, "\tldw RT'%s(%%r1),%%r22\n", lab);
7133 fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n");
7134 fprintf (file, "\tbb,>=,n %%r22,30,.+16\n");
7135 fprintf (file, "\tdepi 0,31,2,%%r22\n");
7136 fprintf (file, "\tldw 4(%%sr0,%%r22),%%r19\n");
7137 fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n");
7138 if (TARGET_NO_SPACE_REGS)
7139 fprintf (file, "\tbe 0(%%sr4,%%r22)");
7140 else
7141 {
7142 fprintf (file, "\tldsid (%%sr0,%%r22),%%r1\n");
7143 fprintf (file, "\tmtsp %%r1,%%sr0\n");
7144 fprintf (file, "\tbe,n 0(%%sr0,%%r22)\n");
7145 }
7146 }
7147 else
7148 {
7149 fprintf (file, "\taddil L'");
7150 fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta);
7151 fprintf (file, ",%%r26\n\tb %s\n\tldo R'", target_name);
7152 fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta);
7153 fprintf (file, "(%%r1),%%r26\n");
7154 }
7155 }
7156
7157 fprintf (file, "\t.EXIT\n\t.PROCEND\n");
7158 if (! TARGET_64BIT && ! TARGET_PORTABLE_RUNTIME && flag_pic)
7159 {
7160 data_section ();
7161 fprintf (file, "\t.align 4\n");
7162 ASM_OUTPUT_INTERNAL_LABEL (file, "LTHN", current_thunk_number);
7163 fprintf (file, "\t.word P'%s\n", target_name);
7164 function_section (thunk_fndecl);
7165 }
7166 current_thunk_number++;
7167 }
7168
7169 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
7170 use in fmpyadd instructions. */
7171 int
fmpyaddoperands(operands)7172 fmpyaddoperands (operands)
7173 rtx *operands;
7174 {
7175 enum machine_mode mode = GET_MODE (operands[0]);
7176
7177 /* Must be a floating point mode. */
7178 if (mode != SFmode && mode != DFmode)
7179 return 0;
7180
7181 /* All modes must be the same. */
7182 if (! (mode == GET_MODE (operands[1])
7183 && mode == GET_MODE (operands[2])
7184 && mode == GET_MODE (operands[3])
7185 && mode == GET_MODE (operands[4])
7186 && mode == GET_MODE (operands[5])))
7187 return 0;
7188
7189 /* All operands must be registers. */
7190 if (! (GET_CODE (operands[1]) == REG
7191 && GET_CODE (operands[2]) == REG
7192 && GET_CODE (operands[3]) == REG
7193 && GET_CODE (operands[4]) == REG
7194 && GET_CODE (operands[5]) == REG))
7195 return 0;
7196
7197 /* Only 2 real operands to the addition. One of the input operands must
7198 be the same as the output operand. */
7199 if (! rtx_equal_p (operands[3], operands[4])
7200 && ! rtx_equal_p (operands[3], operands[5]))
7201 return 0;
7202
7203 /* Inout operand of add can not conflict with any operands from multiply. */
7204 if (rtx_equal_p (operands[3], operands[0])
7205 || rtx_equal_p (operands[3], operands[1])
7206 || rtx_equal_p (operands[3], operands[2]))
7207 return 0;
7208
7209 /* multiply can not feed into addition operands. */
7210 if (rtx_equal_p (operands[4], operands[0])
7211 || rtx_equal_p (operands[5], operands[0]))
7212 return 0;
7213
7214 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
7215 if (mode == SFmode
7216 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
7217 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
7218 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
7219 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
7220 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
7221 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
7222 return 0;
7223
7224 /* Passed. Operands are suitable for fmpyadd. */
7225 return 1;
7226 }
7227
7228 #if !defined(USE_COLLECT2)
7229 static void
pa_asm_out_constructor(symbol,priority)7230 pa_asm_out_constructor (symbol, priority)
7231 rtx symbol;
7232 int priority;
7233 {
7234 if (!function_label_operand (symbol, VOIDmode))
7235 hppa_encode_label (symbol);
7236
7237 #ifdef CTORS_SECTION_ASM_OP
7238 default_ctor_section_asm_out_constructor (symbol, priority);
7239 #else
7240 # ifdef TARGET_ASM_NAMED_SECTION
7241 default_named_section_asm_out_constructor (symbol, priority);
7242 # else
7243 default_stabs_asm_out_constructor (symbol, priority);
7244 # endif
7245 #endif
7246 }
7247
7248 static void
pa_asm_out_destructor(symbol,priority)7249 pa_asm_out_destructor (symbol, priority)
7250 rtx symbol;
7251 int priority;
7252 {
7253 if (!function_label_operand (symbol, VOIDmode))
7254 hppa_encode_label (symbol);
7255
7256 #ifdef DTORS_SECTION_ASM_OP
7257 default_dtor_section_asm_out_destructor (symbol, priority);
7258 #else
7259 # ifdef TARGET_ASM_NAMED_SECTION
7260 default_named_section_asm_out_destructor (symbol, priority);
7261 # else
7262 default_stabs_asm_out_destructor (symbol, priority);
7263 # endif
7264 #endif
7265 }
7266 #endif
7267
7268 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
7269 use in fmpysub instructions. */
7270 int
fmpysuboperands(operands)7271 fmpysuboperands (operands)
7272 rtx *operands;
7273 {
7274 enum machine_mode mode = GET_MODE (operands[0]);
7275
7276 /* Must be a floating point mode. */
7277 if (mode != SFmode && mode != DFmode)
7278 return 0;
7279
7280 /* All modes must be the same. */
7281 if (! (mode == GET_MODE (operands[1])
7282 && mode == GET_MODE (operands[2])
7283 && mode == GET_MODE (operands[3])
7284 && mode == GET_MODE (operands[4])
7285 && mode == GET_MODE (operands[5])))
7286 return 0;
7287
7288 /* All operands must be registers. */
7289 if (! (GET_CODE (operands[1]) == REG
7290 && GET_CODE (operands[2]) == REG
7291 && GET_CODE (operands[3]) == REG
7292 && GET_CODE (operands[4]) == REG
7293 && GET_CODE (operands[5]) == REG))
7294 return 0;
7295
7296 /* Only 2 real operands to the subtraction. Subtraction is not a commutative
7297 operation, so operands[4] must be the same as operand[3]. */
7298 if (! rtx_equal_p (operands[3], operands[4]))
7299 return 0;
7300
7301 /* multiply can not feed into subtraction. */
7302 if (rtx_equal_p (operands[5], operands[0]))
7303 return 0;
7304
7305 /* Inout operand of sub can not conflict with any operands from multiply. */
7306 if (rtx_equal_p (operands[3], operands[0])
7307 || rtx_equal_p (operands[3], operands[1])
7308 || rtx_equal_p (operands[3], operands[2]))
7309 return 0;
7310
7311 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
7312 if (mode == SFmode
7313 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
7314 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
7315 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
7316 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
7317 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
7318 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
7319 return 0;
7320
7321 /* Passed. Operands are suitable for fmpysub. */
7322 return 1;
7323 }
7324
7325 int
plus_xor_ior_operator(op,mode)7326 plus_xor_ior_operator (op, mode)
7327 rtx op;
7328 enum machine_mode mode ATTRIBUTE_UNUSED;
7329 {
7330 return (GET_CODE (op) == PLUS || GET_CODE (op) == XOR
7331 || GET_CODE (op) == IOR);
7332 }
7333
7334 /* Return 1 if the given constant is 2, 4, or 8. These are the valid
7335 constants for shadd instructions. */
7336 static int
shadd_constant_p(val)7337 shadd_constant_p (val)
7338 int val;
7339 {
7340 if (val == 2 || val == 4 || val == 8)
7341 return 1;
7342 else
7343 return 0;
7344 }
7345
7346 /* Return 1 if OP is a CONST_INT with the value 2, 4, or 8. These are
7347 the valid constant for shadd instructions. */
7348 int
shadd_operand(op,mode)7349 shadd_operand (op, mode)
7350 rtx op;
7351 enum machine_mode mode ATTRIBUTE_UNUSED;
7352 {
7353 return (GET_CODE (op) == CONST_INT && shadd_constant_p (INTVAL (op)));
7354 }
7355
7356 /* Return 1 if OP is valid as a base register in a reg + reg address. */
7357
7358 int
basereg_operand(op,mode)7359 basereg_operand (op, mode)
7360 rtx op;
7361 enum machine_mode mode;
7362 {
7363 /* cse will create some unscaled indexed addresses, however; it
7364 generally isn't a win on the PA, so avoid creating unscaled
7365 indexed addresses until after cse is finished. */
7366 if (!cse_not_expected)
7367 return 0;
7368
7369 /* Allow any register when TARGET_NO_SPACE_REGS is in effect since
7370 we don't have to worry about the braindamaged implicit space
7371 register selection from the basereg. */
7372 if (TARGET_NO_SPACE_REGS)
7373 return (GET_CODE (op) == REG);
7374
7375 /* While it's always safe to index off the frame pointer, it's not
7376 always profitable, particularly when the frame pointer is being
7377 eliminated. */
7378 if (! flag_omit_frame_pointer && op == frame_pointer_rtx)
7379 return 1;
7380
7381 return (GET_CODE (op) == REG
7382 && REG_POINTER (op)
7383 && register_operand (op, mode));
7384 }
7385
7386 /* Return 1 if this operand is anything other than a hard register. */
7387
7388 int
non_hard_reg_operand(op,mode)7389 non_hard_reg_operand (op, mode)
7390 rtx op;
7391 enum machine_mode mode ATTRIBUTE_UNUSED;
7392 {
7393 return ! (GET_CODE (op) == REG && REGNO (op) < FIRST_PSEUDO_REGISTER);
7394 }
7395
7396 /* Return 1 if INSN branches forward. Should be using insn_addresses
7397 to avoid walking through all the insns... */
7398 static int
forward_branch_p(insn)7399 forward_branch_p (insn)
7400 rtx insn;
7401 {
7402 rtx label = JUMP_LABEL (insn);
7403
7404 while (insn)
7405 {
7406 if (insn == label)
7407 break;
7408 else
7409 insn = NEXT_INSN (insn);
7410 }
7411
7412 return (insn == label);
7413 }
7414
7415 /* Return 1 if OP is an equality comparison, else return 0. */
7416 int
eq_neq_comparison_operator(op,mode)7417 eq_neq_comparison_operator (op, mode)
7418 rtx op;
7419 enum machine_mode mode ATTRIBUTE_UNUSED;
7420 {
7421 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
7422 }
7423
7424 /* Return 1 if OP is an operator suitable for use in a movb instruction. */
7425 int
movb_comparison_operator(op,mode)7426 movb_comparison_operator (op, mode)
7427 rtx op;
7428 enum machine_mode mode ATTRIBUTE_UNUSED;
7429 {
7430 return (GET_CODE (op) == EQ || GET_CODE (op) == NE
7431 || GET_CODE (op) == LT || GET_CODE (op) == GE);
7432 }
7433
7434 /* Return 1 if INSN is in the delay slot of a call instruction. */
7435 int
jump_in_call_delay(insn)7436 jump_in_call_delay (insn)
7437 rtx insn;
7438 {
7439
7440 if (GET_CODE (insn) != JUMP_INSN)
7441 return 0;
7442
7443 if (PREV_INSN (insn)
7444 && PREV_INSN (PREV_INSN (insn))
7445 && GET_CODE (next_real_insn (PREV_INSN (PREV_INSN (insn)))) == INSN)
7446 {
7447 rtx test_insn = next_real_insn (PREV_INSN (PREV_INSN (insn)));
7448
7449 return (GET_CODE (PATTERN (test_insn)) == SEQUENCE
7450 && XVECEXP (PATTERN (test_insn), 0, 1) == insn);
7451
7452 }
7453 else
7454 return 0;
7455 }
7456
7457 /* Output an unconditional move and branch insn. */
7458
7459 const char *
output_parallel_movb(operands,length)7460 output_parallel_movb (operands, length)
7461 rtx *operands;
7462 int length;
7463 {
7464 /* These are the cases in which we win. */
7465 if (length == 4)
7466 return "mov%I1b,tr %1,%0,%2";
7467
7468 /* None of these cases wins, but they don't lose either. */
7469 if (dbr_sequence_length () == 0)
7470 {
7471 /* Nothing in the delay slot, fake it by putting the combined
7472 insn (the copy or add) in the delay slot of a bl. */
7473 if (GET_CODE (operands[1]) == CONST_INT)
7474 return "b %2\n\tldi %1,%0";
7475 else
7476 return "b %2\n\tcopy %1,%0";
7477 }
7478 else
7479 {
7480 /* Something in the delay slot, but we've got a long branch. */
7481 if (GET_CODE (operands[1]) == CONST_INT)
7482 return "ldi %1,%0\n\tb %2";
7483 else
7484 return "copy %1,%0\n\tb %2";
7485 }
7486 }
7487
7488 /* Output an unconditional add and branch insn. */
7489
7490 const char *
output_parallel_addb(operands,length)7491 output_parallel_addb (operands, length)
7492 rtx *operands;
7493 int length;
7494 {
7495 /* To make life easy we want operand0 to be the shared input/output
7496 operand and operand1 to be the readonly operand. */
7497 if (operands[0] == operands[1])
7498 operands[1] = operands[2];
7499
7500 /* These are the cases in which we win. */
7501 if (length == 4)
7502 return "add%I1b,tr %1,%0,%3";
7503
7504 /* None of these cases win, but they don't lose either. */
7505 if (dbr_sequence_length () == 0)
7506 {
7507 /* Nothing in the delay slot, fake it by putting the combined
7508 insn (the copy or add) in the delay slot of a bl. */
7509 return "b %3\n\tadd%I1 %1,%0,%0";
7510 }
7511 else
7512 {
7513 /* Something in the delay slot, but we've got a long branch. */
7514 return "add%I1 %1,%0,%0\n\tb %3";
7515 }
7516 }
7517
7518 /* Return nonzero if INSN (a jump insn) immediately follows a call
7519 to a named function. This is used to avoid filling the delay slot
7520 of the jump since it can usually be eliminated by modifying RP in
7521 the delay slot of the call. */
7522
7523 int
following_call(insn)7524 following_call (insn)
7525 rtx insn;
7526 {
7527 if (! TARGET_JUMP_IN_DELAY)
7528 return 0;
7529
7530 /* Find the previous real insn, skipping NOTEs. */
7531 insn = PREV_INSN (insn);
7532 while (insn && GET_CODE (insn) == NOTE)
7533 insn = PREV_INSN (insn);
7534
7535 /* Check for CALL_INSNs and millicode calls. */
7536 if (insn
7537 && ((GET_CODE (insn) == CALL_INSN
7538 && get_attr_type (insn) != TYPE_DYNCALL)
7539 || (GET_CODE (insn) == INSN
7540 && GET_CODE (PATTERN (insn)) != SEQUENCE
7541 && GET_CODE (PATTERN (insn)) != USE
7542 && GET_CODE (PATTERN (insn)) != CLOBBER
7543 && get_attr_type (insn) == TYPE_MILLI)))
7544 return 1;
7545
7546 return 0;
7547 }
7548
7549 /* We use this hook to perform a PA specific optimization which is difficult
7550 to do in earlier passes.
7551
7552 We want the delay slots of branches within jump tables to be filled.
7553 None of the compiler passes at the moment even has the notion that a
7554 PA jump table doesn't contain addresses, but instead contains actual
7555 instructions!
7556
7557 Because we actually jump into the table, the addresses of each entry
7558 must stay constant in relation to the beginning of the table (which
7559 itself must stay constant relative to the instruction to jump into
7560 it). I don't believe we can guarantee earlier passes of the compiler
7561 will adhere to those rules.
7562
7563 So, late in the compilation process we find all the jump tables, and
7564 expand them into real code -- eg each entry in the jump table vector
7565 will get an appropriate label followed by a jump to the final target.
7566
7567 Reorg and the final jump pass can then optimize these branches and
7568 fill their delay slots. We end up with smaller, more efficient code.
7569
7570 The jump instructions within the table are special; we must be able
7571 to identify them during assembly output (if the jumps don't get filled
7572 we need to emit a nop rather than nullifying the delay slot)). We
7573 identify jumps in switch tables by marking the SET with DImode.
7574
7575 We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB
7576 insns. This serves two purposes, first it prevents jump.c from
7577 noticing that the last N entries in the table jump to the instruction
7578 immediately after the table and deleting the jumps. Second, those
7579 insns mark where we should emit .begin_brtab and .end_brtab directives
7580 when using GAS (allows for better link time optimizations). */
7581
7582 void
pa_reorg(insns)7583 pa_reorg (insns)
7584 rtx insns;
7585 {
7586 rtx insn;
7587
7588 remove_useless_addtr_insns (insns, 1);
7589
7590 if (pa_cpu < PROCESSOR_8000)
7591 pa_combine_instructions (get_insns ());
7592
7593
7594 /* This is fairly cheap, so always run it if optimizing. */
7595 if (optimize > 0 && !TARGET_BIG_SWITCH)
7596 {
7597 /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns. */
7598 insns = get_insns ();
7599 for (insn = insns; insn; insn = NEXT_INSN (insn))
7600 {
7601 rtx pattern, tmp, location;
7602 unsigned int length, i;
7603
7604 /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode. */
7605 if (GET_CODE (insn) != JUMP_INSN
7606 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
7607 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
7608 continue;
7609
7610 /* Emit marker for the beginning of the branch table. */
7611 emit_insn_before (gen_begin_brtab (), insn);
7612
7613 pattern = PATTERN (insn);
7614 location = PREV_INSN (insn);
7615 length = XVECLEN (pattern, GET_CODE (pattern) == ADDR_DIFF_VEC);
7616
7617 for (i = 0; i < length; i++)
7618 {
7619 /* Emit a label before each jump to keep jump.c from
7620 removing this code. */
7621 tmp = gen_label_rtx ();
7622 LABEL_NUSES (tmp) = 1;
7623 emit_label_after (tmp, location);
7624 location = NEXT_INSN (location);
7625
7626 if (GET_CODE (pattern) == ADDR_VEC)
7627 {
7628 /* Emit the jump itself. */
7629 tmp = gen_jump (XEXP (XVECEXP (pattern, 0, i), 0));
7630 tmp = emit_jump_insn_after (tmp, location);
7631 JUMP_LABEL (tmp) = XEXP (XVECEXP (pattern, 0, i), 0);
7632 /* It is easy to rely on the branch table markers
7633 during assembly output to trigger the correct code
7634 for a switch table jump with an unfilled delay slot,
7635
7636 However, that requires state and assumes that we look
7637 at insns in order.
7638
7639 We can't make such assumptions when computing the length
7640 of instructions. Ugh. We could walk the insn chain to
7641 determine if this instruction is in a branch table, but
7642 that can get rather expensive, particularly during the
7643 branch shortening phase of the compiler.
7644
7645 So instead we mark this jump as being special. This is
7646 far from ideal and knows that no code after this will
7647 muck around with the mode of the JUMP_INSN itself. */
7648 PUT_MODE (tmp, SImode);
7649 LABEL_NUSES (JUMP_LABEL (tmp))++;
7650 location = NEXT_INSN (location);
7651 }
7652 else
7653 {
7654 /* Emit the jump itself. */
7655 tmp = gen_jump (XEXP (XVECEXP (pattern, 1, i), 0));
7656 tmp = emit_jump_insn_after (tmp, location);
7657 JUMP_LABEL (tmp) = XEXP (XVECEXP (pattern, 1, i), 0);
7658 /* It is easy to rely on the branch table markers
7659 during assembly output to trigger the correct code
7660 for a switch table jump with an unfilled delay slot,
7661
7662 However, that requires state and assumes that we look
7663 at insns in order.
7664
7665 We can't make such assumptions when computing the length
7666 of instructions. Ugh. We could walk the insn chain to
7667 determine if this instruction is in a branch table, but
7668 that can get rather expensive, particularly during the
7669 branch shortening phase of the compiler.
7670
7671 So instead we mark this jump as being special. This is
7672 far from ideal and knows that no code after this will
7673 muck around with the mode of the JUMP_INSN itself. */
7674 PUT_MODE (tmp, SImode);
7675 LABEL_NUSES (JUMP_LABEL (tmp))++;
7676 location = NEXT_INSN (location);
7677 }
7678
7679 /* Emit a BARRIER after the jump. */
7680 emit_barrier_after (location);
7681 location = NEXT_INSN (location);
7682 }
7683
7684 /* Emit marker for the end of the branch table. */
7685 emit_insn_before (gen_end_brtab (), location);
7686 location = NEXT_INSN (location);
7687 emit_barrier_after (location);
7688
7689 /* Delete the ADDR_VEC or ADDR_DIFF_VEC. */
7690 delete_insn (insn);
7691 }
7692 }
7693 else
7694 {
7695 /* Sill need an end_brtab insn. */
7696 insns = get_insns ();
7697 for (insn = insns; insn; insn = NEXT_INSN (insn))
7698 {
7699 /* Find an ADDR_VEC insn. */
7700 if (GET_CODE (insn) != JUMP_INSN
7701 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
7702 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
7703 continue;
7704
7705 /* Now generate markers for the beginning and end of the
7706 branch table. */
7707 emit_insn_before (gen_begin_brtab (), insn);
7708 emit_insn_after (gen_end_brtab (), insn);
7709 }
7710 }
7711 }
7712
7713 /* The PA has a number of odd instructions which can perform multiple
7714 tasks at once. On first generation PA machines (PA1.0 and PA1.1)
7715 it may be profitable to combine two instructions into one instruction
7716 with two outputs. It's not profitable PA2.0 machines because the
7717 two outputs would take two slots in the reorder buffers.
7718
7719 This routine finds instructions which can be combined and combines
7720 them. We only support some of the potential combinations, and we
7721 only try common ways to find suitable instructions.
7722
7723 * addb can add two registers or a register and a small integer
7724 and jump to a nearby (+-8k) location. Normally the jump to the
7725 nearby location is conditional on the result of the add, but by
7726 using the "true" condition we can make the jump unconditional.
7727 Thus addb can perform two independent operations in one insn.
7728
7729 * movb is similar to addb in that it can perform a reg->reg
7730 or small immediate->reg copy and jump to a nearby (+-8k location).
7731
7732 * fmpyadd and fmpysub can perform a FP multiply and either an
7733 FP add or FP sub if the operands of the multiply and add/sub are
7734 independent (there are other minor restrictions). Note both
7735 the fmpy and fadd/fsub can in theory move to better spots according
7736 to data dependencies, but for now we require the fmpy stay at a
7737 fixed location.
7738
7739 * Many of the memory operations can perform pre & post updates
7740 of index registers. GCC's pre/post increment/decrement addressing
7741 is far too simple to take advantage of all the possibilities. This
7742 pass may not be suitable since those insns may not be independent.
7743
7744 * comclr can compare two ints or an int and a register, nullify
7745 the following instruction and zero some other register. This
7746 is more difficult to use as it's harder to find an insn which
7747 will generate a comclr than finding something like an unconditional
7748 branch. (conditional moves & long branches create comclr insns).
7749
7750 * Most arithmetic operations can conditionally skip the next
7751 instruction. They can be viewed as "perform this operation
7752 and conditionally jump to this nearby location" (where nearby
7753 is an insns away). These are difficult to use due to the
7754 branch length restrictions. */
7755
7756 static void
pa_combine_instructions(insns)7757 pa_combine_instructions (insns)
7758 rtx insns ATTRIBUTE_UNUSED;
7759 {
7760 rtx anchor, new;
7761
7762 /* This can get expensive since the basic algorithm is on the
7763 order of O(n^2) (or worse). Only do it for -O2 or higher
7764 levels of optimization. */
7765 if (optimize < 2)
7766 return;
7767
7768 /* Walk down the list of insns looking for "anchor" insns which
7769 may be combined with "floating" insns. As the name implies,
7770 "anchor" instructions don't move, while "floating" insns may
7771 move around. */
7772 new = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, NULL_RTX, NULL_RTX));
7773 new = make_insn_raw (new);
7774
7775 for (anchor = get_insns (); anchor; anchor = NEXT_INSN (anchor))
7776 {
7777 enum attr_pa_combine_type anchor_attr;
7778 enum attr_pa_combine_type floater_attr;
7779
7780 /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs.
7781 Also ignore any special USE insns. */
7782 if ((GET_CODE (anchor) != INSN
7783 && GET_CODE (anchor) != JUMP_INSN
7784 && GET_CODE (anchor) != CALL_INSN)
7785 || GET_CODE (PATTERN (anchor)) == USE
7786 || GET_CODE (PATTERN (anchor)) == CLOBBER
7787 || GET_CODE (PATTERN (anchor)) == ADDR_VEC
7788 || GET_CODE (PATTERN (anchor)) == ADDR_DIFF_VEC)
7789 continue;
7790
7791 anchor_attr = get_attr_pa_combine_type (anchor);
7792 /* See if anchor is an insn suitable for combination. */
7793 if (anchor_attr == PA_COMBINE_TYPE_FMPY
7794 || anchor_attr == PA_COMBINE_TYPE_FADDSUB
7795 || (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
7796 && ! forward_branch_p (anchor)))
7797 {
7798 rtx floater;
7799
7800 for (floater = PREV_INSN (anchor);
7801 floater;
7802 floater = PREV_INSN (floater))
7803 {
7804 if (GET_CODE (floater) == NOTE
7805 || (GET_CODE (floater) == INSN
7806 && (GET_CODE (PATTERN (floater)) == USE
7807 || GET_CODE (PATTERN (floater)) == CLOBBER)))
7808 continue;
7809
7810 /* Anything except a regular INSN will stop our search. */
7811 if (GET_CODE (floater) != INSN
7812 || GET_CODE (PATTERN (floater)) == ADDR_VEC
7813 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
7814 {
7815 floater = NULL_RTX;
7816 break;
7817 }
7818
7819 /* See if FLOATER is suitable for combination with the
7820 anchor. */
7821 floater_attr = get_attr_pa_combine_type (floater);
7822 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
7823 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
7824 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
7825 && floater_attr == PA_COMBINE_TYPE_FMPY))
7826 {
7827 /* If ANCHOR and FLOATER can be combined, then we're
7828 done with this pass. */
7829 if (pa_can_combine_p (new, anchor, floater, 0,
7830 SET_DEST (PATTERN (floater)),
7831 XEXP (SET_SRC (PATTERN (floater)), 0),
7832 XEXP (SET_SRC (PATTERN (floater)), 1)))
7833 break;
7834 }
7835
7836 else if (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
7837 && floater_attr == PA_COMBINE_TYPE_ADDMOVE)
7838 {
7839 if (GET_CODE (SET_SRC (PATTERN (floater))) == PLUS)
7840 {
7841 if (pa_can_combine_p (new, anchor, floater, 0,
7842 SET_DEST (PATTERN (floater)),
7843 XEXP (SET_SRC (PATTERN (floater)), 0),
7844 XEXP (SET_SRC (PATTERN (floater)), 1)))
7845 break;
7846 }
7847 else
7848 {
7849 if (pa_can_combine_p (new, anchor, floater, 0,
7850 SET_DEST (PATTERN (floater)),
7851 SET_SRC (PATTERN (floater)),
7852 SET_SRC (PATTERN (floater))))
7853 break;
7854 }
7855 }
7856 }
7857
7858 /* If we didn't find anything on the backwards scan try forwards. */
7859 if (!floater
7860 && (anchor_attr == PA_COMBINE_TYPE_FMPY
7861 || anchor_attr == PA_COMBINE_TYPE_FADDSUB))
7862 {
7863 for (floater = anchor; floater; floater = NEXT_INSN (floater))
7864 {
7865 if (GET_CODE (floater) == NOTE
7866 || (GET_CODE (floater) == INSN
7867 && (GET_CODE (PATTERN (floater)) == USE
7868 || GET_CODE (PATTERN (floater)) == CLOBBER)))
7869
7870 continue;
7871
7872 /* Anything except a regular INSN will stop our search. */
7873 if (GET_CODE (floater) != INSN
7874 || GET_CODE (PATTERN (floater)) == ADDR_VEC
7875 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
7876 {
7877 floater = NULL_RTX;
7878 break;
7879 }
7880
7881 /* See if FLOATER is suitable for combination with the
7882 anchor. */
7883 floater_attr = get_attr_pa_combine_type (floater);
7884 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
7885 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
7886 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
7887 && floater_attr == PA_COMBINE_TYPE_FMPY))
7888 {
7889 /* If ANCHOR and FLOATER can be combined, then we're
7890 done with this pass. */
7891 if (pa_can_combine_p (new, anchor, floater, 1,
7892 SET_DEST (PATTERN (floater)),
7893 XEXP (SET_SRC (PATTERN (floater)),
7894 0),
7895 XEXP (SET_SRC (PATTERN (floater)),
7896 1)))
7897 break;
7898 }
7899 }
7900 }
7901
7902 /* FLOATER will be nonzero if we found a suitable floating
7903 insn for combination with ANCHOR. */
7904 if (floater
7905 && (anchor_attr == PA_COMBINE_TYPE_FADDSUB
7906 || anchor_attr == PA_COMBINE_TYPE_FMPY))
7907 {
7908 /* Emit the new instruction and delete the old anchor. */
7909 emit_insn_before (gen_rtx_PARALLEL
7910 (VOIDmode,
7911 gen_rtvec (2, PATTERN (anchor),
7912 PATTERN (floater))),
7913 anchor);
7914
7915 PUT_CODE (anchor, NOTE);
7916 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
7917 NOTE_SOURCE_FILE (anchor) = 0;
7918
7919 /* Emit a special USE insn for FLOATER, then delete
7920 the floating insn. */
7921 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
7922 delete_insn (floater);
7923
7924 continue;
7925 }
7926 else if (floater
7927 && anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH)
7928 {
7929 rtx temp;
7930 /* Emit the new_jump instruction and delete the old anchor. */
7931 temp
7932 = emit_jump_insn_before (gen_rtx_PARALLEL
7933 (VOIDmode,
7934 gen_rtvec (2, PATTERN (anchor),
7935 PATTERN (floater))),
7936 anchor);
7937
7938 JUMP_LABEL (temp) = JUMP_LABEL (anchor);
7939 PUT_CODE (anchor, NOTE);
7940 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
7941 NOTE_SOURCE_FILE (anchor) = 0;
7942
7943 /* Emit a special USE insn for FLOATER, then delete
7944 the floating insn. */
7945 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
7946 delete_insn (floater);
7947 continue;
7948 }
7949 }
7950 }
7951 }
7952
7953 static int
pa_can_combine_p(new,anchor,floater,reversed,dest,src1,src2)7954 pa_can_combine_p (new, anchor, floater, reversed, dest, src1, src2)
7955 rtx new, anchor, floater;
7956 int reversed;
7957 rtx dest, src1, src2;
7958 {
7959 int insn_code_number;
7960 rtx start, end;
7961
7962 /* Create a PARALLEL with the patterns of ANCHOR and
7963 FLOATER, try to recognize it, then test constraints
7964 for the resulting pattern.
7965
7966 If the pattern doesn't match or the constraints
7967 aren't met keep searching for a suitable floater
7968 insn. */
7969 XVECEXP (PATTERN (new), 0, 0) = PATTERN (anchor);
7970 XVECEXP (PATTERN (new), 0, 1) = PATTERN (floater);
7971 INSN_CODE (new) = -1;
7972 insn_code_number = recog_memoized (new);
7973 if (insn_code_number < 0
7974 || (extract_insn (new), ! constrain_operands (1)))
7975 return 0;
7976
7977 if (reversed)
7978 {
7979 start = anchor;
7980 end = floater;
7981 }
7982 else
7983 {
7984 start = floater;
7985 end = anchor;
7986 }
7987
7988 /* There's up to three operands to consider. One
7989 output and two inputs.
7990
7991 The output must not be used between FLOATER & ANCHOR
7992 exclusive. The inputs must not be set between
7993 FLOATER and ANCHOR exclusive. */
7994
7995 if (reg_used_between_p (dest, start, end))
7996 return 0;
7997
7998 if (reg_set_between_p (src1, start, end))
7999 return 0;
8000
8001 if (reg_set_between_p (src2, start, end))
8002 return 0;
8003
8004 /* If we get here, then everything is good. */
8005 return 1;
8006 }
8007
8008 /* Return nonzero if references for INSN are delayed.
8009
8010 Millicode insns are actually function calls with some special
8011 constraints on arguments and register usage.
8012
8013 Millicode calls always expect their arguments in the integer argument
8014 registers, and always return their result in %r29 (ret1). They
8015 are expected to clobber their arguments, %r1, %r29, and the return
8016 pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else.
8017
8018 This function tells reorg that the references to arguments and
8019 millicode calls do not appear to happen until after the millicode call.
8020 This allows reorg to put insns which set the argument registers into the
8021 delay slot of the millicode call -- thus they act more like traditional
8022 CALL_INSNs.
8023
8024 Note we can not consider side effects of the insn to be delayed because
8025 the branch and link insn will clobber the return pointer. If we happened
8026 to use the return pointer in the delay slot of the call, then we lose.
8027
8028 get_attr_type will try to recognize the given insn, so make sure to
8029 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
8030 in particular. */
8031 int
insn_refs_are_delayed(insn)8032 insn_refs_are_delayed (insn)
8033 rtx insn;
8034 {
8035 return ((GET_CODE (insn) == INSN
8036 && GET_CODE (PATTERN (insn)) != SEQUENCE
8037 && GET_CODE (PATTERN (insn)) != USE
8038 && GET_CODE (PATTERN (insn)) != CLOBBER
8039 && get_attr_type (insn) == TYPE_MILLI));
8040 }
8041
8042 /* On the HP-PA the value is found in register(s) 28(-29), unless
8043 the mode is SF or DF. Then the value is returned in fr4 (32).
8044
8045 This must perform the same promotions as PROMOTE_MODE, else
8046 PROMOTE_FUNCTION_RETURN will not work correctly.
8047
8048 Small structures must be returned in a PARALLEL on PA64 in order
8049 to match the HP Compiler ABI. */
8050
8051 rtx
function_value(valtype,func)8052 function_value (valtype, func)
8053 tree valtype;
8054 tree func ATTRIBUTE_UNUSED;
8055 {
8056 enum machine_mode valmode;
8057
8058 /* Aggregates with a size less than or equal to 128 bits are returned
8059 in GR 28(-29). They are left justified. The pad bits are undefined.
8060 Larger aggregates are returned in memory. */
8061 if (TARGET_64BIT && AGGREGATE_TYPE_P (valtype))
8062 {
8063 rtx loc[2];
8064 int i, offset = 0;
8065 int ub = int_size_in_bytes (valtype) <= UNITS_PER_WORD ? 1 : 2;
8066
8067 for (i = 0; i < ub; i++)
8068 {
8069 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
8070 gen_rtx_REG (DImode, 28 + i),
8071 GEN_INT (offset));
8072 offset += 8;
8073 }
8074
8075 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (ub, loc));
8076 }
8077
8078 if ((INTEGRAL_TYPE_P (valtype)
8079 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
8080 || POINTER_TYPE_P (valtype))
8081 valmode = word_mode;
8082 else
8083 valmode = TYPE_MODE (valtype);
8084
8085 if (TREE_CODE (valtype) == REAL_TYPE
8086 && TYPE_MODE (valtype) != TFmode
8087 && !TARGET_SOFT_FLOAT)
8088 return gen_rtx_REG (valmode, 32);
8089
8090 return gen_rtx_REG (valmode, 28);
8091 }
8092
8093 /* Return the location of a parameter that is passed in a register or NULL
8094 if the parameter has any component that is passed in memory.
8095
8096 This is new code and will be pushed to into the net sources after
8097 further testing.
8098
8099 ??? We might want to restructure this so that it looks more like other
8100 ports. */
8101 rtx
function_arg(cum,mode,type,named)8102 function_arg (cum, mode, type, named)
8103 CUMULATIVE_ARGS *cum;
8104 enum machine_mode mode;
8105 tree type;
8106 int named ATTRIBUTE_UNUSED;
8107 {
8108 int max_arg_words = (TARGET_64BIT ? 8 : 4);
8109 int alignment = 0;
8110 int arg_size;
8111 int fpr_reg_base;
8112 int gpr_reg_base;
8113 rtx retval;
8114
8115 if (mode == VOIDmode)
8116 return NULL_RTX;
8117
8118 arg_size = FUNCTION_ARG_SIZE (mode, type);
8119
8120 /* If this arg would be passed partially or totally on the stack, then
8121 this routine should return zero. FUNCTION_ARG_PARTIAL_NREGS will
8122 handle arguments which are split between regs and stack slots if
8123 the ABI mandates split arguments. */
8124 if (! TARGET_64BIT)
8125 {
8126 /* The 32-bit ABI does not split arguments. */
8127 if (cum->words + arg_size > max_arg_words)
8128 return NULL_RTX;
8129 }
8130 else
8131 {
8132 if (arg_size > 1)
8133 alignment = cum->words & 1;
8134 if (cum->words + alignment >= max_arg_words)
8135 return NULL_RTX;
8136 }
8137
8138 /* The 32bit ABIs and the 64bit ABIs are rather different,
8139 particularly in their handling of FP registers. We might
8140 be able to cleverly share code between them, but I'm not
8141 going to bother in the hope that splitting them up results
8142 in code that is more easily understood. */
8143
8144 if (TARGET_64BIT)
8145 {
8146 /* Advance the base registers to their current locations.
8147
8148 Remember, gprs grow towards smaller register numbers while
8149 fprs grow to higher register numbers. Also remember that
8150 although FP regs are 32-bit addressable, we pretend that
8151 the registers are 64-bits wide. */
8152 gpr_reg_base = 26 - cum->words;
8153 fpr_reg_base = 32 + cum->words;
8154
8155 /* Arguments wider than one word and small aggregates need special
8156 treatment. */
8157 if (arg_size > 1
8158 || mode == BLKmode
8159 || (type && AGGREGATE_TYPE_P (type)))
8160 {
8161 /* Double-extended precision (80-bit), quad-precision (128-bit)
8162 and aggregates including complex numbers are aligned on
8163 128-bit boundaries. The first eight 64-bit argument slots
8164 are associated one-to-one, with general registers r26
8165 through r19, and also with floating-point registers fr4
8166 through fr11. Arguments larger than one word are always
8167 passed in general registers.
8168
8169 Using a PARALLEL with a word mode register results in left
8170 justified data on a big-endian target. */
8171
8172 rtx loc[8];
8173 int i, offset = 0, ub = arg_size;
8174
8175 /* Align the base register. */
8176 gpr_reg_base -= alignment;
8177
8178 ub = MIN (ub, max_arg_words - cum->words - alignment);
8179 for (i = 0; i < ub; i++)
8180 {
8181 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
8182 gen_rtx_REG (DImode, gpr_reg_base),
8183 GEN_INT (offset));
8184 gpr_reg_base -= 1;
8185 offset += 8;
8186 }
8187
8188 return gen_rtx_PARALLEL (mode, gen_rtvec_v (ub, loc));
8189 }
8190 }
8191 else
8192 {
8193 /* If the argument is larger than a word, then we know precisely
8194 which registers we must use. */
8195 if (arg_size > 1)
8196 {
8197 if (cum->words)
8198 {
8199 gpr_reg_base = 23;
8200 fpr_reg_base = 38;
8201 }
8202 else
8203 {
8204 gpr_reg_base = 25;
8205 fpr_reg_base = 34;
8206 }
8207
8208 /* Structures 5 to 8 bytes in size are passed in the general
8209 registers in the same manner as other non floating-point
8210 objects. The data is right-justified and zero-extended
8211 to 64 bits.
8212
8213 This is magic. Normally, using a PARALLEL results in left
8214 justified data on a big-endian target. However, using a
8215 single double-word register provides the required right
8216 justication for 5 to 8 byte structures. This has nothing
8217 to do with the direction of padding specified for the argument.
8218 It has to do with how the data is widened and shifted into
8219 and from the register.
8220
8221 Aside from adding load_multiple and store_multiple patterns,
8222 this is the only way that I have found to obtain right
8223 justification of BLKmode data when it has a size greater
8224 than one word. Splitting the operation into two SImode loads
8225 or returning a DImode REG results in left justified data. */
8226 if (mode == BLKmode)
8227 {
8228 rtx loc = gen_rtx_EXPR_LIST (VOIDmode,
8229 gen_rtx_REG (DImode, gpr_reg_base),
8230 const0_rtx);
8231 return gen_rtx_PARALLEL (mode, gen_rtvec (1, loc));
8232 }
8233 }
8234 else
8235 {
8236 /* We have a single word (32 bits). A simple computation
8237 will get us the register #s we need. */
8238 gpr_reg_base = 26 - cum->words;
8239 fpr_reg_base = 32 + 2 * cum->words;
8240 }
8241 }
8242
8243 /* Determine if the argument needs to be passed in both general and
8244 floating point registers. */
8245 if (((TARGET_PORTABLE_RUNTIME || TARGET_64BIT || TARGET_ELF32)
8246 /* If we are doing soft-float with portable runtime, then there
8247 is no need to worry about FP regs. */
8248 && !TARGET_SOFT_FLOAT
8249 /* The parameter must be some kind of float, else we can just
8250 pass it in integer registers. */
8251 && FLOAT_MODE_P (mode)
8252 /* The target function must not have a prototype. */
8253 && cum->nargs_prototype <= 0
8254 /* libcalls do not need to pass items in both FP and general
8255 registers. */
8256 && type != NULL_TREE
8257 /* All this hair applies to "outgoing" args only. This includes
8258 sibcall arguments setup with FUNCTION_INCOMING_ARG. */
8259 && !cum->incoming)
8260 /* Also pass outgoing floating arguments in both registers in indirect
8261 calls with the 32 bit ABI and the HP assembler since there is no
8262 way to the specify argument locations in static functions. */
8263 || (!TARGET_64BIT
8264 && !TARGET_GAS
8265 && !cum->incoming
8266 && cum->indirect
8267 && FLOAT_MODE_P (mode)))
8268 {
8269 retval
8270 = gen_rtx_PARALLEL
8271 (mode,
8272 gen_rtvec (2,
8273 gen_rtx_EXPR_LIST (VOIDmode,
8274 gen_rtx_REG (mode, fpr_reg_base),
8275 const0_rtx),
8276 gen_rtx_EXPR_LIST (VOIDmode,
8277 gen_rtx_REG (mode, gpr_reg_base),
8278 const0_rtx)));
8279 }
8280 else
8281 {
8282 /* See if we should pass this parameter in a general register. */
8283 if (TARGET_SOFT_FLOAT
8284 /* Indirect calls in the normal 32bit ABI require all arguments
8285 to be passed in general registers. */
8286 || (!TARGET_PORTABLE_RUNTIME
8287 && !TARGET_64BIT
8288 && !TARGET_ELF32
8289 && cum->indirect)
8290 /* If the parameter is not a floating point parameter, then
8291 it belongs in GPRs. */
8292 || !FLOAT_MODE_P (mode))
8293 retval = gen_rtx_REG (mode, gpr_reg_base);
8294 else
8295 retval = gen_rtx_REG (mode, fpr_reg_base);
8296 }
8297 return retval;
8298 }
8299
8300
8301 /* If this arg would be passed totally in registers or totally on the stack,
8302 then this routine should return zero. It is currently called only for
8303 the 64-bit target. */
8304 int
function_arg_partial_nregs(cum,mode,type,named)8305 function_arg_partial_nregs (cum, mode, type, named)
8306 CUMULATIVE_ARGS *cum;
8307 enum machine_mode mode;
8308 tree type;
8309 int named ATTRIBUTE_UNUSED;
8310 {
8311 unsigned int max_arg_words = 8;
8312 unsigned int offset = 0;
8313
8314 if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1))
8315 offset = 1;
8316
8317 if (cum->words + offset + FUNCTION_ARG_SIZE (mode, type) <= max_arg_words)
8318 /* Arg fits fully into registers. */
8319 return 0;
8320 else if (cum->words + offset >= max_arg_words)
8321 /* Arg fully on the stack. */
8322 return 0;
8323 else
8324 /* Arg is split. */
8325 return max_arg_words - cum->words - offset;
8326 }
8327
8328
8329 /* Return 1 if this is a comparison operator. This allows the use of
8330 MATCH_OPERATOR to recognize all the branch insns. */
8331
8332 int
cmpib_comparison_operator(op,mode)8333 cmpib_comparison_operator (op, mode)
8334 register rtx op;
8335 enum machine_mode mode;
8336 {
8337 return ((mode == VOIDmode || GET_MODE (op) == mode)
8338 && (GET_CODE (op) == EQ
8339 || GET_CODE (op) == NE
8340 || GET_CODE (op) == GT
8341 || GET_CODE (op) == GTU
8342 || GET_CODE (op) == GE
8343 || GET_CODE (op) == LT
8344 || GET_CODE (op) == LE
8345 || GET_CODE (op) == LEU));
8346 }
8347
8348 /* On hpux10, the linker will give an error if we have a reference
8349 in the read-only data section to a symbol defined in a shared
8350 library. Therefore, expressions that might require a reloc can
8351 not be placed in the read-only data section. */
8352
8353 static void
pa_select_section(exp,reloc,align)8354 pa_select_section (exp, reloc, align)
8355 tree exp;
8356 int reloc;
8357 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED;
8358 {
8359 if (TREE_CODE (exp) == VAR_DECL
8360 && TREE_READONLY (exp)
8361 && !TREE_THIS_VOLATILE (exp)
8362 && DECL_INITIAL (exp)
8363 && (DECL_INITIAL (exp) == error_mark_node
8364 || TREE_CONSTANT (DECL_INITIAL (exp)))
8365 && !(reloc && flag_pic))
8366 readonly_data_section ();
8367 else if (TREE_CODE_CLASS (TREE_CODE (exp)) == 'c'
8368 && !(TREE_CODE (exp) == STRING_CST && flag_writable_strings)
8369 && !(reloc && flag_pic))
8370 readonly_data_section ();
8371 else
8372 data_section ();
8373 }
8374
8375 static void
pa_globalize_label(stream,name)8376 pa_globalize_label (stream, name)
8377 FILE *stream;
8378 const char *name;
8379 {
8380 /* We only handle DATA objects here, functions are globalized in
8381 ASM_DECLARE_FUNCTION_NAME. */
8382 if (! FUNCTION_NAME_P (name))
8383 {
8384 fputs ("\t.EXPORT ", stream);
8385 assemble_name (stream, name);
8386 fputs (",DATA\n", stream);
8387 }
8388 }
8389 #include "gt-pa.h"
8390