1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2017 Huawei Technologies Co., Ltd 3 */ 4 5 #ifndef _HINIC_PMD_TX_H_ 6 #define _HINIC_PMD_TX_H_ 7 8 #define HINIC_DEFAULT_TX_FREE_THRESH 32 9 #define HINIC_MAX_TX_FREE_BULK 64 10 11 #define HINIC_GET_WQ_HEAD(txq) ((txq)->wq->queue_buf_vaddr) 12 13 #define HINIC_GET_WQ_TAIL(txq) \ 14 ((txq)->wq->queue_buf_vaddr + (txq)->wq->wq_buf_size) 15 16 #define HINIC_TX_CKSUM_OFFLOAD_MASK (RTE_MBUF_F_TX_IP_CKSUM | \ 17 RTE_MBUF_F_TX_TCP_CKSUM | \ 18 RTE_MBUF_F_TX_UDP_CKSUM | \ 19 RTE_MBUF_F_TX_SCTP_CKSUM | \ 20 RTE_MBUF_F_TX_OUTER_IP_CKSUM | \ 21 RTE_MBUF_F_TX_TCP_SEG) 22 23 enum sq_wqe_type { 24 SQ_NORMAL_WQE = 0, 25 }; 26 27 /* tx offload info */ 28 struct hinic_tx_offload_info { 29 u8 outer_l2_len; 30 u8 outer_l3_type; 31 u16 outer_l3_len; 32 33 u8 inner_l2_len; 34 u8 inner_l3_type; 35 u16 inner_l3_len; 36 37 u8 tunnel_length; 38 u8 tunnel_type; 39 u8 inner_l4_type; 40 u8 inner_l4_len; 41 42 u16 payload_offset; 43 u8 inner_l4_tcp_udp; 44 u8 rsvd0; 45 }; 46 47 /* tx sge info */ 48 struct hinic_wqe_info { 49 u16 pi; 50 u16 owner; 51 u16 around; 52 u16 seq_wqebbs; 53 u16 sge_cnt; 54 u16 cpy_mbuf_cnt; 55 }; 56 57 struct hinic_sq_ctrl { 58 u32 ctrl_fmt; 59 u32 queue_info; 60 }; 61 62 struct hinic_sq_task { 63 u32 pkt_info0; 64 u32 pkt_info1; 65 u32 pkt_info2; 66 u32 ufo_v6_identify; 67 u32 pkt_info4; 68 u32 rsvd5; 69 }; 70 71 struct hinic_sq_bufdesc { 72 struct hinic_sge sge; 73 u32 rsvd; 74 }; 75 76 struct hinic_sq_wqe { 77 /* sq wqe control section */ 78 struct hinic_sq_ctrl ctrl; 79 80 /* sq task control section */ 81 struct hinic_sq_task task; 82 83 /* sq sge section start address, 1~127 sges */ 84 struct hinic_sq_bufdesc buf_descs[]; 85 }; 86 87 struct hinic_txq_stats { 88 u64 packets; 89 u64 bytes; 90 u64 rl_drop; 91 u64 tx_busy; 92 u64 off_errs; 93 u64 cpy_pkts; 94 u64 burst_pkts; 95 u64 sge_len0; 96 u64 mbuf_null; 97 }; 98 99 struct hinic_tx_info { 100 struct rte_mbuf *mbuf; 101 int wqebb_cnt; 102 struct rte_mbuf *cpy_mbuf; 103 }; 104 105 struct hinic_txq { 106 /* cacheline0 */ 107 struct hinic_nic_dev *nic_dev; 108 struct hinic_wq *wq; 109 struct hinic_sq *sq; 110 volatile u16 *cons_idx_addr; 111 struct hinic_tx_info *tx_info; 112 113 u16 tx_free_thresh; 114 u16 port_id; 115 u16 q_id; 116 u16 q_depth; 117 u32 cos; 118 u32 socket_id; 119 120 /* cacheline1 */ 121 struct hinic_txq_stats txq_stats; 122 u64 sq_head_addr; 123 u64 sq_bot_sge_addr; 124 }; 125 126 int hinic_setup_tx_resources(struct hinic_txq *txq); 127 128 void hinic_free_all_tx_resources(struct rte_eth_dev *eth_dev); 129 130 void hinic_free_all_tx_mbuf(struct rte_eth_dev *eth_dev); 131 132 void hinic_free_tx_resources(struct hinic_txq *txq); 133 134 u16 hinic_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, u16 nb_pkts); 135 136 void hinic_free_all_tx_mbufs(struct hinic_txq *txq); 137 138 void hinic_txq_get_stats(struct hinic_txq *txq, struct hinic_txq_stats *stats); 139 140 void hinic_txq_stats_reset(struct hinic_txq *txq); 141 142 int hinic_create_sq(struct hinic_hwdev *hwdev, u16 q_id, 143 u16 sq_depth, unsigned int socket_id); 144 145 void hinic_destroy_sq(struct hinic_hwdev *hwdev, u16 q_id); 146 147 #endif /* _HINIC_PMD_TX_H_ */ 148