1 /* $NetBSD: nouveau_dispnv50_head.c,v 1.2 2021/12/18 23:45:32 riastradh Exp $ */
2
3 /*
4 * Copyright 2018 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24 #include <sys/cdefs.h>
25 __KERNEL_RCSID(0, "$NetBSD: nouveau_dispnv50_head.c,v 1.2 2021/12/18 23:45:32 riastradh Exp $");
26
27 #include "head.h"
28 #include "base.h"
29 #include "core.h"
30 #include "curs.h"
31 #include "ovly.h"
32
33 #include <nvif/class.h>
34
35 #include <drm/drm_atomic_helper.h>
36 #include <drm/drm_crtc_helper.h>
37 #include "nouveau_connector.h"
38 void
nv50_head_flush_clr(struct nv50_head * head,struct nv50_head_atom * asyh,bool flush)39 nv50_head_flush_clr(struct nv50_head *head,
40 struct nv50_head_atom *asyh, bool flush)
41 {
42 union nv50_head_atom_mask clr = {
43 .mask = asyh->clr.mask & ~(flush ? 0 : asyh->set.mask),
44 };
45 if (clr.olut) head->func->olut_clr(head);
46 if (clr.core) head->func->core_clr(head);
47 if (clr.curs) head->func->curs_clr(head);
48 }
49
50 void
nv50_head_flush_set(struct nv50_head * head,struct nv50_head_atom * asyh)51 nv50_head_flush_set(struct nv50_head *head, struct nv50_head_atom *asyh)
52 {
53 if (asyh->set.view ) head->func->view (head, asyh);
54 if (asyh->set.mode ) head->func->mode (head, asyh);
55 if (asyh->set.core ) head->func->core_set(head, asyh);
56 if (asyh->set.olut ) {
57 asyh->olut.offset = nv50_lut_load(&head->olut,
58 asyh->olut.buffer,
59 asyh->state.gamma_lut,
60 asyh->olut.load);
61 head->func->olut_set(head, asyh);
62 }
63 if (asyh->set.curs ) head->func->curs_set(head, asyh);
64 if (asyh->set.base ) head->func->base (head, asyh);
65 if (asyh->set.ovly ) head->func->ovly (head, asyh);
66 if (asyh->set.dither ) head->func->dither (head, asyh);
67 if (asyh->set.procamp) head->func->procamp (head, asyh);
68 if (asyh->set.or ) head->func->or (head, asyh);
69 }
70
71 static void
nv50_head_atomic_check_procamp(struct nv50_head_atom * armh,struct nv50_head_atom * asyh,struct nouveau_conn_atom * asyc)72 nv50_head_atomic_check_procamp(struct nv50_head_atom *armh,
73 struct nv50_head_atom *asyh,
74 struct nouveau_conn_atom *asyc)
75 {
76 const int vib = asyc->procamp.color_vibrance - 100;
77 const int hue = asyc->procamp.vibrant_hue - 90;
78 const int adj = (vib > 0) ? 50 : 0;
79 asyh->procamp.sat.cos = ((vib * 2047 + adj) / 100) & 0xfff;
80 asyh->procamp.sat.sin = ((hue * 2047) / 100) & 0xfff;
81 asyh->set.procamp = true;
82 }
83
84 static void
nv50_head_atomic_check_dither(struct nv50_head_atom * armh,struct nv50_head_atom * asyh,struct nouveau_conn_atom * asyc)85 nv50_head_atomic_check_dither(struct nv50_head_atom *armh,
86 struct nv50_head_atom *asyh,
87 struct nouveau_conn_atom *asyc)
88 {
89 u32 mode = 0x00;
90
91 if (asyc->dither.mode == DITHERING_MODE_AUTO) {
92 if (asyh->base.depth > asyh->or.bpc * 3)
93 mode = DITHERING_MODE_DYNAMIC2X2;
94 } else {
95 mode = asyc->dither.mode;
96 }
97
98 if (asyc->dither.depth == DITHERING_DEPTH_AUTO) {
99 if (asyh->or.bpc >= 8)
100 mode |= DITHERING_DEPTH_8BPC;
101 } else {
102 mode |= asyc->dither.depth;
103 }
104
105 asyh->dither.enable = mode;
106 asyh->dither.bits = mode >> 1;
107 asyh->dither.mode = mode >> 3;
108 asyh->set.dither = true;
109 }
110
111 static void
nv50_head_atomic_check_view(struct nv50_head_atom * armh,struct nv50_head_atom * asyh,struct nouveau_conn_atom * asyc)112 nv50_head_atomic_check_view(struct nv50_head_atom *armh,
113 struct nv50_head_atom *asyh,
114 struct nouveau_conn_atom *asyc)
115 {
116 struct drm_connector *connector = asyc->state.connector;
117 struct drm_display_mode *omode = &asyh->state.adjusted_mode;
118 struct drm_display_mode *umode = &asyh->state.mode;
119 int mode = asyc->scaler.mode;
120 struct edid *edid;
121 int umode_vdisplay, omode_hdisplay, omode_vdisplay;
122
123 if (connector->edid_blob_ptr)
124 edid = (struct edid *)connector->edid_blob_ptr->data;
125 else
126 edid = NULL;
127
128 if (!asyc->scaler.full) {
129 if (mode == DRM_MODE_SCALE_NONE)
130 omode = umode;
131 } else {
132 /* Non-EDID LVDS/eDP mode. */
133 mode = DRM_MODE_SCALE_FULLSCREEN;
134 }
135
136 /* For the user-specified mode, we must ignore doublescan and
137 * the like, but honor frame packing.
138 */
139 umode_vdisplay = umode->vdisplay;
140 if ((umode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
141 umode_vdisplay += umode->vtotal;
142 asyh->view.iW = umode->hdisplay;
143 asyh->view.iH = umode_vdisplay;
144 /* For the output mode, we can just use the stock helper. */
145 drm_mode_get_hv_timing(omode, &omode_hdisplay, &omode_vdisplay);
146 asyh->view.oW = omode_hdisplay;
147 asyh->view.oH = omode_vdisplay;
148
149 /* Add overscan compensation if necessary, will keep the aspect
150 * ratio the same as the backend mode unless overridden by the
151 * user setting both hborder and vborder properties.
152 */
153 if ((asyc->scaler.underscan.mode == UNDERSCAN_ON ||
154 (asyc->scaler.underscan.mode == UNDERSCAN_AUTO &&
155 drm_detect_hdmi_monitor(edid)))) {
156 u32 bX = asyc->scaler.underscan.hborder;
157 u32 bY = asyc->scaler.underscan.vborder;
158 u32 r = (asyh->view.oH << 19) / asyh->view.oW;
159
160 if (bX) {
161 asyh->view.oW -= (bX * 2);
162 if (bY) asyh->view.oH -= (bY * 2);
163 else asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19;
164 } else {
165 asyh->view.oW -= (asyh->view.oW >> 4) + 32;
166 if (bY) asyh->view.oH -= (bY * 2);
167 else asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19;
168 }
169 }
170
171 /* Handle CENTER/ASPECT scaling, taking into account the areas
172 * removed already for overscan compensation.
173 */
174 switch (mode) {
175 case DRM_MODE_SCALE_CENTER:
176 /* NOTE: This will cause scaling when the input is
177 * larger than the output.
178 */
179 asyh->view.oW = min(asyh->view.iW, asyh->view.oW);
180 asyh->view.oH = min(asyh->view.iH, asyh->view.oH);
181 break;
182 case DRM_MODE_SCALE_ASPECT:
183 /* Determine whether the scaling should be on width or on
184 * height. This is done by comparing the aspect ratios of the
185 * sizes. If the output AR is larger than input AR, that means
186 * we want to change the width (letterboxed on the
187 * left/right), otherwise on the height (letterboxed on the
188 * top/bottom).
189 *
190 * E.g. 4:3 (1.333) AR image displayed on a 16:10 (1.6) AR
191 * screen will have letterboxes on the left/right. However a
192 * 16:9 (1.777) AR image on that same screen will have
193 * letterboxes on the top/bottom.
194 *
195 * inputAR = iW / iH; outputAR = oW / oH
196 * outputAR > inputAR is equivalent to oW * iH > iW * oH
197 */
198 if (asyh->view.oW * asyh->view.iH > asyh->view.iW * asyh->view.oH) {
199 /* Recompute output width, i.e. left/right letterbox */
200 u32 r = (asyh->view.iW << 19) / asyh->view.iH;
201 asyh->view.oW = ((asyh->view.oH * r) + (r / 2)) >> 19;
202 } else {
203 /* Recompute output height, i.e. top/bottom letterbox */
204 u32 r = (asyh->view.iH << 19) / asyh->view.iW;
205 asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19;
206 }
207 break;
208 default:
209 break;
210 }
211
212 asyh->set.view = true;
213 }
214
215 static int
nv50_head_atomic_check_lut(struct nv50_head * head,struct nv50_head_atom * asyh)216 nv50_head_atomic_check_lut(struct nv50_head *head,
217 struct nv50_head_atom *asyh)
218 {
219 struct nv50_disp *disp = nv50_disp(head->base.base.dev);
220 struct drm_property_blob *olut = asyh->state.gamma_lut;
221 int size;
222
223 /* Determine whether core output LUT should be enabled. */
224 if (olut) {
225 /* Check if any window(s) have stolen the core output LUT
226 * to as an input LUT for legacy gamma + I8 colour format.
227 */
228 if (asyh->wndw.olut) {
229 /* If any window has stolen the core output LUT,
230 * all of them must.
231 */
232 if (asyh->wndw.olut != asyh->wndw.mask)
233 return -EINVAL;
234 olut = NULL;
235 }
236 }
237
238 if (!olut) {
239 if (!head->func->olut_identity) {
240 asyh->olut.handle = 0;
241 return 0;
242 }
243 size = 0;
244 } else {
245 size = drm_color_lut_size(olut);
246 }
247
248 if (!head->func->olut(head, asyh, size)) {
249 DRM_DEBUG_KMS("Invalid olut\n");
250 return -EINVAL;
251 }
252 asyh->olut.handle = disp->core->chan.vram.handle;
253 asyh->olut.buffer = !asyh->olut.buffer;
254
255 return 0;
256 }
257
258 static void
nv50_head_atomic_check_mode(struct nv50_head * head,struct nv50_head_atom * asyh)259 nv50_head_atomic_check_mode(struct nv50_head *head, struct nv50_head_atom *asyh)
260 {
261 struct drm_display_mode *mode = &asyh->state.adjusted_mode;
262 struct nv50_head_mode *m = &asyh->mode;
263 u32 blankus;
264
265 drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V | CRTC_STEREO_DOUBLE);
266
267 /*
268 * DRM modes are defined in terms of a repeating interval
269 * starting with the active display area. The hardware modes
270 * are defined in terms of a repeating interval starting one
271 * unit (pixel or line) into the sync pulse. So, add bias.
272 */
273
274 m->h.active = mode->crtc_htotal;
275 m->h.synce = mode->crtc_hsync_end - mode->crtc_hsync_start - 1;
276 m->h.blanke = mode->crtc_hblank_end - mode->crtc_hsync_start - 1;
277 m->h.blanks = m->h.blanke + mode->crtc_hdisplay;
278
279 m->v.active = mode->crtc_vtotal;
280 m->v.synce = mode->crtc_vsync_end - mode->crtc_vsync_start - 1;
281 m->v.blanke = mode->crtc_vblank_end - mode->crtc_vsync_start - 1;
282 m->v.blanks = m->v.blanke + mode->crtc_vdisplay;
283
284 /*XXX: Safe underestimate, even "0" works */
285 blankus = (m->v.active - mode->crtc_vdisplay - 2) * m->h.active;
286 blankus *= 1000;
287 blankus /= mode->crtc_clock;
288 m->v.blankus = blankus;
289
290 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
291 m->v.blank2e = m->v.active + m->v.blanke;
292 m->v.blank2s = m->v.blank2e + mode->crtc_vdisplay;
293 m->v.active = (m->v.active * 2) + 1;
294 m->interlace = true;
295 } else {
296 m->v.blank2e = 0;
297 m->v.blank2s = 1;
298 m->interlace = false;
299 }
300 m->clock = mode->crtc_clock;
301
302 asyh->or.nhsync = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
303 asyh->or.nvsync = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
304 asyh->set.or = head->func->or != NULL;
305 asyh->set.mode = true;
306 }
307
308 static int
nv50_head_atomic_check(struct drm_crtc * crtc,struct drm_crtc_state * state)309 nv50_head_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state)
310 {
311 struct nouveau_drm *drm = nouveau_drm(crtc->dev);
312 struct nv50_head *head = nv50_head(crtc);
313 struct nv50_head_atom *armh = nv50_head_atom(crtc->state);
314 struct nv50_head_atom *asyh = nv50_head_atom(state);
315 struct nouveau_conn_atom *asyc = NULL;
316 struct drm_connector_state *conns;
317 struct drm_connector *conn;
318 int i;
319
320 NV_ATOMIC(drm, "%s atomic_check %d\n", crtc->name, asyh->state.active);
321 if (asyh->state.active) {
322 for_each_new_connector_in_state(asyh->state.state, conn, conns, i) {
323 if (conns->crtc == crtc) {
324 asyc = nouveau_conn_atom(conns);
325 break;
326 }
327 }
328
329 if (armh->state.active) {
330 if (asyc) {
331 if (asyh->state.mode_changed)
332 asyc->set.scaler = true;
333 if (armh->base.depth != asyh->base.depth)
334 asyc->set.dither = true;
335 }
336 } else {
337 if (asyc)
338 asyc->set.mask = ~0;
339 asyh->set.mask = ~0;
340 asyh->set.or = head->func->or != NULL;
341 }
342
343 if (asyh->state.mode_changed || asyh->state.connectors_changed)
344 nv50_head_atomic_check_mode(head, asyh);
345
346 if (asyh->state.color_mgmt_changed ||
347 memcmp(&armh->wndw, &asyh->wndw, sizeof(asyh->wndw))) {
348 int ret = nv50_head_atomic_check_lut(head, asyh);
349 if (ret)
350 return ret;
351
352 asyh->olut.visible = asyh->olut.handle != 0;
353 }
354
355 if (asyc) {
356 if (asyc->set.scaler)
357 nv50_head_atomic_check_view(armh, asyh, asyc);
358 if (asyc->set.dither)
359 nv50_head_atomic_check_dither(armh, asyh, asyc);
360 if (asyc->set.procamp)
361 nv50_head_atomic_check_procamp(armh, asyh, asyc);
362 }
363
364 if (head->func->core_calc) {
365 head->func->core_calc(head, asyh);
366 if (!asyh->core.visible)
367 asyh->olut.visible = false;
368 }
369
370 asyh->set.base = armh->base.cpp != asyh->base.cpp;
371 asyh->set.ovly = armh->ovly.cpp != asyh->ovly.cpp;
372 } else {
373 asyh->olut.visible = false;
374 asyh->core.visible = false;
375 asyh->curs.visible = false;
376 asyh->base.cpp = 0;
377 asyh->ovly.cpp = 0;
378 }
379
380 if (!drm_atomic_crtc_needs_modeset(&asyh->state)) {
381 if (asyh->core.visible) {
382 if (memcmp(&armh->core, &asyh->core, sizeof(asyh->core)))
383 asyh->set.core = true;
384 } else
385 if (armh->core.visible) {
386 asyh->clr.core = true;
387 }
388
389 if (asyh->curs.visible) {
390 if (memcmp(&armh->curs, &asyh->curs, sizeof(asyh->curs)))
391 asyh->set.curs = true;
392 } else
393 if (armh->curs.visible) {
394 asyh->clr.curs = true;
395 }
396
397 if (asyh->olut.visible) {
398 if (memcmp(&armh->olut, &asyh->olut, sizeof(asyh->olut)))
399 asyh->set.olut = true;
400 } else
401 if (armh->olut.visible) {
402 asyh->clr.olut = true;
403 }
404 } else {
405 asyh->clr.olut = armh->olut.visible;
406 asyh->clr.core = armh->core.visible;
407 asyh->clr.curs = armh->curs.visible;
408 asyh->set.olut = asyh->olut.visible;
409 asyh->set.core = asyh->core.visible;
410 asyh->set.curs = asyh->curs.visible;
411 }
412
413 if (asyh->clr.mask || asyh->set.mask)
414 nv50_atom(asyh->state.state)->lock_core = true;
415 return 0;
416 }
417
418 static const struct drm_crtc_helper_funcs
419 nv50_head_help = {
420 .atomic_check = nv50_head_atomic_check,
421 };
422
423 static void
nv50_head_atomic_destroy_state(struct drm_crtc * crtc,struct drm_crtc_state * state)424 nv50_head_atomic_destroy_state(struct drm_crtc *crtc,
425 struct drm_crtc_state *state)
426 {
427 struct nv50_head_atom *asyh = nv50_head_atom(state);
428 __drm_atomic_helper_crtc_destroy_state(&asyh->state);
429 kfree(asyh);
430 }
431
432 static struct drm_crtc_state *
nv50_head_atomic_duplicate_state(struct drm_crtc * crtc)433 nv50_head_atomic_duplicate_state(struct drm_crtc *crtc)
434 {
435 struct nv50_head_atom *armh = nv50_head_atom(crtc->state);
436 struct nv50_head_atom *asyh;
437 if (!(asyh = kmalloc(sizeof(*asyh), GFP_KERNEL)))
438 return NULL;
439 __drm_atomic_helper_crtc_duplicate_state(crtc, &asyh->state);
440 asyh->wndw = armh->wndw;
441 asyh->view = armh->view;
442 asyh->mode = armh->mode;
443 asyh->olut = armh->olut;
444 asyh->core = armh->core;
445 asyh->curs = armh->curs;
446 asyh->base = armh->base;
447 asyh->ovly = armh->ovly;
448 asyh->dither = armh->dither;
449 asyh->procamp = armh->procamp;
450 asyh->or = armh->or;
451 asyh->dp = armh->dp;
452 asyh->clr.mask = 0;
453 asyh->set.mask = 0;
454 return &asyh->state;
455 }
456
457 static void
nv50_head_reset(struct drm_crtc * crtc)458 nv50_head_reset(struct drm_crtc *crtc)
459 {
460 struct nv50_head_atom *asyh;
461
462 if (WARN_ON(!(asyh = kzalloc(sizeof(*asyh), GFP_KERNEL))))
463 return;
464
465 if (crtc->state)
466 nv50_head_atomic_destroy_state(crtc, crtc->state);
467
468 __drm_atomic_helper_crtc_reset(crtc, &asyh->state);
469 }
470
471 static void
nv50_head_destroy(struct drm_crtc * crtc)472 nv50_head_destroy(struct drm_crtc *crtc)
473 {
474 struct nv50_head *head = nv50_head(crtc);
475 nv50_lut_fini(&head->olut);
476 drm_crtc_cleanup(crtc);
477 kfree(head);
478 }
479
480 static const struct drm_crtc_funcs
481 nv50_head_func = {
482 .reset = nv50_head_reset,
483 .gamma_set = drm_atomic_helper_legacy_gamma_set,
484 .destroy = nv50_head_destroy,
485 .set_config = drm_atomic_helper_set_config,
486 .page_flip = drm_atomic_helper_page_flip,
487 .atomic_duplicate_state = nv50_head_atomic_duplicate_state,
488 .atomic_destroy_state = nv50_head_atomic_destroy_state,
489 };
490
491 struct nv50_head *
nv50_head_create(struct drm_device * dev,int index)492 nv50_head_create(struct drm_device *dev, int index)
493 {
494 struct nouveau_drm *drm = nouveau_drm(dev);
495 struct nv50_disp *disp = nv50_disp(dev);
496 struct nv50_head *head;
497 struct nv50_wndw *base, *ovly, *curs;
498 struct drm_crtc *crtc;
499 int ret;
500
501 head = kzalloc(sizeof(*head), GFP_KERNEL);
502 if (!head)
503 return ERR_PTR(-ENOMEM);
504
505 head->func = disp->core->func->head;
506 head->base.index = index;
507
508 if (disp->disp->object.oclass < GV100_DISP) {
509 ret = nv50_base_new(drm, head->base.index, &base);
510 ret = nv50_ovly_new(drm, head->base.index, &ovly);
511 } else {
512 ret = nv50_wndw_new(drm, DRM_PLANE_TYPE_PRIMARY,
513 head->base.index * 2 + 0, &base);
514 ret = nv50_wndw_new(drm, DRM_PLANE_TYPE_OVERLAY,
515 head->base.index * 2 + 1, &ovly);
516 }
517 if (ret == 0)
518 ret = nv50_curs_new(drm, head->base.index, &curs);
519 if (ret) {
520 kfree(head);
521 return ERR_PTR(ret);
522 }
523
524 crtc = &head->base.base;
525 drm_crtc_init_with_planes(dev, crtc, &base->plane, &curs->plane,
526 &nv50_head_func, "head-%d", head->base.index);
527 drm_crtc_helper_add(crtc, &nv50_head_help);
528 /* Keep the legacy gamma size at 256 to avoid compatibility issues */
529 drm_mode_crtc_set_gamma_size(crtc, 256);
530 drm_crtc_enable_color_mgmt(crtc, base->func->ilut_size,
531 disp->disp->object.oclass >= GF110_DISP,
532 head->func->olut_size);
533
534 if (head->func->olut_set) {
535 ret = nv50_lut_init(disp, &drm->client.mmu, &head->olut);
536 if (ret) {
537 nv50_head_destroy(crtc);
538 return ERR_PTR(ret);
539 }
540 }
541
542 return head;
543 }
544