1 /* $NetBSD: nouveau_dispnv50_core.c,v 1.2 2021/12/18 23:45:32 riastradh Exp $ */
2
3 /*
4 * Copyright 2018 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24 #include <sys/cdefs.h>
25 __KERNEL_RCSID(0, "$NetBSD: nouveau_dispnv50_core.c,v 1.2 2021/12/18 23:45:32 riastradh Exp $");
26
27 #include "core.h"
28
29 #include <nvif/class.h>
30
31 void
nv50_core_del(struct nv50_core ** pcore)32 nv50_core_del(struct nv50_core **pcore)
33 {
34 struct nv50_core *core = *pcore;
35 if (core) {
36 nv50_dmac_destroy(&core->chan);
37 kfree(*pcore);
38 *pcore = NULL;
39 }
40 }
41
42 int
nv50_core_new(struct nouveau_drm * drm,struct nv50_core ** pcore)43 nv50_core_new(struct nouveau_drm *drm, struct nv50_core **pcore)
44 {
45 struct {
46 s32 oclass;
47 int version;
48 int (*new)(struct nouveau_drm *, s32, struct nv50_core **);
49 } cores[] = {
50 { TU102_DISP_CORE_CHANNEL_DMA, 0, corec57d_new },
51 { GV100_DISP_CORE_CHANNEL_DMA, 0, corec37d_new },
52 { GP102_DISP_CORE_CHANNEL_DMA, 0, core917d_new },
53 { GP100_DISP_CORE_CHANNEL_DMA, 0, core917d_new },
54 { GM200_DISP_CORE_CHANNEL_DMA, 0, core917d_new },
55 { GM107_DISP_CORE_CHANNEL_DMA, 0, core917d_new },
56 { GK110_DISP_CORE_CHANNEL_DMA, 0, core917d_new },
57 { GK104_DISP_CORE_CHANNEL_DMA, 0, core917d_new },
58 { GF110_DISP_CORE_CHANNEL_DMA, 0, core907d_new },
59 { GT214_DISP_CORE_CHANNEL_DMA, 0, core827d_new },
60 { GT206_DISP_CORE_CHANNEL_DMA, 0, core827d_new },
61 { GT200_DISP_CORE_CHANNEL_DMA, 0, core827d_new },
62 { G82_DISP_CORE_CHANNEL_DMA, 0, core827d_new },
63 { NV50_DISP_CORE_CHANNEL_DMA, 0, core507d_new },
64 {}
65 };
66 struct nv50_disp *disp = nv50_disp(drm->dev);
67 int cid;
68
69 cid = nvif_mclass(&disp->disp->object, cores);
70 if (cid < 0) {
71 NV_ERROR(drm, "No supported core channel class\n");
72 return cid;
73 }
74
75 return cores[cid].new(drm, cores[cid].oclass, pcore);
76 }
77