1 /* $NetBSD: nouveau_nvkm_engine_gr_nv30.c,v 1.3 2021/12/18 23:45:36 riastradh Exp $ */
2
3 // SPDX-License-Identifier: MIT
4 #include <sys/cdefs.h>
5 __KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_engine_gr_nv30.c,v 1.3 2021/12/18 23:45:36 riastradh Exp $");
6
7 #include "nv20.h"
8 #include "regs.h"
9
10 #include <core/gpuobj.h>
11 #include <engine/fifo.h>
12 #include <engine/fifo/chan.h>
13 #include <subdev/fb.h>
14
15 /*******************************************************************************
16 * PGRAPH context
17 ******************************************************************************/
18
19 static const struct nvkm_object_func
20 nv30_gr_chan = {
21 .dtor = nv20_gr_chan_dtor,
22 .init = nv20_gr_chan_init,
23 .fini = nv20_gr_chan_fini,
24 };
25
26 static int
nv30_gr_chan_new(struct nvkm_gr * base,struct nvkm_fifo_chan * fifoch,const struct nvkm_oclass * oclass,struct nvkm_object ** pobject)27 nv30_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch,
28 const struct nvkm_oclass *oclass, struct nvkm_object **pobject)
29 {
30 struct nv20_gr *gr = nv20_gr(base);
31 struct nv20_gr_chan *chan;
32 int ret, i;
33
34 if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
35 return -ENOMEM;
36 nvkm_object_ctor(&nv30_gr_chan, oclass, &chan->object);
37 chan->gr = gr;
38 chan->chid = fifoch->chid;
39 *pobject = &chan->object;
40
41 ret = nvkm_memory_new(gr->base.engine.subdev.device,
42 NVKM_MEM_TARGET_INST, 0x5f48, 16, true,
43 &chan->inst);
44 if (ret)
45 return ret;
46
47 nvkm_kmap(chan->inst);
48 nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24));
49 nvkm_wo32(chan->inst, 0x0410, 0x00000101);
50 nvkm_wo32(chan->inst, 0x0424, 0x00000111);
51 nvkm_wo32(chan->inst, 0x0428, 0x00000060);
52 nvkm_wo32(chan->inst, 0x0444, 0x00000080);
53 nvkm_wo32(chan->inst, 0x0448, 0xffff0000);
54 nvkm_wo32(chan->inst, 0x044c, 0x00000001);
55 nvkm_wo32(chan->inst, 0x0460, 0x44400000);
56 nvkm_wo32(chan->inst, 0x048c, 0xffff0000);
57 for (i = 0x04e0; i < 0x04e8; i += 4)
58 nvkm_wo32(chan->inst, i, 0x0fff0000);
59 nvkm_wo32(chan->inst, 0x04ec, 0x00011100);
60 for (i = 0x0508; i < 0x0548; i += 4)
61 nvkm_wo32(chan->inst, i, 0x07ff0000);
62 nvkm_wo32(chan->inst, 0x0550, 0x4b7fffff);
63 nvkm_wo32(chan->inst, 0x058c, 0x00000080);
64 nvkm_wo32(chan->inst, 0x0590, 0x30201000);
65 nvkm_wo32(chan->inst, 0x0594, 0x70605040);
66 nvkm_wo32(chan->inst, 0x0598, 0xb8a89888);
67 nvkm_wo32(chan->inst, 0x059c, 0xf8e8d8c8);
68 nvkm_wo32(chan->inst, 0x05b0, 0xb0000000);
69 for (i = 0x0600; i < 0x0640; i += 4)
70 nvkm_wo32(chan->inst, i, 0x00010588);
71 for (i = 0x0640; i < 0x0680; i += 4)
72 nvkm_wo32(chan->inst, i, 0x00030303);
73 for (i = 0x06c0; i < 0x0700; i += 4)
74 nvkm_wo32(chan->inst, i, 0x0008aae4);
75 for (i = 0x0700; i < 0x0740; i += 4)
76 nvkm_wo32(chan->inst, i, 0x01012000);
77 for (i = 0x0740; i < 0x0780; i += 4)
78 nvkm_wo32(chan->inst, i, 0x00080008);
79 nvkm_wo32(chan->inst, 0x085c, 0x00040000);
80 nvkm_wo32(chan->inst, 0x0860, 0x00010000);
81 for (i = 0x0864; i < 0x0874; i += 4)
82 nvkm_wo32(chan->inst, i, 0x00040004);
83 for (i = 0x1f18; i <= 0x3088 ; i += 16) {
84 nvkm_wo32(chan->inst, i + 0, 0x10700ff9);
85 nvkm_wo32(chan->inst, i + 4, 0x0436086c);
86 nvkm_wo32(chan->inst, i + 8, 0x000c001b);
87 }
88 for (i = 0x30b8; i < 0x30c8; i += 4)
89 nvkm_wo32(chan->inst, i, 0x0000ffff);
90 nvkm_wo32(chan->inst, 0x344c, 0x3f800000);
91 nvkm_wo32(chan->inst, 0x3808, 0x3f800000);
92 nvkm_wo32(chan->inst, 0x381c, 0x3f800000);
93 nvkm_wo32(chan->inst, 0x3848, 0x40000000);
94 nvkm_wo32(chan->inst, 0x384c, 0x3f800000);
95 nvkm_wo32(chan->inst, 0x3850, 0x3f000000);
96 nvkm_wo32(chan->inst, 0x3858, 0x40000000);
97 nvkm_wo32(chan->inst, 0x385c, 0x3f800000);
98 nvkm_wo32(chan->inst, 0x3864, 0xbf800000);
99 nvkm_wo32(chan->inst, 0x386c, 0xbf800000);
100 nvkm_done(chan->inst);
101 return 0;
102 }
103
104 /*******************************************************************************
105 * PGRAPH engine/subdev functions
106 ******************************************************************************/
107
108 int
nv30_gr_init(struct nvkm_gr * base)109 nv30_gr_init(struct nvkm_gr *base)
110 {
111 struct nv20_gr *gr = nv20_gr(base);
112 struct nvkm_device *device = gr->base.engine.subdev.device;
113
114 nvkm_wr32(device, NV20_PGRAPH_CHANNEL_CTX_TABLE,
115 nvkm_memory_addr(gr->ctxtab) >> 4);
116
117 nvkm_wr32(device, NV03_PGRAPH_INTR , 0xFFFFFFFF);
118 nvkm_wr32(device, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
119
120 nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
121 nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x00000000);
122 nvkm_wr32(device, NV04_PGRAPH_DEBUG_1, 0x401287c0);
123 nvkm_wr32(device, 0x400890, 0x01b463ff);
124 nvkm_wr32(device, NV04_PGRAPH_DEBUG_3, 0xf2de0475);
125 nvkm_wr32(device, NV10_PGRAPH_DEBUG_4, 0x00008000);
126 nvkm_wr32(device, NV04_PGRAPH_LIMIT_VIOL_PIX, 0xf04bdff6);
127 nvkm_wr32(device, 0x400B80, 0x1003d888);
128 nvkm_wr32(device, 0x400B84, 0x0c000000);
129 nvkm_wr32(device, 0x400098, 0x00000000);
130 nvkm_wr32(device, 0x40009C, 0x0005ad00);
131 nvkm_wr32(device, 0x400B88, 0x62ff00ff); /* suspiciously like PGRAPH_DEBUG_2 */
132 nvkm_wr32(device, 0x4000a0, 0x00000000);
133 nvkm_wr32(device, 0x4000a4, 0x00000008);
134 nvkm_wr32(device, 0x4008a8, 0xb784a400);
135 nvkm_wr32(device, 0x400ba0, 0x002f8685);
136 nvkm_wr32(device, 0x400ba4, 0x00231f3f);
137 nvkm_wr32(device, 0x4008a4, 0x40000020);
138
139 if (device->chipset == 0x34) {
140 nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0004);
141 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00200201);
142 nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0008);
143 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000008);
144 nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0000);
145 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000032);
146 nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00E00004);
147 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000002);
148 }
149
150 nvkm_wr32(device, 0x4000c0, 0x00000016);
151
152 nvkm_wr32(device, NV10_PGRAPH_CTX_CONTROL, 0x10000100);
153 nvkm_wr32(device, NV10_PGRAPH_STATE , 0xFFFFFFFF);
154 nvkm_wr32(device, 0x0040075c , 0x00000001);
155
156 /* begin RAM config */
157 /* vramsz = pci_resource_len(gr->dev->pdev, 1) - 1; */
158 nvkm_wr32(device, 0x4009A4, nvkm_rd32(device, 0x100200));
159 nvkm_wr32(device, 0x4009A8, nvkm_rd32(device, 0x100204));
160 if (device->chipset != 0x34) {
161 nvkm_wr32(device, 0x400750, 0x00EA0000);
162 nvkm_wr32(device, 0x400754, nvkm_rd32(device, 0x100200));
163 nvkm_wr32(device, 0x400750, 0x00EA0004);
164 nvkm_wr32(device, 0x400754, nvkm_rd32(device, 0x100204));
165 }
166
167 return 0;
168 }
169
170 static const struct nvkm_gr_func
171 nv30_gr = {
172 .dtor = nv20_gr_dtor,
173 .oneinit = nv20_gr_oneinit,
174 .init = nv30_gr_init,
175 .intr = nv20_gr_intr,
176 .tile = nv20_gr_tile,
177 .chan_new = nv30_gr_chan_new,
178 .sclass = {
179 { -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */
180 { -1, -1, 0x0019, &nv04_gr_object }, /* clip */
181 { -1, -1, 0x0030, &nv04_gr_object }, /* null */
182 { -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */
183 { -1, -1, 0x0043, &nv04_gr_object }, /* rop */
184 { -1, -1, 0x0044, &nv04_gr_object }, /* patt */
185 { -1, -1, 0x004a, &nv04_gr_object }, /* gdi */
186 { -1, -1, 0x0062, &nv04_gr_object }, /* surf2d */
187 { -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */
188 { -1, -1, 0x0089, &nv04_gr_object }, /* sifm */
189 { -1, -1, 0x008a, &nv04_gr_object }, /* ifc */
190 { -1, -1, 0x009f, &nv04_gr_object }, /* imageblit */
191 { -1, -1, 0x0362, &nv04_gr_object }, /* surf2d (nv30) */
192 { -1, -1, 0x0389, &nv04_gr_object }, /* sifm (nv30) */
193 { -1, -1, 0x038a, &nv04_gr_object }, /* ifc (nv30) */
194 { -1, -1, 0x039e, &nv04_gr_object }, /* swzsurf (nv30) */
195 { -1, -1, 0x0397, &nv04_gr_object }, /* rankine */
196 { -1, -1, 0x0597, &nv04_gr_object }, /* kelvin */
197 {}
198 }
199 };
200
201 int
nv30_gr_new(struct nvkm_device * device,int index,struct nvkm_gr ** pgr)202 nv30_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
203 {
204 return nv20_gr_new_(&nv30_gr, device, index, pgr);
205 }
206