1 /* $NetBSD: nouveau_nvkm_engine_gr_nv2a.c,v 1.3 2021/12/18 23:45:36 riastradh Exp $ */
2
3 // SPDX-License-Identifier: MIT
4 #include <sys/cdefs.h>
5 __KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_engine_gr_nv2a.c,v 1.3 2021/12/18 23:45:36 riastradh Exp $");
6
7 #include "nv20.h"
8 #include "regs.h"
9
10 #include <core/gpuobj.h>
11 #include <engine/fifo.h>
12 #include <engine/fifo/chan.h>
13
14 /*******************************************************************************
15 * PGRAPH context
16 ******************************************************************************/
17
18 static const struct nvkm_object_func
19 nv2a_gr_chan = {
20 .dtor = nv20_gr_chan_dtor,
21 .init = nv20_gr_chan_init,
22 .fini = nv20_gr_chan_fini,
23 };
24
25 static int
nv2a_gr_chan_new(struct nvkm_gr * base,struct nvkm_fifo_chan * fifoch,const struct nvkm_oclass * oclass,struct nvkm_object ** pobject)26 nv2a_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch,
27 const struct nvkm_oclass *oclass, struct nvkm_object **pobject)
28 {
29 struct nv20_gr *gr = nv20_gr(base);
30 struct nv20_gr_chan *chan;
31 int ret, i;
32
33 if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
34 return -ENOMEM;
35 nvkm_object_ctor(&nv2a_gr_chan, oclass, &chan->object);
36 chan->gr = gr;
37 chan->chid = fifoch->chid;
38 *pobject = &chan->object;
39
40 ret = nvkm_memory_new(gr->base.engine.subdev.device,
41 NVKM_MEM_TARGET_INST, 0x36b0, 16, true,
42 &chan->inst);
43 if (ret)
44 return ret;
45
46 nvkm_kmap(chan->inst);
47 nvkm_wo32(chan->inst, 0x0000, 0x00000001 | (chan->chid << 24));
48 nvkm_wo32(chan->inst, 0x033c, 0xffff0000);
49 nvkm_wo32(chan->inst, 0x03a0, 0x0fff0000);
50 nvkm_wo32(chan->inst, 0x03a4, 0x0fff0000);
51 nvkm_wo32(chan->inst, 0x047c, 0x00000101);
52 nvkm_wo32(chan->inst, 0x0490, 0x00000111);
53 nvkm_wo32(chan->inst, 0x04a8, 0x44400000);
54 for (i = 0x04d4; i <= 0x04e0; i += 4)
55 nvkm_wo32(chan->inst, i, 0x00030303);
56 for (i = 0x04f4; i <= 0x0500; i += 4)
57 nvkm_wo32(chan->inst, i, 0x00080000);
58 for (i = 0x050c; i <= 0x0518; i += 4)
59 nvkm_wo32(chan->inst, i, 0x01012000);
60 for (i = 0x051c; i <= 0x0528; i += 4)
61 nvkm_wo32(chan->inst, i, 0x000105b8);
62 for (i = 0x052c; i <= 0x0538; i += 4)
63 nvkm_wo32(chan->inst, i, 0x00080008);
64 for (i = 0x055c; i <= 0x0598; i += 4)
65 nvkm_wo32(chan->inst, i, 0x07ff0000);
66 nvkm_wo32(chan->inst, 0x05a4, 0x4b7fffff);
67 nvkm_wo32(chan->inst, 0x05fc, 0x00000001);
68 nvkm_wo32(chan->inst, 0x0604, 0x00004000);
69 nvkm_wo32(chan->inst, 0x0610, 0x00000001);
70 nvkm_wo32(chan->inst, 0x0618, 0x00040000);
71 nvkm_wo32(chan->inst, 0x061c, 0x00010000);
72 for (i = 0x1a9c; i <= 0x22fc; i += 16) { /*XXX: check!! */
73 nvkm_wo32(chan->inst, (i + 0), 0x10700ff9);
74 nvkm_wo32(chan->inst, (i + 4), 0x0436086c);
75 nvkm_wo32(chan->inst, (i + 8), 0x000c001b);
76 }
77 nvkm_wo32(chan->inst, 0x269c, 0x3f800000);
78 nvkm_wo32(chan->inst, 0x26b0, 0x3f800000);
79 nvkm_wo32(chan->inst, 0x26dc, 0x40000000);
80 nvkm_wo32(chan->inst, 0x26e0, 0x3f800000);
81 nvkm_wo32(chan->inst, 0x26e4, 0x3f000000);
82 nvkm_wo32(chan->inst, 0x26ec, 0x40000000);
83 nvkm_wo32(chan->inst, 0x26f0, 0x3f800000);
84 nvkm_wo32(chan->inst, 0x26f8, 0xbf800000);
85 nvkm_wo32(chan->inst, 0x2700, 0xbf800000);
86 nvkm_wo32(chan->inst, 0x3024, 0x000fe000);
87 nvkm_wo32(chan->inst, 0x30a0, 0x000003f8);
88 nvkm_wo32(chan->inst, 0x33fc, 0x002fe000);
89 for (i = 0x341c; i <= 0x3438; i += 4)
90 nvkm_wo32(chan->inst, i, 0x001c527c);
91 nvkm_done(chan->inst);
92 return 0;
93 }
94
95 /*******************************************************************************
96 * PGRAPH engine/subdev functions
97 ******************************************************************************/
98
99 static const struct nvkm_gr_func
100 nv2a_gr = {
101 .dtor = nv20_gr_dtor,
102 .oneinit = nv20_gr_oneinit,
103 .init = nv20_gr_init,
104 .intr = nv20_gr_intr,
105 .tile = nv20_gr_tile,
106 .chan_new = nv2a_gr_chan_new,
107 .sclass = {
108 { -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */
109 { -1, -1, 0x0019, &nv04_gr_object }, /* clip */
110 { -1, -1, 0x0030, &nv04_gr_object }, /* null */
111 { -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */
112 { -1, -1, 0x0043, &nv04_gr_object }, /* rop */
113 { -1, -1, 0x0044, &nv04_gr_object }, /* patt */
114 { -1, -1, 0x004a, &nv04_gr_object }, /* gdi */
115 { -1, -1, 0x0062, &nv04_gr_object }, /* surf2d */
116 { -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */
117 { -1, -1, 0x0089, &nv04_gr_object }, /* sifm */
118 { -1, -1, 0x008a, &nv04_gr_object }, /* ifc */
119 { -1, -1, 0x0096, &nv04_gr_object }, /* celcius */
120 { -1, -1, 0x009e, &nv04_gr_object }, /* swzsurf */
121 { -1, -1, 0x009f, &nv04_gr_object }, /* imageblit */
122 { -1, -1, 0x0597, &nv04_gr_object }, /* kelvin */
123 {}
124 }
125 };
126
127 int
nv2a_gr_new(struct nvkm_device * device,int index,struct nvkm_gr ** pgr)128 nv2a_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
129 {
130 return nv20_gr_new_(&nv2a_gr, device, index, pgr);
131 }
132