1 /* $NetBSD: nouveau_nvkm_engine_gr_nv25.c,v 1.3 2021/12/18 23:45:36 riastradh Exp $ */
2
3 // SPDX-License-Identifier: MIT
4 #include <sys/cdefs.h>
5 __KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_engine_gr_nv25.c,v 1.3 2021/12/18 23:45:36 riastradh Exp $");
6
7 #include "nv20.h"
8 #include "regs.h"
9
10 #include <core/gpuobj.h>
11 #include <engine/fifo.h>
12 #include <engine/fifo/chan.h>
13
14 /*******************************************************************************
15 * PGRAPH context
16 ******************************************************************************/
17
18 static const struct nvkm_object_func
19 nv25_gr_chan = {
20 .dtor = nv20_gr_chan_dtor,
21 .init = nv20_gr_chan_init,
22 .fini = nv20_gr_chan_fini,
23 };
24
25 static int
nv25_gr_chan_new(struct nvkm_gr * base,struct nvkm_fifo_chan * fifoch,const struct nvkm_oclass * oclass,struct nvkm_object ** pobject)26 nv25_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch,
27 const struct nvkm_oclass *oclass, struct nvkm_object **pobject)
28 {
29 struct nv20_gr *gr = nv20_gr(base);
30 struct nv20_gr_chan *chan;
31 int ret, i;
32
33 if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
34 return -ENOMEM;
35 nvkm_object_ctor(&nv25_gr_chan, oclass, &chan->object);
36 chan->gr = gr;
37 chan->chid = fifoch->chid;
38 *pobject = &chan->object;
39
40 ret = nvkm_memory_new(gr->base.engine.subdev.device,
41 NVKM_MEM_TARGET_INST, 0x3724, 16, true,
42 &chan->inst);
43 if (ret)
44 return ret;
45
46 nvkm_kmap(chan->inst);
47 nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24));
48 nvkm_wo32(chan->inst, 0x035c, 0xffff0000);
49 nvkm_wo32(chan->inst, 0x03c0, 0x0fff0000);
50 nvkm_wo32(chan->inst, 0x03c4, 0x0fff0000);
51 nvkm_wo32(chan->inst, 0x049c, 0x00000101);
52 nvkm_wo32(chan->inst, 0x04b0, 0x00000111);
53 nvkm_wo32(chan->inst, 0x04c8, 0x00000080);
54 nvkm_wo32(chan->inst, 0x04cc, 0xffff0000);
55 nvkm_wo32(chan->inst, 0x04d0, 0x00000001);
56 nvkm_wo32(chan->inst, 0x04e4, 0x44400000);
57 nvkm_wo32(chan->inst, 0x04fc, 0x4b800000);
58 for (i = 0x0510; i <= 0x051c; i += 4)
59 nvkm_wo32(chan->inst, i, 0x00030303);
60 for (i = 0x0530; i <= 0x053c; i += 4)
61 nvkm_wo32(chan->inst, i, 0x00080000);
62 for (i = 0x0548; i <= 0x0554; i += 4)
63 nvkm_wo32(chan->inst, i, 0x01012000);
64 for (i = 0x0558; i <= 0x0564; i += 4)
65 nvkm_wo32(chan->inst, i, 0x000105b8);
66 for (i = 0x0568; i <= 0x0574; i += 4)
67 nvkm_wo32(chan->inst, i, 0x00080008);
68 for (i = 0x0598; i <= 0x05d4; i += 4)
69 nvkm_wo32(chan->inst, i, 0x07ff0000);
70 nvkm_wo32(chan->inst, 0x05e0, 0x4b7fffff);
71 nvkm_wo32(chan->inst, 0x0620, 0x00000080);
72 nvkm_wo32(chan->inst, 0x0624, 0x30201000);
73 nvkm_wo32(chan->inst, 0x0628, 0x70605040);
74 nvkm_wo32(chan->inst, 0x062c, 0xb0a09080);
75 nvkm_wo32(chan->inst, 0x0630, 0xf0e0d0c0);
76 nvkm_wo32(chan->inst, 0x0664, 0x00000001);
77 nvkm_wo32(chan->inst, 0x066c, 0x00004000);
78 nvkm_wo32(chan->inst, 0x0678, 0x00000001);
79 nvkm_wo32(chan->inst, 0x0680, 0x00040000);
80 nvkm_wo32(chan->inst, 0x0684, 0x00010000);
81 for (i = 0x1b04; i <= 0x2374; i += 16) {
82 nvkm_wo32(chan->inst, (i + 0), 0x10700ff9);
83 nvkm_wo32(chan->inst, (i + 4), 0x0436086c);
84 nvkm_wo32(chan->inst, (i + 8), 0x000c001b);
85 }
86 nvkm_wo32(chan->inst, 0x2704, 0x3f800000);
87 nvkm_wo32(chan->inst, 0x2718, 0x3f800000);
88 nvkm_wo32(chan->inst, 0x2744, 0x40000000);
89 nvkm_wo32(chan->inst, 0x2748, 0x3f800000);
90 nvkm_wo32(chan->inst, 0x274c, 0x3f000000);
91 nvkm_wo32(chan->inst, 0x2754, 0x40000000);
92 nvkm_wo32(chan->inst, 0x2758, 0x3f800000);
93 nvkm_wo32(chan->inst, 0x2760, 0xbf800000);
94 nvkm_wo32(chan->inst, 0x2768, 0xbf800000);
95 nvkm_wo32(chan->inst, 0x308c, 0x000fe000);
96 nvkm_wo32(chan->inst, 0x3108, 0x000003f8);
97 nvkm_wo32(chan->inst, 0x3468, 0x002fe000);
98 for (i = 0x3484; i <= 0x34a0; i += 4)
99 nvkm_wo32(chan->inst, i, 0x001c527c);
100 nvkm_done(chan->inst);
101 return 0;
102 }
103
104 /*******************************************************************************
105 * PGRAPH engine/subdev functions
106 ******************************************************************************/
107
108 static const struct nvkm_gr_func
109 nv25_gr = {
110 .dtor = nv20_gr_dtor,
111 .oneinit = nv20_gr_oneinit,
112 .init = nv20_gr_init,
113 .intr = nv20_gr_intr,
114 .tile = nv20_gr_tile,
115 .chan_new = nv25_gr_chan_new,
116 .sclass = {
117 { -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */
118 { -1, -1, 0x0019, &nv04_gr_object }, /* clip */
119 { -1, -1, 0x0030, &nv04_gr_object }, /* null */
120 { -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */
121 { -1, -1, 0x0043, &nv04_gr_object }, /* rop */
122 { -1, -1, 0x0044, &nv04_gr_object }, /* patt */
123 { -1, -1, 0x004a, &nv04_gr_object }, /* gdi */
124 { -1, -1, 0x0062, &nv04_gr_object }, /* surf2d */
125 { -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */
126 { -1, -1, 0x0089, &nv04_gr_object }, /* sifm */
127 { -1, -1, 0x008a, &nv04_gr_object }, /* ifc */
128 { -1, -1, 0x0096, &nv04_gr_object }, /* celcius */
129 { -1, -1, 0x009e, &nv04_gr_object }, /* swzsurf */
130 { -1, -1, 0x009f, &nv04_gr_object }, /* imageblit */
131 { -1, -1, 0x0597, &nv04_gr_object }, /* kelvin */
132 {}
133 }
134 };
135
136 int
nv25_gr_new(struct nvkm_device * device,int index,struct nvkm_gr ** pgr)137 nv25_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
138 {
139 return nv20_gr_new_(&nv25_gr, device, index, pgr);
140 }
141