1 /* $NetBSD: nouveau_dispnv04_tvnv17.c,v 1.5 2021/12/18 23:45:32 riastradh Exp $ */
2
3 /*
4 * Copyright (C) 2009 Francisco Jerez.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining
8 * a copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sublicense, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial
17 * portions of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
22 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
23 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
24 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
25 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: nouveau_dispnv04_tvnv17.c,v 1.5 2021/12/18 23:45:32 riastradh Exp $");
31
32 #include <drm/drm_crtc_helper.h>
33 #include <drm/drm_probe_helper.h>
34 #include "nouveau_drv.h"
35 #include "nouveau_reg.h"
36 #include "nouveau_encoder.h"
37 #include "nouveau_connector.h"
38 #include "nouveau_crtc.h"
39 #include "hw.h"
40 #include "tvnv17.h"
41
42 MODULE_PARM_DESC(tv_norm, "Default TV norm.\n"
43 "\t\tSupported: PAL, PAL-M, PAL-N, PAL-Nc, NTSC-M, NTSC-J,\n"
44 "\t\t\thd480i, hd480p, hd576i, hd576p, hd720p, hd1080i.\n"
45 "\t\tDefault: PAL\n"
46 "\t\t*NOTE* Ignored for cards with external TV encoders.");
47 static char *nouveau_tv_norm;
48 module_param_named(tv_norm, nouveau_tv_norm, charp, 0400);
49
nv42_tv_sample_load(struct drm_encoder * encoder)50 static uint32_t nv42_tv_sample_load(struct drm_encoder *encoder)
51 {
52 struct drm_device *dev = encoder->dev;
53 struct nouveau_drm *drm = nouveau_drm(dev);
54 struct nvkm_gpio *gpio = nvxx_gpio(&drm->client.device);
55 uint32_t testval, regoffset = nv04_dac_output_offset(encoder);
56 uint32_t gpio0, gpio1, fp_htotal, fp_hsync_start, fp_hsync_end,
57 fp_control, test_ctrl, dacclk, ctv_14, ctv_1c, ctv_6c;
58 uint32_t sample = 0;
59 int head;
60
61 #define RGB_TEST_DATA(r, g, b) (r << 0 | g << 10 | b << 20)
62 testval = RGB_TEST_DATA(0x82, 0xeb, 0x82);
63 if (drm->vbios.tvdactestval)
64 testval = drm->vbios.tvdactestval;
65
66 dacclk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset);
67 head = (dacclk & 0x100) >> 8;
68
69 /* Save the previous state. */
70 gpio1 = nvkm_gpio_get(gpio, 0, DCB_GPIO_TVDAC1, 0xff);
71 gpio0 = nvkm_gpio_get(gpio, 0, DCB_GPIO_TVDAC0, 0xff);
72 fp_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL);
73 fp_hsync_start = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START);
74 fp_hsync_end = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END);
75 fp_control = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL);
76 test_ctrl = NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset);
77 ctv_1c = NVReadRAMDAC(dev, head, 0x680c1c);
78 ctv_14 = NVReadRAMDAC(dev, head, 0x680c14);
79 ctv_6c = NVReadRAMDAC(dev, head, 0x680c6c);
80
81 /* Prepare the DAC for load detection. */
82 nvkm_gpio_set(gpio, 0, DCB_GPIO_TVDAC1, 0xff, true);
83 nvkm_gpio_set(gpio, 0, DCB_GPIO_TVDAC0, 0xff, true);
84
85 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, 1343);
86 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, 1047);
87 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END, 1183);
88 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL,
89 NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS |
90 NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12 |
91 NV_PRAMDAC_FP_TG_CONTROL_READ_PROG |
92 NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS |
93 NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS);
94
95 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, 0);
96
97 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset,
98 (dacclk & ~0xff) | 0x22);
99 msleep(1);
100 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset,
101 (dacclk & ~0xff) | 0x21);
102
103 NVWriteRAMDAC(dev, head, 0x680c1c, 1 << 20);
104 NVWriteRAMDAC(dev, head, 0x680c14, 4 << 16);
105
106 /* Sample pin 0x4 (usually S-video luma). */
107 NVWriteRAMDAC(dev, head, 0x680c6c, testval >> 10 & 0x3ff);
108 msleep(20);
109 sample |= NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset)
110 & 0x4 << 28;
111
112 /* Sample the remaining pins. */
113 NVWriteRAMDAC(dev, head, 0x680c6c, testval & 0x3ff);
114 msleep(20);
115 sample |= NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset)
116 & 0xa << 28;
117
118 /* Restore the previous state. */
119 NVWriteRAMDAC(dev, head, 0x680c1c, ctv_1c);
120 NVWriteRAMDAC(dev, head, 0x680c14, ctv_14);
121 NVWriteRAMDAC(dev, head, 0x680c6c, ctv_6c);
122 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, dacclk);
123 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, test_ctrl);
124 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, fp_control);
125 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END, fp_hsync_end);
126 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, fp_hsync_start);
127 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, fp_htotal);
128 nvkm_gpio_set(gpio, 0, DCB_GPIO_TVDAC1, 0xff, gpio1);
129 nvkm_gpio_set(gpio, 0, DCB_GPIO_TVDAC0, 0xff, gpio0);
130
131 return sample;
132 }
133
134 static bool
get_tv_detect_quirks(struct drm_device * dev,uint32_t * pin_mask)135 get_tv_detect_quirks(struct drm_device *dev, uint32_t *pin_mask)
136 {
137 struct nouveau_drm *drm = nouveau_drm(dev);
138 struct nvkm_device *device = nvxx_device(&drm->client.device);
139
140 if (device->quirk && device->quirk->tv_pin_mask) {
141 *pin_mask = device->quirk->tv_pin_mask;
142 return false;
143 }
144
145 return true;
146 }
147
148 static enum drm_connector_status
nv17_tv_detect(struct drm_encoder * encoder,struct drm_connector * connector)149 nv17_tv_detect(struct drm_encoder *encoder, struct drm_connector *connector)
150 {
151 struct drm_device *dev = encoder->dev;
152 struct nouveau_drm *drm = nouveau_drm(dev);
153 struct drm_mode_config *conf = &dev->mode_config;
154 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
155 struct dcb_output *dcb = tv_enc->base.dcb;
156 bool reliable = get_tv_detect_quirks(dev, &tv_enc->pin_mask);
157
158 if (nv04_dac_in_use(encoder))
159 return connector_status_disconnected;
160
161 if (reliable) {
162 if (drm->client.device.info.chipset == 0x42 ||
163 drm->client.device.info.chipset == 0x43)
164 tv_enc->pin_mask =
165 nv42_tv_sample_load(encoder) >> 28 & 0xe;
166 else
167 tv_enc->pin_mask =
168 nv17_dac_sample_load(encoder) >> 28 & 0xe;
169 }
170
171 switch (tv_enc->pin_mask) {
172 case 0x2:
173 case 0x4:
174 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Composite;
175 break;
176 case 0xc:
177 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_SVIDEO;
178 break;
179 case 0xe:
180 if (dcb->tvconf.has_component_output)
181 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Component;
182 else
183 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_SCART;
184 break;
185 default:
186 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
187 break;
188 }
189
190 drm_object_property_set_value(&connector->base,
191 conf->tv_subconnector_property,
192 tv_enc->subconnector);
193
194 if (!reliable) {
195 return connector_status_unknown;
196 } else if (tv_enc->subconnector) {
197 NV_INFO(drm, "Load detected on output %c\n",
198 '@' + ffs(dcb->or));
199 return connector_status_connected;
200 } else {
201 return connector_status_disconnected;
202 }
203 }
204
nv17_tv_get_ld_modes(struct drm_encoder * encoder,struct drm_connector * connector)205 static int nv17_tv_get_ld_modes(struct drm_encoder *encoder,
206 struct drm_connector *connector)
207 {
208 const struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
209 const struct drm_display_mode *tv_mode;
210 int n = 0;
211
212 for (tv_mode = nv17_tv_modes; tv_mode->hdisplay; tv_mode++) {
213 struct drm_display_mode *mode;
214
215 mode = drm_mode_duplicate(encoder->dev, tv_mode);
216
217 mode->clock = tv_norm->tv_enc_mode.vrefresh *
218 mode->htotal / 1000 *
219 mode->vtotal / 1000;
220
221 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
222 mode->clock *= 2;
223
224 if (mode->hdisplay == tv_norm->tv_enc_mode.hdisplay &&
225 mode->vdisplay == tv_norm->tv_enc_mode.vdisplay)
226 mode->type |= DRM_MODE_TYPE_PREFERRED;
227
228 drm_mode_probed_add(connector, mode);
229 n++;
230 }
231
232 return n;
233 }
234
nv17_tv_get_hd_modes(struct drm_encoder * encoder,struct drm_connector * connector)235 static int nv17_tv_get_hd_modes(struct drm_encoder *encoder,
236 struct drm_connector *connector)
237 {
238 const struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
239 const struct drm_display_mode *output_mode = &tv_norm->ctv_enc_mode.mode;
240 struct drm_display_mode *mode;
241 const struct {
242 int hdisplay;
243 int vdisplay;
244 } modes[] = {
245 { 640, 400 },
246 { 640, 480 },
247 { 720, 480 },
248 { 720, 576 },
249 { 800, 600 },
250 { 1024, 768 },
251 { 1280, 720 },
252 { 1280, 1024 },
253 { 1920, 1080 }
254 };
255 int i, n = 0;
256
257 for (i = 0; i < ARRAY_SIZE(modes); i++) {
258 if (modes[i].hdisplay > output_mode->hdisplay ||
259 modes[i].vdisplay > output_mode->vdisplay)
260 continue;
261
262 if (modes[i].hdisplay == output_mode->hdisplay &&
263 modes[i].vdisplay == output_mode->vdisplay) {
264 mode = drm_mode_duplicate(encoder->dev, output_mode);
265 mode->type |= DRM_MODE_TYPE_PREFERRED;
266
267 } else {
268 mode = drm_cvt_mode(encoder->dev, modes[i].hdisplay,
269 modes[i].vdisplay, 60, false,
270 (output_mode->flags &
271 DRM_MODE_FLAG_INTERLACE), false);
272 }
273
274 /* CVT modes are sometimes unsuitable... */
275 if (output_mode->hdisplay <= 720
276 || output_mode->hdisplay >= 1920) {
277 mode->htotal = output_mode->htotal;
278 mode->hsync_start = (mode->hdisplay + (mode->htotal
279 - mode->hdisplay) * 9 / 10) & ~7;
280 mode->hsync_end = mode->hsync_start + 8;
281 }
282
283 if (output_mode->vdisplay >= 1024) {
284 mode->vtotal = output_mode->vtotal;
285 mode->vsync_start = output_mode->vsync_start;
286 mode->vsync_end = output_mode->vsync_end;
287 }
288
289 mode->type |= DRM_MODE_TYPE_DRIVER;
290 drm_mode_probed_add(connector, mode);
291 n++;
292 }
293
294 return n;
295 }
296
nv17_tv_get_modes(struct drm_encoder * encoder,struct drm_connector * connector)297 static int nv17_tv_get_modes(struct drm_encoder *encoder,
298 struct drm_connector *connector)
299 {
300 const struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
301
302 if (tv_norm->kind == CTV_ENC_MODE)
303 return nv17_tv_get_hd_modes(encoder, connector);
304 else
305 return nv17_tv_get_ld_modes(encoder, connector);
306 }
307
nv17_tv_mode_valid(struct drm_encoder * encoder,struct drm_display_mode * mode)308 static int nv17_tv_mode_valid(struct drm_encoder *encoder,
309 struct drm_display_mode *mode)
310 {
311 const struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
312
313 if (tv_norm->kind == CTV_ENC_MODE) {
314 const struct drm_display_mode *output_mode =
315 &tv_norm->ctv_enc_mode.mode;
316
317 if (mode->clock > 400000)
318 return MODE_CLOCK_HIGH;
319
320 if (mode->hdisplay > output_mode->hdisplay ||
321 mode->vdisplay > output_mode->vdisplay)
322 return MODE_BAD;
323
324 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) !=
325 (output_mode->flags & DRM_MODE_FLAG_INTERLACE))
326 return MODE_NO_INTERLACE;
327
328 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
329 return MODE_NO_DBLESCAN;
330
331 } else {
332 const int vsync_tolerance = 600;
333
334 if (mode->clock > 70000)
335 return MODE_CLOCK_HIGH;
336
337 if (abs(drm_mode_vrefresh(mode) * 1000 -
338 tv_norm->tv_enc_mode.vrefresh) > vsync_tolerance)
339 return MODE_VSYNC;
340
341 /* The encoder takes care of the actual interlacing */
342 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
343 return MODE_NO_INTERLACE;
344 }
345
346 return MODE_OK;
347 }
348
nv17_tv_mode_fixup(struct drm_encoder * encoder,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)349 static bool nv17_tv_mode_fixup(struct drm_encoder *encoder,
350 const struct drm_display_mode *mode,
351 struct drm_display_mode *adjusted_mode)
352 {
353 const struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
354
355 if (nv04_dac_in_use(encoder))
356 return false;
357
358 if (tv_norm->kind == CTV_ENC_MODE)
359 adjusted_mode->clock = tv_norm->ctv_enc_mode.mode.clock;
360 else
361 adjusted_mode->clock = 90000;
362
363 return true;
364 }
365
nv17_tv_dpms(struct drm_encoder * encoder,int mode)366 static void nv17_tv_dpms(struct drm_encoder *encoder, int mode)
367 {
368 struct drm_device *dev = encoder->dev;
369 struct nouveau_drm *drm = nouveau_drm(dev);
370 struct nvkm_gpio *gpio = nvxx_gpio(&drm->client.device);
371 struct nv17_tv_state *regs = &to_tv_enc(encoder)->state;
372 const struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
373
374 if (nouveau_encoder(encoder)->last_dpms == mode)
375 return;
376 nouveau_encoder(encoder)->last_dpms = mode;
377
378 NV_INFO(drm, "Setting dpms mode %d on TV encoder (output %d)\n",
379 mode, nouveau_encoder(encoder)->dcb->index);
380
381 regs->ptv_200 &= ~1;
382
383 if (tv_norm->kind == CTV_ENC_MODE) {
384 nv04_dfp_update_fp_control(encoder, mode);
385
386 } else {
387 nv04_dfp_update_fp_control(encoder, DRM_MODE_DPMS_OFF);
388
389 if (mode == DRM_MODE_DPMS_ON)
390 regs->ptv_200 |= 1;
391 }
392
393 nv_load_ptv(dev, regs, 200);
394
395 nvkm_gpio_set(gpio, 0, DCB_GPIO_TVDAC1, 0xff, mode == DRM_MODE_DPMS_ON);
396 nvkm_gpio_set(gpio, 0, DCB_GPIO_TVDAC0, 0xff, mode == DRM_MODE_DPMS_ON);
397
398 nv04_dac_update_dacclk(encoder, mode == DRM_MODE_DPMS_ON);
399 }
400
nv17_tv_prepare(struct drm_encoder * encoder)401 static void nv17_tv_prepare(struct drm_encoder *encoder)
402 {
403 struct drm_device *dev = encoder->dev;
404 struct nouveau_drm *drm = nouveau_drm(dev);
405 const struct drm_encoder_helper_funcs *helper = encoder->helper_private;
406 const struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
407 int head = nouveau_crtc(encoder->crtc)->index;
408 uint8_t *cr_lcd = &nv04_display(dev)->mode_reg.crtc_reg[head].CRTC[
409 NV_CIO_CRE_LCD__INDEX];
410 uint32_t dacclk_off = NV_PRAMDAC_DACCLK +
411 nv04_dac_output_offset(encoder);
412 uint32_t dacclk;
413
414 helper->dpms(encoder, DRM_MODE_DPMS_OFF);
415
416 nv04_dfp_disable(dev, head);
417
418 /* Unbind any FP encoders from this head if we need the FP
419 * stuff enabled. */
420 if (tv_norm->kind == CTV_ENC_MODE) {
421 struct drm_encoder *enc;
422
423 list_for_each_entry(enc, &dev->mode_config.encoder_list, head) {
424 struct dcb_output *dcb = nouveau_encoder(enc)->dcb;
425
426 if ((dcb->type == DCB_OUTPUT_TMDS ||
427 dcb->type == DCB_OUTPUT_LVDS) &&
428 !enc->crtc &&
429 nv04_dfp_get_bound_head(dev, dcb) == head) {
430 nv04_dfp_bind_head(dev, dcb, head ^ 1,
431 drm->vbios.fp.dual_link);
432 }
433 }
434
435 }
436
437 if (tv_norm->kind == CTV_ENC_MODE)
438 *cr_lcd |= 0x1 | (head ? 0x0 : 0x8);
439
440 /* Set the DACCLK register */
441 dacclk = (NVReadRAMDAC(dev, 0, dacclk_off) & ~0x30) | 0x1;
442
443 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE)
444 dacclk |= 0x1a << 16;
445
446 if (tv_norm->kind == CTV_ENC_MODE) {
447 dacclk |= 0x20;
448
449 if (head)
450 dacclk |= 0x100;
451 else
452 dacclk &= ~0x100;
453
454 } else {
455 dacclk |= 0x10;
456
457 }
458
459 NVWriteRAMDAC(dev, 0, dacclk_off, dacclk);
460 }
461
nv17_tv_mode_set(struct drm_encoder * encoder,struct drm_display_mode * drm_mode,struct drm_display_mode * adjusted_mode)462 static void nv17_tv_mode_set(struct drm_encoder *encoder,
463 struct drm_display_mode *drm_mode,
464 struct drm_display_mode *adjusted_mode)
465 {
466 struct drm_device *dev = encoder->dev;
467 struct nouveau_drm *drm = nouveau_drm(dev);
468 int head = nouveau_crtc(encoder->crtc)->index;
469 struct nv04_crtc_reg *regs = &nv04_display(dev)->mode_reg.crtc_reg[head];
470 struct nv17_tv_state *tv_regs = &to_tv_enc(encoder)->state;
471 const struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
472 int i;
473
474 regs->CRTC[NV_CIO_CRE_53] = 0x40; /* FP_HTIMING */
475 regs->CRTC[NV_CIO_CRE_54] = 0; /* FP_VTIMING */
476 regs->ramdac_630 = 0x2; /* turn off green mode (tv test pattern?) */
477 regs->tv_setup = 1;
478 regs->ramdac_8c0 = 0x0;
479
480 if (tv_norm->kind == TV_ENC_MODE) {
481 tv_regs->ptv_200 = 0x13111100;
482 if (head)
483 tv_regs->ptv_200 |= 0x10;
484
485 tv_regs->ptv_20c = 0x808010;
486 tv_regs->ptv_304 = 0x2d00000;
487 tv_regs->ptv_600 = 0x0;
488 tv_regs->ptv_60c = 0x0;
489 tv_regs->ptv_610 = 0x1e00000;
490
491 if (tv_norm->tv_enc_mode.vdisplay == 576) {
492 tv_regs->ptv_508 = 0x1200000;
493 tv_regs->ptv_614 = 0x33;
494
495 } else if (tv_norm->tv_enc_mode.vdisplay == 480) {
496 tv_regs->ptv_508 = 0xf00000;
497 tv_regs->ptv_614 = 0x13;
498 }
499
500 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE) {
501 tv_regs->ptv_500 = 0xe8e0;
502 tv_regs->ptv_504 = 0x1710;
503 tv_regs->ptv_604 = 0x0;
504 tv_regs->ptv_608 = 0x0;
505 } else {
506 if (tv_norm->tv_enc_mode.vdisplay == 576) {
507 tv_regs->ptv_604 = 0x20;
508 tv_regs->ptv_608 = 0x10;
509 tv_regs->ptv_500 = 0x19710;
510 tv_regs->ptv_504 = 0x68f0;
511
512 } else if (tv_norm->tv_enc_mode.vdisplay == 480) {
513 tv_regs->ptv_604 = 0x10;
514 tv_regs->ptv_608 = 0x20;
515 tv_regs->ptv_500 = 0x4b90;
516 tv_regs->ptv_504 = 0x1b480;
517 }
518 }
519
520 for (i = 0; i < 0x40; i++)
521 tv_regs->tv_enc[i] = tv_norm->tv_enc_mode.tv_enc[i];
522
523 } else {
524 const struct drm_display_mode *output_mode =
525 &tv_norm->ctv_enc_mode.mode;
526
527 /* The registers in PRAMDAC+0xc00 control some timings and CSC
528 * parameters for the CTV encoder (It's only used for "HD" TV
529 * modes, I don't think I have enough working to guess what
530 * they exactly mean...), it's probably connected at the
531 * output of the FP encoder, but it also needs the analog
532 * encoder in its OR enabled and routed to the head it's
533 * using. It's enabled with the DACCLK register, bits [5:4].
534 */
535 for (i = 0; i < 38; i++)
536 regs->ctv_regs[i] = tv_norm->ctv_enc_mode.ctv_regs[i];
537
538 regs->fp_horiz_regs[FP_DISPLAY_END] = output_mode->hdisplay - 1;
539 regs->fp_horiz_regs[FP_TOTAL] = output_mode->htotal - 1;
540 regs->fp_horiz_regs[FP_SYNC_START] =
541 output_mode->hsync_start - 1;
542 regs->fp_horiz_regs[FP_SYNC_END] = output_mode->hsync_end - 1;
543 regs->fp_horiz_regs[FP_CRTC] = output_mode->hdisplay +
544 max((output_mode->hdisplay-600)/40 - 1, 1);
545
546 regs->fp_vert_regs[FP_DISPLAY_END] = output_mode->vdisplay - 1;
547 regs->fp_vert_regs[FP_TOTAL] = output_mode->vtotal - 1;
548 regs->fp_vert_regs[FP_SYNC_START] =
549 output_mode->vsync_start - 1;
550 regs->fp_vert_regs[FP_SYNC_END] = output_mode->vsync_end - 1;
551 regs->fp_vert_regs[FP_CRTC] = output_mode->vdisplay - 1;
552
553 regs->fp_control = NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS |
554 NV_PRAMDAC_FP_TG_CONTROL_READ_PROG |
555 NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12;
556
557 if (output_mode->flags & DRM_MODE_FLAG_PVSYNC)
558 regs->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS;
559 if (output_mode->flags & DRM_MODE_FLAG_PHSYNC)
560 regs->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS;
561
562 regs->fp_debug_0 = NV_PRAMDAC_FP_DEBUG_0_YWEIGHT_ROUND |
563 NV_PRAMDAC_FP_DEBUG_0_XWEIGHT_ROUND |
564 NV_PRAMDAC_FP_DEBUG_0_YINTERP_BILINEAR |
565 NV_PRAMDAC_FP_DEBUG_0_XINTERP_BILINEAR |
566 NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED |
567 NV_PRAMDAC_FP_DEBUG_0_YSCALE_ENABLE |
568 NV_PRAMDAC_FP_DEBUG_0_XSCALE_ENABLE;
569
570 regs->fp_debug_2 = 0;
571
572 regs->fp_margin_color = 0x801080;
573
574 }
575 }
576
nv17_tv_commit(struct drm_encoder * encoder)577 static void nv17_tv_commit(struct drm_encoder *encoder)
578 {
579 struct drm_device *dev = encoder->dev;
580 struct nouveau_drm *drm = nouveau_drm(dev);
581 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
582 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
583 const struct drm_encoder_helper_funcs *helper = encoder->helper_private;
584
585 if (get_tv_norm(encoder)->kind == TV_ENC_MODE) {
586 nv17_tv_update_rescaler(encoder);
587 nv17_tv_update_properties(encoder);
588 } else {
589 nv17_ctv_update_rescaler(encoder);
590 }
591
592 nv17_tv_state_load(dev, &to_tv_enc(encoder)->state);
593
594 /* This could use refinement for flatpanels, but it should work */
595 if (drm->client.device.info.chipset < 0x44)
596 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL +
597 nv04_dac_output_offset(encoder),
598 0xf0000000);
599 else
600 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL +
601 nv04_dac_output_offset(encoder),
602 0x00100000);
603
604 helper->dpms(encoder, DRM_MODE_DPMS_ON);
605
606 NV_INFO(drm, "Output %s is running on CRTC %d using output %c\n",
607 nouveau_encoder_connector_get(nv_encoder)->base.name,
608 nv_crtc->index, '@' + ffs(nv_encoder->dcb->or));
609 }
610
nv17_tv_save(struct drm_encoder * encoder)611 static void nv17_tv_save(struct drm_encoder *encoder)
612 {
613 struct drm_device *dev = encoder->dev;
614 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
615
616 nouveau_encoder(encoder)->restore.output =
617 NVReadRAMDAC(dev, 0,
618 NV_PRAMDAC_DACCLK +
619 nv04_dac_output_offset(encoder));
620
621 nv17_tv_state_save(dev, &tv_enc->saved_state);
622
623 tv_enc->state.ptv_200 = tv_enc->saved_state.ptv_200;
624 }
625
nv17_tv_restore(struct drm_encoder * encoder)626 static void nv17_tv_restore(struct drm_encoder *encoder)
627 {
628 struct drm_device *dev = encoder->dev;
629
630 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK +
631 nv04_dac_output_offset(encoder),
632 nouveau_encoder(encoder)->restore.output);
633
634 nv17_tv_state_load(dev, &to_tv_enc(encoder)->saved_state);
635
636 nouveau_encoder(encoder)->last_dpms = NV_DPMS_CLEARED;
637 }
638
nv17_tv_create_resources(struct drm_encoder * encoder,struct drm_connector * connector)639 static int nv17_tv_create_resources(struct drm_encoder *encoder,
640 struct drm_connector *connector)
641 {
642 struct drm_device *dev = encoder->dev;
643 struct nouveau_drm *drm = nouveau_drm(dev);
644 struct drm_mode_config *conf = &dev->mode_config;
645 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
646 struct dcb_output *dcb = nouveau_encoder(encoder)->dcb;
647 int num_tv_norms = dcb->tvconf.has_component_output ? NUM_TV_NORMS :
648 NUM_LD_TV_NORMS;
649 int i;
650
651 if (nouveau_tv_norm) {
652 i = match_string(nv17_tv_norm_names, num_tv_norms,
653 nouveau_tv_norm);
654 if (i < 0)
655 NV_WARN(drm, "Invalid TV norm setting \"%s\"\n",
656 nouveau_tv_norm);
657 else
658 tv_enc->tv_norm = i;
659 }
660
661 drm_mode_create_tv_properties(dev, num_tv_norms, nv17_tv_norm_names);
662
663 drm_object_attach_property(&connector->base,
664 conf->tv_select_subconnector_property,
665 tv_enc->select_subconnector);
666 drm_object_attach_property(&connector->base,
667 conf->tv_subconnector_property,
668 tv_enc->subconnector);
669 drm_object_attach_property(&connector->base,
670 conf->tv_mode_property,
671 tv_enc->tv_norm);
672 drm_object_attach_property(&connector->base,
673 conf->tv_flicker_reduction_property,
674 tv_enc->flicker);
675 drm_object_attach_property(&connector->base,
676 conf->tv_saturation_property,
677 tv_enc->saturation);
678 drm_object_attach_property(&connector->base,
679 conf->tv_hue_property,
680 tv_enc->hue);
681 drm_object_attach_property(&connector->base,
682 conf->tv_overscan_property,
683 tv_enc->overscan);
684
685 return 0;
686 }
687
nv17_tv_set_property(struct drm_encoder * encoder,struct drm_connector * connector,struct drm_property * property,uint64_t val)688 static int nv17_tv_set_property(struct drm_encoder *encoder,
689 struct drm_connector *connector,
690 struct drm_property *property,
691 uint64_t val)
692 {
693 struct drm_mode_config *conf = &encoder->dev->mode_config;
694 struct drm_crtc *crtc = encoder->crtc;
695 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
696 const struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
697 bool modes_changed = false;
698
699 if (property == conf->tv_overscan_property) {
700 tv_enc->overscan = val;
701 if (encoder->crtc) {
702 if (tv_norm->kind == CTV_ENC_MODE)
703 nv17_ctv_update_rescaler(encoder);
704 else
705 nv17_tv_update_rescaler(encoder);
706 }
707
708 } else if (property == conf->tv_saturation_property) {
709 if (tv_norm->kind != TV_ENC_MODE)
710 return -EINVAL;
711
712 tv_enc->saturation = val;
713 nv17_tv_update_properties(encoder);
714
715 } else if (property == conf->tv_hue_property) {
716 if (tv_norm->kind != TV_ENC_MODE)
717 return -EINVAL;
718
719 tv_enc->hue = val;
720 nv17_tv_update_properties(encoder);
721
722 } else if (property == conf->tv_flicker_reduction_property) {
723 if (tv_norm->kind != TV_ENC_MODE)
724 return -EINVAL;
725
726 tv_enc->flicker = val;
727 if (encoder->crtc)
728 nv17_tv_update_rescaler(encoder);
729
730 } else if (property == conf->tv_mode_property) {
731 if (connector->dpms != DRM_MODE_DPMS_OFF)
732 return -EINVAL;
733
734 tv_enc->tv_norm = val;
735
736 modes_changed = true;
737
738 } else if (property == conf->tv_select_subconnector_property) {
739 if (tv_norm->kind != TV_ENC_MODE)
740 return -EINVAL;
741
742 tv_enc->select_subconnector = val;
743 nv17_tv_update_properties(encoder);
744
745 } else {
746 return -EINVAL;
747 }
748
749 if (modes_changed) {
750 drm_helper_probe_single_connector_modes(connector, 0, 0);
751
752 /* Disable the crtc to ensure a full modeset is
753 * performed whenever it's turned on again. */
754 if (crtc)
755 drm_crtc_helper_set_mode(crtc, &crtc->mode,
756 crtc->x, crtc->y,
757 crtc->primary->fb);
758 }
759
760 return 0;
761 }
762
nv17_tv_destroy(struct drm_encoder * encoder)763 static void nv17_tv_destroy(struct drm_encoder *encoder)
764 {
765 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
766
767 drm_encoder_cleanup(encoder);
768 kfree(tv_enc);
769 }
770
771 static const struct drm_encoder_helper_funcs nv17_tv_helper_funcs = {
772 .dpms = nv17_tv_dpms,
773 .mode_fixup = nv17_tv_mode_fixup,
774 .prepare = nv17_tv_prepare,
775 .commit = nv17_tv_commit,
776 .mode_set = nv17_tv_mode_set,
777 .detect = nv17_tv_detect,
778 };
779
780 static const struct drm_encoder_slave_funcs nv17_tv_slave_funcs = {
781 .get_modes = nv17_tv_get_modes,
782 .mode_valid = nv17_tv_mode_valid,
783 .create_resources = nv17_tv_create_resources,
784 .set_property = nv17_tv_set_property,
785 };
786
787 static const struct drm_encoder_funcs nv17_tv_funcs = {
788 .destroy = nv17_tv_destroy,
789 };
790
791 int
nv17_tv_create(struct drm_connector * connector,struct dcb_output * entry)792 nv17_tv_create(struct drm_connector *connector, struct dcb_output *entry)
793 {
794 struct drm_device *dev = connector->dev;
795 struct drm_encoder *encoder;
796 struct nv17_tv_encoder *tv_enc = NULL;
797
798 tv_enc = kzalloc(sizeof(*tv_enc), GFP_KERNEL);
799 if (!tv_enc)
800 return -ENOMEM;
801
802 tv_enc->overscan = 50;
803 tv_enc->flicker = 50;
804 tv_enc->saturation = 50;
805 tv_enc->hue = 0;
806 tv_enc->tv_norm = TV_NORM_PAL;
807 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
808 tv_enc->select_subconnector = DRM_MODE_SUBCONNECTOR_Automatic;
809 tv_enc->pin_mask = 0;
810
811 encoder = to_drm_encoder(&tv_enc->base);
812
813 tv_enc->base.dcb = entry;
814 tv_enc->base.or = ffs(entry->or) - 1;
815
816 drm_encoder_init(dev, encoder, &nv17_tv_funcs, DRM_MODE_ENCODER_TVDAC,
817 NULL);
818 drm_encoder_helper_add(encoder, &nv17_tv_helper_funcs);
819 to_encoder_slave(encoder)->slave_funcs = &nv17_tv_slave_funcs;
820
821 tv_enc->base.enc_save = nv17_tv_save;
822 tv_enc->base.enc_restore = nv17_tv_restore;
823
824 encoder->possible_crtcs = entry->heads;
825 encoder->possible_clones = 0;
826
827 nv17_tv_create_resources(encoder, connector);
828 drm_connector_attach_encoder(connector, encoder);
829 return 0;
830 }
831