1 /* $NetBSD: nouveau_nvkm_engine_fifo_dmanv17.c,v 1.3 2021/12/18 23:45:35 riastradh Exp $ */
2
3 /*
4 * Copyright 2012 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Ben Skeggs
25 */
26 #include <sys/cdefs.h>
27 __KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_engine_fifo_dmanv17.c,v 1.3 2021/12/18 23:45:35 riastradh Exp $");
28
29 #include "channv04.h"
30 #include "regsnv04.h"
31
32 #include <core/client.h>
33 #include <core/gpuobj.h>
34 #include <subdev/instmem.h>
35
36 #include <nvif/class.h>
37 #include <nvif/cl006b.h>
38 #include <nvif/unpack.h>
39
40 static int
nv17_fifo_dma_new(struct nvkm_fifo * base,const struct nvkm_oclass * oclass,void * data,u32 size,struct nvkm_object ** pobject)41 nv17_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,
42 void *data, u32 size, struct nvkm_object **pobject)
43 {
44 struct nvkm_object *parent = oclass->parent;
45 union {
46 struct nv03_channel_dma_v0 v0;
47 } *args = data;
48 struct nv04_fifo *fifo = nv04_fifo(base);
49 struct nv04_fifo_chan *chan = NULL;
50 struct nvkm_device *device = fifo->base.engine.subdev.device;
51 struct nvkm_instmem *imem = device->imem;
52 int ret = -ENOSYS;
53
54 nvif_ioctl(parent, "create channel dma size %d\n", size);
55 if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
56 nvif_ioctl(parent, "create channel dma vers %d pushbuf %"PRIx64" "
57 "offset %08x\n", args->v0.version,
58 args->v0.pushbuf, args->v0.offset);
59 if (!args->v0.pushbuf)
60 return -EINVAL;
61 } else
62 return ret;
63
64 if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
65 return -ENOMEM;
66 *pobject = &chan->base.object;
67
68 ret = nvkm_fifo_chan_ctor(&nv04_fifo_dma_func, &fifo->base,
69 0x1000, 0x1000, false, 0, args->v0.pushbuf,
70 (1ULL << NVKM_ENGINE_DMAOBJ) |
71 (1ULL << NVKM_ENGINE_GR) |
72 (1ULL << NVKM_ENGINE_MPEG) | /* NV31- */
73 (1ULL << NVKM_ENGINE_SW),
74 0, 0x800000, 0x10000, oclass, &chan->base);
75 chan->fifo = fifo;
76 if (ret)
77 return ret;
78
79 args->v0.chid = chan->base.chid;
80 chan->ramfc = chan->base.chid * 64;
81
82 nvkm_kmap(imem->ramfc);
83 nvkm_wo32(imem->ramfc, chan->ramfc + 0x00, args->v0.offset);
84 nvkm_wo32(imem->ramfc, chan->ramfc + 0x04, args->v0.offset);
85 nvkm_wo32(imem->ramfc, chan->ramfc + 0x0c, chan->base.push->addr >> 4);
86 nvkm_wo32(imem->ramfc, chan->ramfc + 0x14,
87 NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
88 NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
89 #ifdef __BIG_ENDIAN
90 NV_PFIFO_CACHE1_BIG_ENDIAN |
91 #endif
92 NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8);
93 nvkm_done(imem->ramfc);
94 return 0;
95 }
96
97 const struct nvkm_fifo_chan_oclass
98 nv17_fifo_dma_oclass = {
99 .base.oclass = NV17_CHANNEL_DMA,
100 .base.minver = 0,
101 .base.maxver = 0,
102 .ctor = nv17_fifo_dma_new,
103 };
104