1 /* $NetBSD: nouveau_nv04_fbcon.c,v 1.4 2021/12/18 23:45:32 riastradh Exp $ */
2
3 /*
4 * Copyright 2009 Ben Skeggs
5 * Copyright 2008 Stuart Bennett
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 */
26
27 #include <sys/cdefs.h>
28 __KERNEL_RCSID(0, "$NetBSD: nouveau_nv04_fbcon.c,v 1.4 2021/12/18 23:45:32 riastradh Exp $");
29
30 #include "nouveau_drv.h"
31 #include "nouveau_dma.h"
32 #include "nouveau_fbcon.h"
33
34 int
nv04_fbcon_copyarea(struct fb_info * info,const struct fb_copyarea * region)35 nv04_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region)
36 {
37 struct nouveau_fbdev *nfbdev = info->par;
38 struct nouveau_drm *drm = nouveau_drm(nfbdev->helper.dev);
39 struct nouveau_channel *chan = drm->channel;
40 int ret;
41
42 ret = RING_SPACE(chan, 4);
43 if (ret)
44 return ret;
45
46 BEGIN_NV04(chan, NvSubImageBlit, 0x0300, 3);
47 OUT_RING(chan, (region->sy << 16) | region->sx);
48 OUT_RING(chan, (region->dy << 16) | region->dx);
49 OUT_RING(chan, (region->height << 16) | region->width);
50 FIRE_RING(chan);
51 return 0;
52 }
53
54 int
nv04_fbcon_fillrect(struct fb_info * info,const struct fb_fillrect * rect)55 nv04_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
56 {
57 struct nouveau_fbdev *nfbdev = info->par;
58 struct nouveau_drm *drm = nouveau_drm(nfbdev->helper.dev);
59 struct nouveau_channel *chan = drm->channel;
60 int ret;
61
62 ret = RING_SPACE(chan, 7);
63 if (ret)
64 return ret;
65
66 BEGIN_NV04(chan, NvSubGdiRect, 0x02fc, 1);
67 OUT_RING(chan, (rect->rop != ROP_COPY) ? 1 : 3);
68 BEGIN_NV04(chan, NvSubGdiRect, 0x03fc, 1);
69 if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
70 info->fix.visual == FB_VISUAL_DIRECTCOLOR)
71 OUT_RING(chan, ((uint32_t *)info->pseudo_palette)[rect->color]);
72 else
73 OUT_RING(chan, rect->color);
74 BEGIN_NV04(chan, NvSubGdiRect, 0x0400, 2);
75 OUT_RING(chan, (rect->dx << 16) | rect->dy);
76 OUT_RING(chan, (rect->width << 16) | rect->height);
77 FIRE_RING(chan);
78 return 0;
79 }
80
81 int
nv04_fbcon_imageblit(struct fb_info * info,const struct fb_image * image)82 nv04_fbcon_imageblit(struct fb_info *info, const struct fb_image *image)
83 {
84 struct nouveau_fbdev *nfbdev = info->par;
85 struct nouveau_drm *drm = nouveau_drm(nfbdev->helper.dev);
86 struct nouveau_channel *chan = drm->channel;
87 uint32_t fg;
88 uint32_t bg;
89 uint32_t dsize;
90 uint32_t *data = (uint32_t *)image->data;
91 int ret;
92
93 if (image->depth != 1)
94 return -ENODEV;
95
96 ret = RING_SPACE(chan, 8);
97 if (ret)
98 return ret;
99
100 if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
101 info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
102 fg = ((uint32_t *) info->pseudo_palette)[image->fg_color];
103 bg = ((uint32_t *) info->pseudo_palette)[image->bg_color];
104 } else {
105 fg = image->fg_color;
106 bg = image->bg_color;
107 }
108
109 BEGIN_NV04(chan, NvSubGdiRect, 0x0be4, 7);
110 OUT_RING(chan, (image->dy << 16) | (image->dx & 0xffff));
111 OUT_RING(chan, ((image->dy + image->height) << 16) |
112 ((image->dx + image->width) & 0xffff));
113 OUT_RING(chan, bg);
114 OUT_RING(chan, fg);
115 OUT_RING(chan, (image->height << 16) | ALIGN(image->width, 8));
116 OUT_RING(chan, (image->height << 16) | image->width);
117 OUT_RING(chan, (image->dy << 16) | (image->dx & 0xffff));
118
119 dsize = ALIGN(ALIGN(image->width, 8) * image->height, 32) >> 5;
120 while (dsize) {
121 int iter_len = dsize > 128 ? 128 : dsize;
122
123 ret = RING_SPACE(chan, iter_len + 1);
124 if (ret)
125 return ret;
126
127 BEGIN_NV04(chan, NvSubGdiRect, 0x0c00, iter_len);
128 OUT_RINGp(chan, data, iter_len);
129 data += iter_len;
130 dsize -= iter_len;
131 }
132
133 FIRE_RING(chan);
134 return 0;
135 }
136
137 int
nv04_fbcon_accel_init(struct fb_info * info)138 nv04_fbcon_accel_init(struct fb_info *info)
139 {
140 struct nouveau_fbdev *nfbdev = info->par;
141 struct drm_device *dev = nfbdev->helper.dev;
142 struct nouveau_drm *drm = nouveau_drm(dev);
143 struct nouveau_channel *chan = drm->channel;
144 struct nvif_device *device = &drm->client.device;
145 int surface_fmt, pattern_fmt, rect_fmt;
146 int ret;
147
148 switch (info->var.bits_per_pixel) {
149 case 8:
150 surface_fmt = 1;
151 pattern_fmt = 3;
152 rect_fmt = 3;
153 break;
154 case 16:
155 surface_fmt = 4;
156 pattern_fmt = 1;
157 rect_fmt = 1;
158 break;
159 case 32:
160 switch (info->var.transp.length) {
161 case 0: /* depth 24 */
162 case 8: /* depth 32 */
163 break;
164 default:
165 return -EINVAL;
166 }
167
168 surface_fmt = 6;
169 pattern_fmt = 3;
170 rect_fmt = 3;
171 break;
172 default:
173 return -EINVAL;
174 }
175
176 ret = nvif_object_init(&chan->user, 0x0062,
177 device->info.family >= NV_DEVICE_INFO_V0_CELSIUS ?
178 0x0062 : 0x0042, NULL, 0, &nfbdev->surf2d);
179 if (ret)
180 return ret;
181
182 ret = nvif_object_init(&chan->user, 0x0019, 0x0019, NULL, 0,
183 &nfbdev->clip);
184 if (ret)
185 return ret;
186
187 ret = nvif_object_init(&chan->user, 0x0043, 0x0043, NULL, 0,
188 &nfbdev->rop);
189 if (ret)
190 return ret;
191
192 ret = nvif_object_init(&chan->user, 0x0044, 0x0044, NULL, 0,
193 &nfbdev->patt);
194 if (ret)
195 return ret;
196
197 ret = nvif_object_init(&chan->user, 0x004a, 0x004a, NULL, 0,
198 &nfbdev->gdi);
199 if (ret)
200 return ret;
201
202 ret = nvif_object_init(&chan->user, 0x005f,
203 device->info.chipset >= 0x11 ? 0x009f : 0x005f,
204 NULL, 0, &nfbdev->blit);
205 if (ret)
206 return ret;
207
208 if (RING_SPACE(chan, 49 + (device->info.chipset >= 0x11 ? 4 : 0))) {
209 nouveau_fbcon_gpu_lockup(info);
210 return 0;
211 }
212
213 BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1);
214 OUT_RING(chan, nfbdev->surf2d.handle);
215 BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0184, 2);
216 OUT_RING(chan, chan->vram.handle);
217 OUT_RING(chan, chan->vram.handle);
218 BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 4);
219 OUT_RING(chan, surface_fmt);
220 OUT_RING(chan, info->fix.line_length | (info->fix.line_length << 16));
221 OUT_RING(chan, info->fix.smem_start - dev->mode_config.fb_base);
222 OUT_RING(chan, info->fix.smem_start - dev->mode_config.fb_base);
223
224 BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1);
225 OUT_RING(chan, nfbdev->rop.handle);
226 BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 1);
227 OUT_RING(chan, 0x55);
228
229 BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1);
230 OUT_RING(chan, nfbdev->patt.handle);
231 BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 8);
232 OUT_RING(chan, pattern_fmt);
233 #ifdef __BIG_ENDIAN
234 OUT_RING(chan, 2);
235 #else
236 OUT_RING(chan, 1);
237 #endif
238 OUT_RING(chan, 0);
239 OUT_RING(chan, 1);
240 OUT_RING(chan, ~0);
241 OUT_RING(chan, ~0);
242 OUT_RING(chan, ~0);
243 OUT_RING(chan, ~0);
244
245 BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1);
246 OUT_RING(chan, nfbdev->clip.handle);
247 BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 2);
248 OUT_RING(chan, 0);
249 OUT_RING(chan, (info->var.yres_virtual << 16) | info->var.xres_virtual);
250
251 BEGIN_NV04(chan, NvSubImageBlit, 0x0000, 1);
252 OUT_RING(chan, nfbdev->blit.handle);
253 BEGIN_NV04(chan, NvSubImageBlit, 0x019c, 1);
254 OUT_RING(chan, nfbdev->surf2d.handle);
255 BEGIN_NV04(chan, NvSubImageBlit, 0x02fc, 1);
256 OUT_RING(chan, 3);
257 if (device->info.chipset >= 0x11 /*XXX: oclass == 0x009f*/) {
258 BEGIN_NV04(chan, NvSubImageBlit, 0x0120, 3);
259 OUT_RING(chan, 0);
260 OUT_RING(chan, 1);
261 OUT_RING(chan, 2);
262 }
263
264 BEGIN_NV04(chan, NvSubGdiRect, 0x0000, 1);
265 OUT_RING(chan, nfbdev->gdi.handle);
266 BEGIN_NV04(chan, NvSubGdiRect, 0x0198, 1);
267 OUT_RING(chan, nfbdev->surf2d.handle);
268 BEGIN_NV04(chan, NvSubGdiRect, 0x0188, 2);
269 OUT_RING(chan, nfbdev->patt.handle);
270 OUT_RING(chan, nfbdev->rop.handle);
271 BEGIN_NV04(chan, NvSubGdiRect, 0x0304, 1);
272 OUT_RING(chan, 1);
273 BEGIN_NV04(chan, NvSubGdiRect, 0x0300, 1);
274 OUT_RING(chan, rect_fmt);
275 BEGIN_NV04(chan, NvSubGdiRect, 0x02fc, 1);
276 OUT_RING(chan, 3);
277
278 FIRE_RING(chan);
279
280 return 0;
281 }
282
283