xref: /netbsd-src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/disp/nouveau_nvkm_engine_disp_nv04.c (revision 41ec02673d281bbb3d38e6c78504ce6e30c228c1)
1 /*	$NetBSD: nouveau_nvkm_engine_disp_nv04.c,v 1.3 2021/12/18 23:45:35 riastradh Exp $	*/
2 
3 /*
4  * Copyright 2012 Red Hat Inc.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Ben Skeggs
25  */
26 #include <sys/cdefs.h>
27 __KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_engine_disp_nv04.c,v 1.3 2021/12/18 23:45:35 riastradh Exp $");
28 
29 #include "priv.h"
30 #include "head.h"
31 
32 static const struct nvkm_disp_oclass *
nv04_disp_root(struct nvkm_disp * disp)33 nv04_disp_root(struct nvkm_disp *disp)
34 {
35 	return &nv04_disp_root_oclass;
36 }
37 
38 static void
nv04_disp_intr(struct nvkm_disp * disp)39 nv04_disp_intr(struct nvkm_disp *disp)
40 {
41 	struct nvkm_subdev *subdev = &disp->engine.subdev;
42 	struct nvkm_device *device = subdev->device;
43 	u32 crtc0 = nvkm_rd32(device, 0x600100);
44 	u32 crtc1 = nvkm_rd32(device, 0x602100);
45 	u32 pvideo;
46 
47 	if (crtc0 & 0x00000001) {
48 		nvkm_disp_vblank(disp, 0);
49 		nvkm_wr32(device, 0x600100, 0x00000001);
50 	}
51 
52 	if (crtc1 & 0x00000001) {
53 		nvkm_disp_vblank(disp, 1);
54 		nvkm_wr32(device, 0x602100, 0x00000001);
55 	}
56 
57 	if (device->chipset >= 0x10 && device->chipset <= 0x40) {
58 		pvideo = nvkm_rd32(device, 0x8100);
59 		if (pvideo & ~0x11)
60 			nvkm_info(subdev, "PVIDEO intr: %08x\n", pvideo);
61 		nvkm_wr32(device, 0x8100, pvideo);
62 	}
63 }
64 
65 static const struct nvkm_disp_func
66 nv04_disp = {
67 	.intr = nv04_disp_intr,
68 	.root = nv04_disp_root,
69 };
70 
71 int
nv04_disp_new(struct nvkm_device * device,int index,struct nvkm_disp ** pdisp)72 nv04_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp)
73 {
74 	int ret, i;
75 
76 	ret = nvkm_disp_new_(&nv04_disp, device, index, pdisp);
77 	if (ret)
78 		return ret;
79 
80 	for (i = 0; i < 2; i++) {
81 		ret = nv04_head_new(*pdisp, i);
82 		if (ret)
83 			return ret;
84 	}
85 
86 	return 0;
87 }
88