1 /* $NetBSD: nouveau_dispnv04_arb.c,v 1.5 2021/12/18 23:45:32 riastradh Exp $ */
2
3 /*
4 * Copyright 1993-2003 NVIDIA, Corporation
5 * Copyright 2007-2009 Stuart Bennett
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
21 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
22 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 */
25
26 #include <sys/cdefs.h>
27 __KERNEL_RCSID(0, "$NetBSD: nouveau_dispnv04_arb.c,v 1.5 2021/12/18 23:45:32 riastradh Exp $");
28
29 #include "nouveau_drv.h"
30 #include "nouveau_reg.h"
31 #include "hw.h"
32
33 /****************************************************************************\
34 * *
35 * The video arbitration routines calculate some "magic" numbers. Fixes *
36 * the snow seen when accessing the framebuffer without it. *
37 * It just works (I hope). *
38 * *
39 \****************************************************************************/
40
41 struct nv_fifo_info {
42 int lwm;
43 int burst;
44 };
45
46 struct nv_sim_state {
47 int pclk_khz;
48 int mclk_khz;
49 int nvclk_khz;
50 int bpp;
51 int mem_page_miss;
52 int mem_latency;
53 int memory_type;
54 int memory_width;
55 int two_heads;
56 };
57
58 static void
nv04_calc_arb(struct nv_fifo_info * fifo,struct nv_sim_state * arb)59 nv04_calc_arb(struct nv_fifo_info *fifo, struct nv_sim_state *arb)
60 {
61 int pagemiss, cas, bpp;
62 int nvclks, mclks, crtpagemiss;
63 int found, mclk_extra, mclk_loop, cbs, m1, p1;
64 int mclk_freq, pclk_freq, nvclk_freq;
65 int us_m, us_n, us_p, crtc_drain_rate;
66 int cpm_us, us_crt, clwm;
67
68 pclk_freq = arb->pclk_khz;
69 mclk_freq = arb->mclk_khz;
70 nvclk_freq = arb->nvclk_khz;
71 pagemiss = arb->mem_page_miss;
72 cas = arb->mem_latency;
73 bpp = arb->bpp;
74 cbs = 128;
75
76 nvclks = 10;
77 mclks = 13 + cas;
78 mclk_extra = 3;
79 found = 0;
80
81 while (!found) {
82 found = 1;
83
84 mclk_loop = mclks + mclk_extra;
85 us_m = mclk_loop * 1000 * 1000 / mclk_freq;
86 us_n = nvclks * 1000 * 1000 / nvclk_freq;
87 us_p = nvclks * 1000 * 1000 / pclk_freq;
88
89 crtc_drain_rate = pclk_freq * bpp / 8;
90 crtpagemiss = 2;
91 crtpagemiss += 1;
92 cpm_us = crtpagemiss * pagemiss * 1000 * 1000 / mclk_freq;
93 us_crt = cpm_us + us_m + us_n + us_p;
94 clwm = us_crt * crtc_drain_rate / (1000 * 1000);
95 clwm++;
96
97 m1 = clwm + cbs - 512;
98 p1 = m1 * pclk_freq / mclk_freq;
99 p1 = p1 * bpp / 8;
100 if ((p1 < m1 && m1 > 0) || clwm > 519) {
101 found = !mclk_extra;
102 mclk_extra--;
103 }
104 if (clwm < 384)
105 clwm = 384;
106
107 fifo->lwm = clwm;
108 fifo->burst = cbs;
109 }
110 }
111
112 static void
nv10_calc_arb(struct nv_fifo_info * fifo,struct nv_sim_state * arb)113 nv10_calc_arb(struct nv_fifo_info *fifo, struct nv_sim_state *arb)
114 {
115 int fill_rate, drain_rate;
116 int pclks, nvclks, mclks, xclks;
117 int pclk_freq, nvclk_freq, mclk_freq;
118 int fill_lat, extra_lat;
119 int max_burst_o, max_burst_l;
120 int fifo_len, min_lwm, max_lwm;
121 const int burst_lat = 80; /* Maximum allowable latency due
122 * to the CRTC FIFO burst. (ns) */
123
124 pclk_freq = arb->pclk_khz;
125 nvclk_freq = arb->nvclk_khz;
126 mclk_freq = arb->mclk_khz;
127
128 fill_rate = mclk_freq * arb->memory_width / 8; /* kB/s */
129 drain_rate = pclk_freq * arb->bpp / 8; /* kB/s */
130
131 fifo_len = arb->two_heads ? 1536 : 1024; /* B */
132
133 /* Fixed FIFO refill latency. */
134
135 pclks = 4; /* lwm detect. */
136
137 nvclks = 3 /* lwm -> sync. */
138 + 2 /* fbi bus cycles (1 req + 1 busy) */
139 + 1 /* 2 edge sync. may be very close to edge so
140 * just put one. */
141 + 1 /* fbi_d_rdv_n */
142 + 1 /* Fbi_d_rdata */
143 + 1; /* crtfifo load */
144
145 mclks = 1 /* 2 edge sync. may be very close to edge so
146 * just put one. */
147 + 1 /* arb_hp_req */
148 + 5 /* tiling pipeline */
149 + 2 /* latency fifo */
150 + 2 /* memory request to fbio block */
151 + 7; /* data returned from fbio block */
152
153 /* Need to accumulate 256 bits for read */
154 mclks += (arb->memory_type == 0 ? 2 : 1)
155 * arb->memory_width / 32;
156
157 fill_lat = mclks * 1000 * 1000 / mclk_freq /* minimum mclk latency */
158 + nvclks * 1000 * 1000 / nvclk_freq /* nvclk latency */
159 + pclks * 1000 * 1000 / pclk_freq; /* pclk latency */
160
161 /* Conditional FIFO refill latency. */
162
163 xclks = 2 * arb->mem_page_miss + mclks /* Extra latency due to
164 * the overlay. */
165 + 2 * arb->mem_page_miss /* Extra pagemiss latency. */
166 + (arb->bpp == 32 ? 8 : 4); /* Margin of error. */
167
168 extra_lat = xclks * 1000 * 1000 / mclk_freq;
169
170 if (arb->two_heads)
171 /* Account for another CRTC. */
172 extra_lat += fill_lat + extra_lat + burst_lat;
173
174 /* FIFO burst */
175
176 /* Max burst not leading to overflows. */
177 max_burst_o = (1 + fifo_len - extra_lat * drain_rate / (1000 * 1000))
178 * (fill_rate / 1000) / ((fill_rate - drain_rate) / 1000);
179 fifo->burst = min(max_burst_o, 1024);
180
181 /* Max burst value with an acceptable latency. */
182 max_burst_l = burst_lat * fill_rate / (1000 * 1000);
183 fifo->burst = min(max_burst_l, fifo->burst);
184
185 fifo->burst = rounddown_pow_of_two(fifo->burst);
186
187 /* FIFO low watermark */
188
189 min_lwm = (fill_lat + extra_lat) * drain_rate / (1000 * 1000) + 1;
190 max_lwm = fifo_len - fifo->burst
191 + fill_lat * drain_rate / (1000 * 1000)
192 + fifo->burst * drain_rate / fill_rate;
193
194 fifo->lwm = min_lwm + 10 * (max_lwm - min_lwm) / 100; /* Empirical. */
195 }
196
197 static void
nv04_update_arb(struct drm_device * dev,int VClk,int bpp,int * burst,int * lwm)198 nv04_update_arb(struct drm_device *dev, int VClk, int bpp,
199 int *burst, int *lwm)
200 {
201 struct nouveau_drm *drm = nouveau_drm(dev);
202 struct nvif_object *device = &nouveau_drm(dev)->client.device.object;
203 struct nv_fifo_info fifo_data;
204 struct nv_sim_state sim_data;
205 int MClk = nouveau_hw_get_clock(dev, PLL_MEMORY);
206 int NVClk = nouveau_hw_get_clock(dev, PLL_CORE);
207 uint32_t cfg1 = nvif_rd32(device, NV04_PFB_CFG1);
208
209 sim_data.pclk_khz = VClk;
210 sim_data.mclk_khz = MClk;
211 sim_data.nvclk_khz = NVClk;
212 sim_data.bpp = bpp;
213 sim_data.two_heads = nv_two_heads(dev);
214 if ((dev->pdev->device & 0xffff) == 0x01a0 /*CHIPSET_NFORCE*/ ||
215 (dev->pdev->device & 0xffff) == 0x01f0 /*CHIPSET_NFORCE2*/) {
216 uint32_t type;
217 int domain = pci_domain_nr(dev->pdev->bus);
218
219 pci_read_config_dword(pci_get_domain_bus_and_slot(domain, 0, 1),
220 0x7c, &type);
221
222 sim_data.memory_type = (type >> 12) & 1;
223 sim_data.memory_width = 64;
224 sim_data.mem_latency = 3;
225 sim_data.mem_page_miss = 10;
226 } else {
227 sim_data.memory_type = nvif_rd32(device, NV04_PFB_CFG0) & 0x1;
228 sim_data.memory_width = (nvif_rd32(device, NV_PEXTDEV_BOOT_0) & 0x10) ? 128 : 64;
229 sim_data.mem_latency = cfg1 & 0xf;
230 sim_data.mem_page_miss = ((cfg1 >> 4) & 0xf) + ((cfg1 >> 31) & 0x1);
231 }
232
233 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_TNT)
234 nv04_calc_arb(&fifo_data, &sim_data);
235 else
236 nv10_calc_arb(&fifo_data, &sim_data);
237
238 *burst = ilog2(fifo_data.burst >> 4);
239 *lwm = fifo_data.lwm >> 3;
240 }
241
242 static void
nv20_update_arb(int * burst,int * lwm)243 nv20_update_arb(int *burst, int *lwm)
244 {
245 unsigned int fifo_size, burst_size, graphics_lwm;
246
247 fifo_size = 2048;
248 burst_size = 512;
249 graphics_lwm = fifo_size - burst_size;
250
251 *burst = ilog2(burst_size >> 5);
252 *lwm = graphics_lwm >> 3;
253 }
254
255 void
nouveau_calc_arb(struct drm_device * dev,int vclk,int bpp,int * burst,int * lwm)256 nouveau_calc_arb(struct drm_device *dev, int vclk, int bpp, int *burst, int *lwm)
257 {
258 struct nouveau_drm *drm = nouveau_drm(dev);
259
260 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_KELVIN)
261 nv04_update_arb(dev, vclk, bpp, burst, lwm);
262 else if ((dev->pdev->device & 0xfff0) == 0x0240 /*CHIPSET_C51*/ ||
263 (dev->pdev->device & 0xfff0) == 0x03d0 /*CHIPSET_C512*/) {
264 *burst = 128;
265 *lwm = 0x0480;
266 } else
267 nv20_update_arb(burst, lwm);
268 }
269