1 /* $NetBSD: ninjaata32.c,v 1.20 2017/10/20 07:06:07 jdolecek Exp $ */
2
3 /*
4 * Copyright (c) 2006 ITOH Yasufumi.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS''
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
26 * THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: ninjaata32.c,v 1.20 2017/10/20 07:06:07 jdolecek Exp $");
31
32 #include <sys/param.h>
33 #include <sys/kernel.h>
34 #include <sys/device.h>
35 #include <sys/proc.h>
36
37 #include <sys/bus.h>
38 #include <sys/intr.h>
39
40 #include <dev/ata/atavar.h>
41 #include <dev/ic/wdcreg.h>
42 #include <dev/ic/wdcvar.h>
43
44 #include <dev/ic/ninjaata32reg.h>
45 #include <dev/ic/ninjaata32var.h>
46
47 #ifdef NJATA32_DEBUG
48 #define DPRINTF(x) printf x
49 #else
50 #define DPRINTF(x)
51 #endif
52
53 static void njata32_init(struct njata32_softc *, int nosleep);
54 static void njata32_irqack(struct ata_channel *);
55 static void njata32_clearirq(struct ata_channel *, int);
56 static void njata32_setup_channel(struct ata_channel *);
57 static int njata32_dma_init(void *, int channel, int drive,
58 void *databuf, size_t datalen, int flags);
59 static void njata32_piobm_start(void *, int channel, int drive, int skip,
60 int xferlen, int flags);
61 static int njata32_dma_finish(void *, int channel, int drive, int force);
62 static void njata32_piobm_done(void *, int channel, int drive);
63
64 #if 0 /* ATA DMA is currently unused */
65 static const uint8_t njata32_timing_dma[NJATA32_MODE_MAX_DMA + 1] = {
66 NJATA32_TIMING_DMA0, NJATA32_TIMING_DMA1, NJATA32_TIMING_DMA2
67 };
68 #endif
69 static const uint8_t njata32_timing_pio[NJATA32_MODE_MAX_PIO + 1] = {
70 NJATA32_TIMING_PIO0, NJATA32_TIMING_PIO1, NJATA32_TIMING_PIO2,
71 NJATA32_TIMING_PIO3, NJATA32_TIMING_PIO4
72 };
73
74 static void
njata32_init(struct njata32_softc * sc,int nosleep)75 njata32_init(struct njata32_softc *sc, int nosleep)
76 {
77
78 /* disable interrupts */
79 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
80 NJATA32_REG_IRQ_SELECT, 0);
81
82 /* bus reset */
83 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), NJATA32_REG_AS,
84 NJATA32_AS_WAIT0 | NJATA32_AS_BUS_RESET);
85 if (nosleep)
86 delay(50000);
87 else
88 tsleep(sc, PRIBIO, "njaini", mstohz(50));
89 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), NJATA32_REG_AS,
90 NJATA32_AS_WAIT0);
91
92 /* initial transfer speed */
93 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
94 NJATA32_REG_TIMING, NJATA32_TIMING_PIO0 + sc->sc_atawait);
95
96 /* setup busmaster mode */
97 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), NJATA32_REG_IOBM,
98 NJATA32_IOBM_DEFAULT);
99
100 /* enable interrupts */
101 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
102 NJATA32_REG_IRQ_SELECT, NJATA32_IRQ_XFER | NJATA32_IRQ_DEV);
103 }
104
105 void
njata32_attach(struct njata32_softc * sc)106 njata32_attach(struct njata32_softc *sc)
107 {
108 bus_addr_t dmaaddr;
109 int i, devno, error;
110 struct wdc_regs *wdr;
111
112 /*
113 * allocate DMA resource
114 */
115 if ((error = bus_dmamem_alloc(sc->sc_dmat,
116 sizeof(struct njata32_dma_page), PAGE_SIZE, 0,
117 &sc->sc_sgt_seg, 1, &sc->sc_sgt_nsegs, BUS_DMA_NOWAIT)) != 0) {
118 aprint_error("%s: unable to allocate sgt page, error = %d\n",
119 NJATA32NAME(sc), error);
120 return;
121 }
122 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_sgt_seg,
123 sc->sc_sgt_nsegs, sizeof(struct njata32_dma_page),
124 (void **)&sc->sc_sgtpg,
125 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) {
126 aprint_error("%s: unable to map sgt page, error = %d\n",
127 NJATA32NAME(sc), error);
128 goto fail1;
129 }
130 if ((error = bus_dmamap_create(sc->sc_dmat,
131 sizeof(struct njata32_dma_page), 1,
132 sizeof(struct njata32_dma_page), 0, BUS_DMA_NOWAIT,
133 &sc->sc_dmamap_sgt)) != 0) {
134 aprint_error("%s: unable to create sgt DMA map, error = %d\n",
135 NJATA32NAME(sc), error);
136 goto fail2;
137 }
138 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap_sgt,
139 sc->sc_sgtpg, sizeof(struct njata32_dma_page),
140 NULL, BUS_DMA_NOWAIT)) != 0) {
141 aprint_error("%s: unable to load sgt DMA map, error = %d\n",
142 NJATA32NAME(sc), error);
143 goto fail3;
144 }
145
146 dmaaddr = sc->sc_dmamap_sgt->dm_segs[0].ds_addr;
147
148 for (devno = 0; devno < NJATA32_NUM_DEV; devno++) {
149 sc->sc_dev[devno].d_sgt = sc->sc_sgtpg->dp_sg[devno];
150 sc->sc_dev[devno].d_sgt_dma = dmaaddr +
151 offsetof(struct njata32_dma_page, dp_sg[devno]);
152
153 error = bus_dmamap_create(sc->sc_dmat,
154 NJATA32_MAX_XFER, /* max total map size */
155 NJATA32_NUM_SG, /* max number of segments */
156 NJATA32_SGT_MAXSEGLEN, /* max size of a segment */
157 0, /* boundary */
158 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW,
159 &sc->sc_dev[devno].d_dmamap_xfer);
160 if (error) {
161 aprint_error("%s: failed to create DMA map "
162 "(error = %d)\n", NJATA32NAME(sc), error);
163 goto fail4;
164 }
165 }
166
167 /* device properties */
168 sc->sc_wdcdev.sc_atac.atac_cap =
169 ATAC_CAP_DATA16 | ATAC_CAP_DATA32 | ATAC_CAP_PIOBM;
170 sc->sc_wdcdev.irqack = njata32_irqack;
171 sc->sc_wdcdev.sc_atac.atac_channels = sc->sc_wdc_chanarray;
172 sc->sc_wdcdev.sc_atac.atac_nchannels = NJATA32_NCHAN; /* 1 */
173 sc->sc_wdcdev.sc_atac.atac_pio_cap = NJATA32_MODE_MAX_PIO;
174 #if 0 /* ATA DMA is currently unused */
175 sc->sc_wdcdev.sc_atac.atac_dma_cap = NJATA32_MODE_MAX_DMA;
176 #endif
177 sc->sc_wdcdev.sc_atac.atac_set_modes = njata32_setup_channel;
178
179 /* DMA control functions */
180 sc->sc_wdcdev.dma_arg = sc;
181 sc->sc_wdcdev.dma_init = njata32_dma_init;
182 sc->sc_wdcdev.piobm_start = njata32_piobm_start;
183 sc->sc_wdcdev.dma_finish = njata32_dma_finish;
184 sc->sc_wdcdev.piobm_done = njata32_piobm_done;
185
186 sc->sc_wdcdev.cap |= WDC_CAPABILITY_NO_EXTRA_RESETS;
187
188 sc->sc_wdcdev.regs = wdr = &sc->sc_wdc_regs;
189
190 /* only one channel */
191 sc->sc_wdc_chanarray[0] = &sc->sc_ch[0].ch_ata_channel;
192 sc->sc_ch[0].ch_ata_channel.ch_channel = 0;
193 sc->sc_ch[0].ch_ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac;
194 sc->sc_wdcdev.wdc_maxdrives = 2; /* max number of drives per channel */
195
196 /* map ATA registers */
197 for (i = 0; i < WDC_NREG; i++) {
198 if (bus_space_subregion(NJATA32_REGT(sc), NJATA32_REGH(sc),
199 NJATA32_OFFSET_WDCREGS + i,
200 i == wd_data ? 4 : 1, &wdr->cmd_iohs[i]) != 0) {
201 aprint_error("%s: couldn't subregion cmd regs\n",
202 NJATA32NAME(sc));
203 goto fail4;
204 }
205 }
206 wdc_init_shadow_regs(wdr);
207 wdr->data32iot = NJATA32_REGT(sc);
208 wdr->data32ioh = wdr->cmd_iohs[wd_data];
209
210 /* map ATA ctl reg */
211 wdr->ctl_iot = NJATA32_REGT(sc);
212 if (bus_space_subregion(NJATA32_REGT(sc), NJATA32_REGH(sc),
213 NJATA32_REG_WD_ALTSTATUS, 1, &wdr->ctl_ioh) != 0) {
214 aprint_error("%s: couldn't subregion ctl regs\n",
215 NJATA32NAME(sc));
216 goto fail4;
217 }
218
219 sc->sc_flags |= NJATA32_CMDPG_MAPPED;
220
221 /* use flags value as busmaster wait */
222 if ((sc->sc_atawait =
223 (uint8_t)device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags))
224 aprint_normal("%s: ATA wait = %#x\n",
225 NJATA32NAME(sc), sc->sc_atawait);
226
227 njata32_init(sc, cold);
228
229 wdcattach(&sc->sc_ch[0].ch_ata_channel);
230
231 return;
232
233 /*
234 * cleanup
235 */
236 fail4: while (--devno >= 0) {
237 bus_dmamap_destroy(sc->sc_dmat,
238 sc->sc_dev[devno].d_dmamap_xfer);
239 }
240 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap_sgt);
241 fail3: bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap_sgt);
242 fail2: bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_sgtpg,
243 sizeof(struct njata32_dma_page));
244 fail1: bus_dmamem_free(sc->sc_dmat, &sc->sc_sgt_seg, sc->sc_sgt_nsegs);
245 }
246
247 int
njata32_detach(struct njata32_softc * sc,int flags)248 njata32_detach(struct njata32_softc *sc, int flags)
249 {
250 int rv, devno;
251
252 if (sc->sc_flags & NJATA32_CMDPG_MAPPED) {
253 if ((rv = wdcdetach(sc->sc_wdcdev.sc_atac.atac_dev, flags)))
254 return rv;
255
256 /* free DMA resource */
257 for (devno = 0; devno < NJATA32_NUM_DEV; devno++) {
258 bus_dmamap_destroy(sc->sc_dmat,
259 sc->sc_dev[devno].d_dmamap_xfer);
260 }
261 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap_sgt);
262 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap_sgt);
263 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_sgtpg,
264 sizeof(struct njata32_dma_page));
265 bus_dmamem_free(sc->sc_dmat, &sc->sc_sgt_seg, sc->sc_sgt_nsegs);
266 }
267
268 return 0;
269 }
270
271 static void
njata32_irqack(struct ata_channel * chp)272 njata32_irqack(struct ata_channel *chp)
273 {
274 struct njata32_softc *sc = (void *)chp->ch_atac;
275
276 /* disable busmaster */
277 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
278 NJATA32_REG_BM, NJATA32_BM_WAIT0);
279 }
280
281 static void
njata32_clearirq(struct ata_channel * chp,int irq)282 njata32_clearirq(struct ata_channel *chp, int irq)
283 {
284 struct njata32_softc *sc = (void *)chp->ch_atac;
285
286 aprint_error("%s: unhandled intr: irq %#x, bm %#x, ",
287 NJATA32NAME(sc), irq,
288 bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
289 NJATA32_REG_BM));
290
291 /* disable busmaster */
292 njata32_irqack(chp);
293
294 /* clear device interrupt */
295 aprint_normal("err %#x, seccnt %#x, cyl %#x, sdh %#x, ",
296 bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
297 NJATA32_REG_WD_ERROR),
298 bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
299 NJATA32_REG_WD_SECCNT),
300 bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
301 NJATA32_REG_WD_CYL_LO) |
302 (bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
303 NJATA32_REG_WD_CYL_HI) << 8),
304 bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
305 NJATA32_REG_WD_SDH));
306 aprint_normal("status %#x\n",
307 bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
308 NJATA32_REG_WD_STATUS));
309 }
310
311 static void
njata32_setup_channel(struct ata_channel * chp)312 njata32_setup_channel(struct ata_channel *chp)
313 {
314 struct njata32_softc *sc = (void *)chp->ch_atac;
315 struct ata_drive_datas *drvp;
316 int drive;
317 uint8_t mode;
318
319 KASSERT(chp->ch_ndrives != 0);
320
321 sc->sc_timing_pio = 0;
322 #if 0 /* ATA DMA is currently unused */
323 sc->sc_timing_dma = 0;
324 #endif
325
326 for (drive = 0; drive < chp->ch_ndrives; drive++) {
327 drvp = &chp->ch_drive[drive];
328 if (drvp->drive_type == ATA_DRIVET_NONE)
329 continue; /* no drive */
330
331 #if 0 /* ATA DMA is currently unused */
332 if ((drvp->drive_flags & ATA_DRIVE_DMA) != 0) {
333 /*
334 * Multiword DMA
335 */
336 if ((mode = drvp->DMA_mode) > NJATA32_MODE_MAX_DMA)
337 mode = NJATA32_MODE_MAX_DMA;
338 if (sc->sc_timing_dma < njata32_timing_dma[mode])
339 sc->sc_timing_dma = njata32_timing_dma[mode];
340 }
341 #endif
342 /*
343 * PIO
344 */
345 if ((mode = drvp->PIO_mode) > NJATA32_MODE_MAX_PIO)
346 mode = NJATA32_MODE_MAX_PIO;
347 if (sc->sc_timing_pio < njata32_timing_pio[mode])
348 sc->sc_timing_pio = njata32_timing_pio[mode];
349 }
350
351 sc->sc_timing_pio += sc->sc_atawait;
352
353 /* set timing for PIO */
354 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
355 NJATA32_REG_TIMING, sc->sc_timing_pio);
356 }
357
358 /*
359 * map DMA buffer
360 */
361 int
njata32_dma_init(void * v,int channel,int drive,void * databuf,size_t datalen,int flags)362 njata32_dma_init(void *v, int channel, int drive, void *databuf,
363 size_t datalen, int flags)
364 {
365 struct njata32_softc *sc = v;
366 int error;
367 struct njata32_device *dev = &sc->sc_dev[drive];
368
369 KASSERT(channel == 0);
370 KASSERT((dev->d_flags & NJATA32_DEV_DMA_MAPPED) == 0);
371 KASSERT((dev->d_flags & NJATA32_DEV_DMA_STARTED) == 0);
372
373 KASSERT(flags & (WDC_DMA_PIOBM_ATA | WDC_DMA_PIOBM_ATAPI));
374
375 /* use PIO for short transfer */
376 if (datalen < 64 /* needs tune */) {
377 DPRINTF(("%s: njata32_dma_init: short transfer (%u)\n",
378 NJATA32NAME(sc), (unsigned)datalen));
379 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
380 NJATA32_REG_TIMING, sc->sc_timing_pio);
381 return EINVAL;
382 }
383
384 /* use PIO for unaligned transfer (word alignment seems OK) */
385 if (((uintptr_t)databuf & 1) || (datalen & 1)) {
386 DPRINTF(("%s: njata32_dma_init: unaligned: buf %p, len %u\n",
387 NJATA32NAME(sc), databuf, (unsigned)datalen));
388 return EINVAL;
389 }
390
391 DPRINTF(("%s: njata32_dma_init: %s: databuf %p, datalen %u\n",
392 NJATA32NAME(sc), (flags & WDC_DMA_READ) ? "read" : "write",
393 databuf, (unsigned)datalen));
394
395 error = bus_dmamap_load(sc->sc_dmat, dev->d_dmamap_xfer,
396 databuf, datalen, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING |
397 ((flags & WDC_DMA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE));
398 if (error) {
399 printf("%s: load xfer failed, error %d\n",
400 NJATA32NAME(sc), error);
401 return error;
402 }
403
404 bus_dmamap_sync(sc->sc_dmat, dev->d_dmamap_xfer, 0,
405 dev->d_dmamap_xfer->dm_mapsize,
406 (flags & WDC_DMA_READ) ?
407 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
408
409 dev->d_flags =
410 ((flags & WDC_DMA_READ) ? NJATA32_DEV_DMA_READ : 0) |
411 ((flags & WDC_DMA_PIOBM_ATAPI) ? NJATA32_DEV_DMA_ATAPI : 0) |
412 NJATA32_DEV_DMA_MAPPED;
413
414 return 0;
415 }
416
417 /*
418 * start DMA
419 *
420 * top: databuf + skip
421 * size: xferlen
422 */
423 void
njata32_piobm_start(void * v,int channel,int drive,int skip,int xferlen,int flags)424 njata32_piobm_start(void *v, int channel, int drive,
425 int skip, int xferlen, int flags)
426 {
427 struct njata32_softc *sc = v;
428 struct njata32_device *dev = &sc->sc_dev[drive];
429 int i, nsegs, seglen;
430 uint8_t bmreg;
431
432 DPRINTF(("%s: njata32_piobm_start: ch%d, dv%d, skip %d, xferlen %d\n",
433 NJATA32NAME(sc), channel, drive, skip, xferlen));
434
435 KASSERT(channel == 0);
436 KASSERT(dev->d_flags & NJATA32_DEV_DMA_MAPPED);
437 KASSERT((dev->d_flags & NJATA32_DEV_DMA_STARTED) == 0);
438
439 /*
440 * create scatter/gather table
441 * XXX this code may be slow
442 */
443 for (i = nsegs = 0;
444 i < dev->d_dmamap_xfer->dm_nsegs && xferlen > 0; i++) {
445 if (dev->d_dmamap_xfer->dm_segs[i].ds_len <= skip) {
446 skip -= dev->d_dmamap_xfer->dm_segs[i].ds_len;
447 continue;
448 }
449
450 seglen = dev->d_dmamap_xfer->dm_segs[i].ds_len - skip;
451 if (seglen > xferlen)
452 seglen = xferlen;
453
454 dev->d_sgt[nsegs].sg_addr =
455 htole32(dev->d_dmamap_xfer->dm_segs[i].ds_addr + skip);
456 dev->d_sgt[nsegs].sg_len = htole32(seglen);
457
458 xferlen -= seglen;
459 nsegs++;
460 skip = 0;
461 }
462 sc->sc_piobm_nsegs = nsegs;
463 /* end mark */
464 dev->d_sgt[nsegs - 1].sg_len |= htole32(NJATA32_SGT_ENDMARK);
465
466 #ifdef DIAGNOSTIC
467 if (xferlen)
468 panic("%s: njata32_piobm_start: xferlen residue %d\n",
469 NJATA32NAME(sc), xferlen);
470 #endif
471
472 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_sgt,
473 (char *)dev->d_sgt - (char *)sc->sc_sgtpg,
474 sizeof(struct njata32_sgtable) * nsegs,
475 BUS_DMASYNC_PREWRITE);
476
477 /* set timing for PIO */
478 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
479 NJATA32_REG_TIMING, sc->sc_timing_pio);
480
481 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), NJATA32_REG_IOBM,
482 NJATA32_IOBM_DEFAULT);
483 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), NJATA32_REG_AS,
484 NJATA32_AS_WAIT0);
485
486 /*
487 * interrupt configuration
488 */
489 if ((dev->d_flags & (NJATA32_DEV_DMA_READ | NJATA32_DEV_DMA_ATAPI)) ==
490 NJATA32_DEV_DMA_READ) {
491 /*
492 * ATA piobm read is executed while device interrupt is active,
493 * so disable device interrupt here
494 */
495 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
496 NJATA32_REG_IRQ_SELECT, NJATA32_IRQ_XFER);
497 }
498
499 /* enable scatter/gather busmaster transfer */
500 bmreg = NJATA32_BM_EN | NJATA32_BM_SG | NJATA32_BM_WAIT0 |
501 ((dev->d_flags & NJATA32_DEV_DMA_READ) ? NJATA32_BM_RD : 0);
502 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), NJATA32_REG_BM,
503 bmreg);
504
505 /* load scatter/gather table */
506 bus_space_write_4(NJATA32_REGT(sc), NJATA32_REGH(sc),
507 NJATA32_REG_DMAADDR, dev->d_sgt_dma);
508 bus_space_write_4(NJATA32_REGT(sc), NJATA32_REGH(sc),
509 NJATA32_REG_DMALENGTH, sizeof(struct njata32_sgtable) * nsegs);
510
511 /* start transfer */
512 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), NJATA32_REG_BM,
513 (bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
514 NJATA32_REG_BM)
515 & ~(NJATA32_BM_RD|NJATA32_BM_SG|NJATA32_BM_WAIT_MASK)) |
516 bmreg | NJATA32_BM_GO);
517
518 sc->sc_devflags = dev->d_flags;
519 if (flags & WDC_PIOBM_XFER_IRQ)
520 sc->sc_devflags |= NJATA32_DEV_XFER_INTR;
521 #ifdef DIAGNOSTIC
522 dev->d_flags |= NJATA32_DEV_DMA_STARTED;
523 #endif
524 }
525
526 /*
527 * end of DMA
528 */
529 int
njata32_dma_finish(void * v,int channel,int drive,int force)530 njata32_dma_finish(void *v, int channel, int drive,
531 int force)
532 {
533 struct njata32_softc *sc = v;
534 struct njata32_device *dev = &sc->sc_dev[drive];
535 int bm;
536 int error = 0;
537
538 DPRINTF(("%s: njata32_dma_finish: bm = %#x\n", NJATA32NAME(sc),
539 bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
540 NJATA32_REG_BM)));
541
542 KASSERT(channel == 0);
543 KASSERT(dev->d_flags & NJATA32_DEV_DMA_MAPPED);
544 KASSERT(dev->d_flags & NJATA32_DEV_DMA_STARTED);
545
546 bm = bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
547 NJATA32_REG_BM);
548
549 #ifdef NJATA32_DEBUG
550 printf("%s: irq %#x, bm %#x, 18 %#x, 1c %#x\n", NJATA32NAME(sc),
551 bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
552 NJATA32_REG_IRQ_STAT),
553 bm,
554 bus_space_read_4(NJATA32_REGT(sc), NJATA32_REGH(sc), 0x18),
555 bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc), 0x1c));
556 #endif
557
558 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_sgt,
559 (char *)dev->d_sgt - (char *)sc->sc_sgtpg,
560 sizeof(struct njata32_sgtable) * sc->sc_piobm_nsegs,
561 BUS_DMASYNC_POSTWRITE);
562
563 /* check if DMA is active */
564 if (bm & NJATA32_BM_GO) {
565 error = WDC_DMAST_NOIRQ;
566
567 switch (force) {
568 case WDC_DMAEND_END:
569 return error;
570
571 case WDC_DMAEND_ABRT:
572 printf("%s: aborting DMA\n", NJATA32NAME(sc));
573 break;
574 }
575 }
576
577 /*
578 * ???
579 * For unknown reason, PIOBM transfer sometimes fails in the middle,
580 * in which case the bit #7 of BM register becomes 0.
581 * Increasing the wait value seems to improve the situation.
582 *
583 * XXX
584 * PIO transfer may also fail, but it seems it can't be detected.
585 */
586 if ((bm & NJATA32_BM_DONE) == 0) {
587 error |= WDC_DMAST_ERR;
588 printf("%s: busmaster error", NJATA32NAME(sc));
589 if (sc->sc_atawait < 0x11) {
590 if ((sc->sc_atawait & 0xf) == 0)
591 sc->sc_atawait++;
592 else
593 sc->sc_atawait += 0x10;
594 printf(", new ATA wait = %#x", sc->sc_atawait);
595 njata32_setup_channel(&sc->sc_ch[0].ch_ata_channel);
596 }
597 printf("\n");
598 }
599
600 /* stop command */
601 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), NJATA32_REG_AS,
602 NJATA32_AS_WAIT0);
603 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc), NJATA32_REG_BM,
604 NJATA32_BM_WAIT0);
605
606 /* set timing for PIO */
607 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
608 NJATA32_REG_TIMING, sc->sc_timing_pio);
609
610 /*
611 * reenable device interrupt in case it was disabled for
612 * this transfer
613 */
614 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
615 NJATA32_REG_IRQ_SELECT, NJATA32_IRQ_XFER | NJATA32_IRQ_DEV);
616
617 #if 1 /* should be? */
618 if ((sc->sc_devflags & NJATA32_DEV_GOT_XFER_INTR) == 0)
619 error |= WDC_DMAST_ERR;
620 #endif
621 sc->sc_devflags = 0;
622
623 #ifdef DIAGNOSTIC
624 dev->d_flags &= ~NJATA32_DEV_DMA_STARTED;
625 #endif
626
627 return error;
628 }
629
630 /*
631 * unmap DMA buffer
632 */
633 void
njata32_piobm_done(void * v,int channel,int drive)634 njata32_piobm_done(void *v, int channel, int drive)
635 {
636 struct njata32_softc *sc = v;
637 struct njata32_device *dev = &sc->sc_dev[drive];
638
639 DPRINTF(("%s: njata32_piobm_done: ch%d dv%d\n",
640 NJATA32NAME(sc), channel, drive));
641
642 KASSERT(channel == 0);
643 KASSERT(dev->d_flags & NJATA32_DEV_DMA_MAPPED);
644 KASSERT((dev->d_flags & NJATA32_DEV_DMA_STARTED) == 0);
645
646 /* unload dma map */
647 bus_dmamap_sync(sc->sc_dmat, dev->d_dmamap_xfer,
648 0, dev->d_dmamap_xfer->dm_mapsize,
649 (dev->d_flags & NJATA32_DEV_DMA_READ) ?
650 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
651
652 bus_dmamap_unload(sc->sc_dmat, dev->d_dmamap_xfer);
653 dev->d_flags &= ~NJATA32_DEV_DMA_MAPPED;
654 }
655
656 int
njata32_intr(void * arg)657 njata32_intr(void *arg)
658 {
659 struct njata32_softc *sc = arg;
660 struct ata_channel *chp;
661 int irq;
662
663 irq = bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
664 NJATA32_REG_IRQ_STAT);
665 if ((irq & (NJATA32_IRQ_XFER | NJATA32_IRQ_DEV)) == 0)
666 return 0; /* not mine */
667
668 DPRINTF(("%s: njata32_intr: irq = %#x, altstatus = %#x\n",
669 NJATA32NAME(sc), irq,
670 bus_space_read_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
671 NJATA32_REG_WD_ALTSTATUS)));
672
673 chp = &sc->sc_ch[0].ch_ata_channel;
674
675 if (irq & NJATA32_IRQ_XFER)
676 sc->sc_devflags |= NJATA32_DEV_GOT_XFER_INTR;
677
678 if ((irq & (NJATA32_IRQ_XFER | NJATA32_IRQ_DEV)) == NJATA32_IRQ_XFER &&
679 (sc->sc_devflags & NJATA32_DEV_XFER_INTR) == 0) {
680 /*
681 * transfer done, wait for device interrupt
682 */
683 bus_space_write_1(NJATA32_REGT(sc), NJATA32_REGH(sc),
684 NJATA32_REG_BM, NJATA32_BM_WAIT0);
685 return 1;
686 }
687
688 /*
689 * If both transfer done interrupt and device interrupt are
690 * active for ATAPI transfer, call wdcintr() twice.
691 */
692 if ((sc->sc_devflags & NJATA32_DEV_DMA_ATAPI) &&
693 (irq & (NJATA32_IRQ_XFER | NJATA32_IRQ_DEV)) ==
694 (NJATA32_IRQ_XFER | NJATA32_IRQ_DEV) &&
695 (sc->sc_devflags & NJATA32_DEV_XFER_INTR)) {
696 if (wdcintr(chp) == 0) {
697 njata32_clearirq(&sc->sc_ch[0].ch_ata_channel, irq);
698 }
699 }
700
701 if (wdcintr(chp) == 0) {
702 njata32_clearirq(&sc->sc_ch[0].ch_ata_channel, irq);
703 }
704
705 return 1;
706 }
707