1 /* $NetBSD: if_tl.c,v 1.126 2024/06/29 12:11:12 riastradh Exp $ */
2
3 /*
4 * Copyright (c) 1997 Manuel Bouyer. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27 /*
28 * Texas Instruments ThunderLAN ethernet controller
29 * ThunderLAN Programmer's Guide (TI Literature Number SPWU013A)
30 * available from www.ti.com
31 */
32
33 #include <sys/cdefs.h>
34 __KERNEL_RCSID(0, "$NetBSD: if_tl.c,v 1.126 2024/06/29 12:11:12 riastradh Exp $");
35
36 #undef TLDEBUG
37 #define TL_PRIV_STATS
38 #undef TLDEBUG_RX
39 #undef TLDEBUG_TX
40 #undef TLDEBUG_ADDR
41
42 #include "opt_inet.h"
43
44 #include <sys/param.h>
45 #include <sys/systm.h>
46 #include <sys/mbuf.h>
47 #include <sys/protosw.h>
48 #include <sys/socket.h>
49 #include <sys/ioctl.h>
50 #include <sys/errno.h>
51 #include <sys/malloc.h>
52 #include <sys/kernel.h>
53 #include <sys/proc.h> /* only for declaration of wakeup() used by vm.h */
54 #include <sys/device.h>
55
56 #include <net/if.h>
57 #include <net/if_media.h>
58 #include <net/if_types.h>
59 #include <net/if_dl.h>
60 #include <net/route.h>
61 #include <net/bpf.h>
62
63 #include <sys/rndsource.h>
64
65 #ifdef INET
66 #include <netinet/in.h>
67 #include <netinet/in_systm.h>
68 #include <netinet/in_var.h>
69 #include <netinet/ip.h>
70 #endif
71
72
73 #if defined(__NetBSD__)
74 #include <net/if_ether.h>
75 #if defined(INET)
76 #include <netinet/if_inarp.h>
77 #endif
78
79 #include <sys/bus.h>
80 #include <sys/intr.h>
81
82 #include <dev/pci/pcireg.h>
83 #include <dev/pci/pcivar.h>
84 #include <dev/pci/pcidevs.h>
85
86 #include <dev/i2c/i2cvar.h>
87 #include <dev/i2c/i2c_bitbang.h>
88 #include <dev/i2c/at24cxxvar.h>
89
90 #include <dev/mii/mii.h>
91 #include <dev/mii/miivar.h>
92
93 #include <dev/mii/tlphyvar.h>
94
95 #include <dev/pci/if_tlregs.h>
96 #include <dev/pci/if_tlvar.h>
97 #endif /* __NetBSD__ */
98
99 /* number of transmit/receive buffers */
100 #ifndef TL_NBUF
101 #define TL_NBUF 32
102 #endif
103
104 static int tl_pci_match(device_t, cfdata_t, void *);
105 static void tl_pci_attach(device_t, device_t, void *);
106 static int tl_intr(void *);
107
108 static int tl_ifioctl(struct ifnet *, ioctl_cmd_t, void *);
109 static void tl_ifwatchdog(struct ifnet *);
110 static bool tl_shutdown(device_t, int);
111
112 static void tl_ifstart(struct ifnet *);
113 static void tl_reset(tl_softc_t *);
114 static int tl_init(struct ifnet *);
115 static void tl_stop(struct ifnet *, int);
116 static void tl_restart(void *);
117 static int tl_add_RxBuff(tl_softc_t *, struct Rx_list *, struct mbuf *);
118 static void tl_read_stats(tl_softc_t *);
119 static void tl_ticks(void *);
120 static int tl_multicast_hash(uint8_t *);
121 static void tl_addr_filter(tl_softc_t *);
122
123 static uint32_t tl_intreg_read(tl_softc_t *, uint32_t);
124 static void tl_intreg_write(tl_softc_t *, uint32_t, uint32_t);
125 static uint8_t tl_intreg_read_byte(tl_softc_t *, uint32_t);
126 static void tl_intreg_write_byte(tl_softc_t *, uint32_t, uint8_t);
127
128 void tl_mii_sync(struct tl_softc *);
129 void tl_mii_sendbits(struct tl_softc *, uint32_t, int);
130
131
132 #if defined(TLDEBUG_RX)
133 static void ether_printheader(struct ether_header *);
134 #endif
135
136 int tl_mii_read(device_t, int, int, uint16_t *);
137 int tl_mii_write(device_t, int, int, uint16_t);
138
139 void tl_statchg(struct ifnet *);
140
141 /* I2C glue */
142 static int tl_i2c_send_start(void *, int);
143 static int tl_i2c_send_stop(void *, int);
144 static int tl_i2c_initiate_xfer(void *, i2c_addr_t, int);
145 static int tl_i2c_read_byte(void *, uint8_t *, int);
146 static int tl_i2c_write_byte(void *, uint8_t, int);
147
148 /* I2C bit-bang glue */
149 static void tl_i2cbb_set_bits(void *, uint32_t);
150 static void tl_i2cbb_set_dir(void *, uint32_t);
151 static uint32_t tl_i2cbb_read(void *);
152 static const struct i2c_bitbang_ops tl_i2cbb_ops = {
153 tl_i2cbb_set_bits,
154 tl_i2cbb_set_dir,
155 tl_i2cbb_read,
156 {
157 TL_NETSIO_EDATA, /* SDA */
158 TL_NETSIO_ECLOCK, /* SCL */
159 TL_NETSIO_ETXEN, /* SDA is output */
160 0, /* SDA is input */
161 }
162 };
163
164 static inline void netsio_clr(tl_softc_t *, uint8_t);
165 static inline void netsio_set(tl_softc_t *, uint8_t);
166 static inline uint8_t netsio_read(tl_softc_t *, uint8_t);
167
168 static inline void
netsio_clr(tl_softc_t * sc,uint8_t bits)169 netsio_clr(tl_softc_t *sc, uint8_t bits)
170 {
171
172 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio,
173 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & (~bits));
174 }
175
176 static inline void
netsio_set(tl_softc_t * sc,uint8_t bits)177 netsio_set(tl_softc_t *sc, uint8_t bits)
178 {
179
180 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio,
181 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) | bits);
182 }
183
184 static inline uint8_t
netsio_read(tl_softc_t * sc,uint8_t bits)185 netsio_read(tl_softc_t *sc, uint8_t bits)
186 {
187
188 return tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & bits;
189 }
190
191 CFATTACH_DECL_NEW(tl, sizeof(tl_softc_t),
192 tl_pci_match, tl_pci_attach, NULL, NULL);
193
194 static const struct tl_product_desc tl_compaq_products[] = {
195 { PCI_PRODUCT_COMPAQ_N100TX, TLPHY_MEDIA_NO_10_T,
196 "Compaq Netelligent 10/100 TX" },
197 { PCI_PRODUCT_COMPAQ_INT100TX, TLPHY_MEDIA_NO_10_T,
198 "Integrated Compaq Netelligent 10/100 TX" },
199 { PCI_PRODUCT_COMPAQ_N10T, TLPHY_MEDIA_10_5,
200 "Compaq Netelligent 10 T" },
201 { PCI_PRODUCT_COMPAQ_N10T2, TLPHY_MEDIA_10_2,
202 "Compaq Netelligent 10 T/2 UTP/Coax" },
203 { PCI_PRODUCT_COMPAQ_IntNF3P, TLPHY_MEDIA_10_2,
204 "Compaq Integrated NetFlex 3/P" },
205 { PCI_PRODUCT_COMPAQ_IntPL100TX, TLPHY_MEDIA_10_2 |TLPHY_MEDIA_NO_10_T,
206 "Compaq ProLiant Integrated Netelligent 10/100 TX" },
207 { PCI_PRODUCT_COMPAQ_DPNet100TX, TLPHY_MEDIA_10_5 |TLPHY_MEDIA_NO_10_T,
208 "Compaq Dual Port Netelligent 10/100 TX" },
209 { PCI_PRODUCT_COMPAQ_DP4000, TLPHY_MEDIA_10_5 | TLPHY_MEDIA_NO_10_T,
210 "Compaq Deskpro 4000 5233MMX" },
211 { PCI_PRODUCT_COMPAQ_NF3P_BNC, TLPHY_MEDIA_10_2,
212 "Compaq NetFlex 3/P w/ BNC" },
213 { PCI_PRODUCT_COMPAQ_NF3P, TLPHY_MEDIA_10_5,
214 "Compaq NetFlex 3/P" },
215 { 0, 0, NULL },
216 };
217
218 static const struct tl_product_desc tl_ti_products[] = {
219 /*
220 * Built-in Ethernet on the TI TravelMate 5000
221 * docking station; better product description?
222 */
223 { PCI_PRODUCT_TI_TLAN, 0,
224 "Texas Instruments ThunderLAN" },
225 { 0, 0, NULL },
226 };
227
228 struct tl_vendor_desc {
229 uint32_t tv_vendor;
230 const struct tl_product_desc *tv_products;
231 };
232
233 const struct tl_vendor_desc tl_vendors[] = {
234 { PCI_VENDOR_COMPAQ, tl_compaq_products },
235 { PCI_VENDOR_TI, tl_ti_products },
236 { 0, NULL },
237 };
238
239 static const struct tl_product_desc *tl_lookup_product(uint32_t);
240
241 static const struct tl_product_desc *
tl_lookup_product(uint32_t id)242 tl_lookup_product(uint32_t id)
243 {
244 const struct tl_product_desc *tp;
245 const struct tl_vendor_desc *tv;
246
247 for (tv = tl_vendors; tv->tv_products != NULL; tv++)
248 if (PCI_VENDOR(id) == tv->tv_vendor)
249 break;
250
251 if ((tp = tv->tv_products) == NULL)
252 return NULL;
253
254 for (; tp->tp_desc != NULL; tp++)
255 if (PCI_PRODUCT(id) == tp->tp_product)
256 break;
257
258 if (tp->tp_desc == NULL)
259 return NULL;
260
261 return tp;
262 }
263
264 static int
tl_pci_match(device_t parent,cfdata_t cf,void * aux)265 tl_pci_match(device_t parent, cfdata_t cf, void *aux)
266 {
267 struct pci_attach_args *pa = (struct pci_attach_args *)aux;
268
269 if (tl_lookup_product(pa->pa_id) != NULL)
270 return 1;
271
272 return 0;
273 }
274
275 static void
tl_pci_attach(device_t parent,device_t self,void * aux)276 tl_pci_attach(device_t parent, device_t self, void *aux)
277 {
278 tl_softc_t *sc = device_private(self);
279 struct pci_attach_args * const pa = (struct pci_attach_args *)aux;
280 const struct tl_product_desc *tp;
281 struct ifnet * const ifp = &sc->tl_if;
282 struct mii_data * const mii = &sc->tl_mii;
283 bus_space_tag_t iot, memt;
284 bus_space_handle_t ioh, memh;
285 pci_intr_handle_t intrhandle;
286 const char *intrstr;
287 int ioh_valid, memh_valid;
288 int reg_io, reg_mem;
289 pcireg_t reg10, reg14;
290 pcireg_t csr;
291 char intrbuf[PCI_INTRSTR_LEN];
292
293 sc->sc_dev = self;
294 aprint_normal("\n");
295
296 callout_init(&sc->tl_tick_ch, 0);
297 callout_init(&sc->tl_restart_ch, 0);
298
299 tp = tl_lookup_product(pa->pa_id);
300 if (tp == NULL)
301 panic("%s: impossible", __func__);
302 sc->tl_product = tp;
303
304 /*
305 * Map the card space. First we have to find the I/O and MEM
306 * registers. I/O is supposed to be at 0x10, MEM at 0x14,
307 * but some boards (Compaq Netflex 3/P PCI) seem to have it reversed.
308 * The ThunderLAN manual is not consistent about this either (there
309 * are both cases in code examples).
310 */
311 reg10 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x10);
312 reg14 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x14);
313 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_IO)
314 reg_io = 0x10;
315 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_IO)
316 reg_io = 0x14;
317 else
318 reg_io = 0;
319 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_MEM)
320 reg_mem = 0x10;
321 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_MEM)
322 reg_mem = 0x14;
323 else
324 reg_mem = 0;
325
326 if (reg_io != 0)
327 ioh_valid = (pci_mapreg_map(pa, reg_io, PCI_MAPREG_TYPE_IO,
328 0, &iot, &ioh, NULL, NULL) == 0);
329 else
330 ioh_valid = 0;
331 if (reg_mem != 0)
332 memh_valid = (pci_mapreg_map(pa, PCI_CBMA,
333 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT,
334 0, &memt, &memh, NULL, NULL) == 0);
335 else
336 memh_valid = 0;
337
338 if (ioh_valid) {
339 sc->tl_bustag = iot;
340 sc->tl_bushandle = ioh;
341 } else if (memh_valid) {
342 sc->tl_bustag = memt;
343 sc->tl_bushandle = memh;
344 } else {
345 aprint_error_dev(self, "unable to map device registers\n");
346 return;
347 }
348 sc->tl_dmatag = pa->pa_dmat;
349
350 /* Enable the device. */
351 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
352 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
353 csr | PCI_COMMAND_MASTER_ENABLE);
354
355 aprint_normal_dev(self, "%s\n", tp->tp_desc);
356
357 tl_reset(sc);
358
359 /* fill in the i2c tag */
360 iic_tag_init(&sc->sc_i2c);
361 sc->sc_i2c.ic_cookie = sc;
362 sc->sc_i2c.ic_send_start = tl_i2c_send_start;
363 sc->sc_i2c.ic_send_stop = tl_i2c_send_stop;
364 sc->sc_i2c.ic_initiate_xfer = tl_i2c_initiate_xfer;
365 sc->sc_i2c.ic_read_byte = tl_i2c_read_byte;
366 sc->sc_i2c.ic_write_byte = tl_i2c_write_byte;
367
368 #ifdef TLDEBUG
369 aprint_debug_dev(self, "default values of INTreg: 0x%x\n",
370 tl_intreg_read(sc, TL_INT_Defaults));
371 #endif
372
373 /* read mac addr */
374 if (seeprom_bootstrap_read(&sc->sc_i2c, 0x50, 0x83, 256 /* 2kbit */,
375 sc->tl_enaddr, ETHER_ADDR_LEN)) {
376 aprint_error_dev(self, "error reading Ethernet address\n");
377 return;
378 }
379 aprint_normal_dev(self, "Ethernet address %s\n",
380 ether_sprintf(sc->tl_enaddr));
381
382 /* Map and establish interrupts */
383 if (pci_intr_map(pa, &intrhandle)) {
384 aprint_error_dev(self, "couldn't map interrupt\n");
385 return;
386 }
387 intrstr = pci_intr_string(pa->pa_pc, intrhandle, intrbuf,
388 sizeof(intrbuf));
389 sc->tl_if.if_softc = sc;
390 sc->tl_ih = pci_intr_establish_xname(pa->pa_pc, intrhandle, IPL_NET,
391 tl_intr, sc, device_xname(self));
392 if (sc->tl_ih == NULL) {
393 aprint_error_dev(self, "couldn't establish interrupt");
394 if (intrstr != NULL)
395 aprint_error(" at %s", intrstr);
396 aprint_error("\n");
397 return;
398 }
399 aprint_normal_dev(self, "interrupting at %s\n", intrstr);
400
401 /* init these pointers, so that tl_shutdown won't try to read them */
402 sc->Rx_list = NULL;
403 sc->Tx_list = NULL;
404
405 /* allocate DMA-safe memory for control structs */
406 if (bus_dmamem_alloc(sc->tl_dmatag, PAGE_SIZE, 0, PAGE_SIZE,
407 &sc->ctrl_segs, 1, &sc->ctrl_nsegs, BUS_DMA_NOWAIT) != 0 ||
408 bus_dmamem_map(sc->tl_dmatag, &sc->ctrl_segs,
409 sc->ctrl_nsegs, PAGE_SIZE, (void **)&sc->ctrl,
410 BUS_DMA_NOWAIT | BUS_DMA_COHERENT) != 0) {
411 aprint_error_dev(self, "can't allocate DMA memory for lists\n");
412 return;
413 }
414
415 /*
416 * Initialize our media structures and probe the MII.
417 *
418 * Note that we don't care about the media instance. We
419 * are expecting to have multiple PHYs on the 10/100 cards,
420 * and on those cards we exclude the internal PHY from providing
421 * 10baseT. By ignoring the instance, it allows us to not have
422 * to specify it on the command line when switching media.
423 */
424 mii->mii_ifp = ifp;
425 mii->mii_readreg = tl_mii_read;
426 mii->mii_writereg = tl_mii_write;
427 mii->mii_statchg = tl_statchg;
428 sc->tl_ec.ec_mii = mii;
429 ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange,
430 ether_mediastatus);
431 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 0);
432 if (LIST_FIRST(&mii->mii_phys) == NULL) {
433 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL);
434 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE);
435 } else
436 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO);
437
438 /*
439 * We can support 802.1Q VLAN-sized frames.
440 */
441 sc->tl_ec.ec_capabilities |= ETHERCAP_VLAN_MTU;
442
443 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ);
444 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
445 ifp->if_ioctl = tl_ifioctl;
446 ifp->if_start = tl_ifstart;
447 ifp->if_watchdog = tl_ifwatchdog;
448 ifp->if_init = tl_init;
449 ifp->if_stop = tl_stop;
450 ifp->if_timer = 0;
451 IFQ_SET_READY(&ifp->if_snd);
452 if_attach(ifp);
453 if_deferred_start_init(ifp, NULL);
454 ether_ifattach(&(sc)->tl_if, (sc)->tl_enaddr);
455
456 /*
457 * Add shutdown hook so that DMA is disabled prior to reboot.
458 * Not doing reboot before the driver initializes.
459 */
460 if (pmf_device_register1(self, NULL, NULL, tl_shutdown))
461 pmf_class_network_register(self, ifp);
462 else
463 aprint_error_dev(self, "couldn't establish power handler\n");
464
465 rnd_attach_source(&sc->rnd_source, device_xname(self),
466 RND_TYPE_NET, RND_FLAG_DEFAULT);
467 }
468
469 static void
tl_reset(tl_softc_t * sc)470 tl_reset(tl_softc_t *sc)
471 {
472 int i;
473
474 /* read stats */
475 if (sc->tl_if.if_flags & IFF_RUNNING) {
476 callout_stop(&sc->tl_tick_ch);
477 tl_read_stats(sc);
478 }
479 /* Reset adapter */
480 TL_HR_WRITE(sc, TL_HOST_CMD,
481 TL_HR_READ(sc, TL_HOST_CMD) | HOST_CMD_Ad_Rst);
482 DELAY(100000);
483 /* Disable interrupts */
484 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff);
485 /* setup aregs & hash */
486 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4)
487 tl_intreg_write(sc, i, 0);
488 #ifdef TLDEBUG_ADDR
489 printf("Areg & hash registers: \n");
490 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4)
491 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i));
492 #endif
493 /* Setup NetConfig */
494 tl_intreg_write(sc, TL_INT_NetConfig,
495 TL_NETCONFIG_1F | TL_NETCONFIG_1chn | TL_NETCONFIG_PHY_EN);
496 /* Bsize: accept default */
497 /* TX commit in Acommit: accept default */
498 /* Load Ld_tmr and Ld_thr */
499 /* Ld_tmr = 3 */
500 TL_HR_WRITE(sc, TL_HOST_CMD, 0x3 | HOST_CMD_LdTmr);
501 /* Ld_thr = 0 */
502 TL_HR_WRITE(sc, TL_HOST_CMD, 0x0 | HOST_CMD_LdThr);
503 /* Unreset MII */
504 netsio_set(sc, TL_NETSIO_NMRST);
505 DELAY(100000);
506 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE;
507 }
508
509 static bool
tl_shutdown(device_t self,int howto)510 tl_shutdown(device_t self, int howto)
511 {
512 tl_softc_t *sc = device_private(self);
513 struct ifnet *ifp = &sc->tl_if;
514
515 tl_stop(ifp, 1);
516
517 return true;
518 }
519
520 static void
tl_stop(struct ifnet * ifp,int disable)521 tl_stop(struct ifnet *ifp, int disable)
522 {
523 tl_softc_t *sc = ifp->if_softc;
524 struct Tx_list *Tx;
525 int i;
526
527 if ((ifp->if_flags & IFF_RUNNING) == 0)
528 return;
529 /* disable interrupts */
530 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff);
531 /* stop TX and RX channels */
532 TL_HR_WRITE(sc, TL_HOST_CMD,
533 HOST_CMD_STOP | HOST_CMD_RT | HOST_CMD_Nes);
534 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_STOP);
535 DELAY(100000);
536
537 /* stop statistics reading loop, read stats */
538 callout_stop(&sc->tl_tick_ch);
539 tl_read_stats(sc);
540
541 /* Down the MII. */
542 mii_down(&sc->tl_mii);
543
544 /* deallocate memory allocations */
545 if (sc->Rx_list) {
546 for (i = 0; i< TL_NBUF; i++) {
547 if (sc->Rx_list[i].m) {
548 bus_dmamap_unload(sc->tl_dmatag,
549 sc->Rx_list[i].m_dmamap);
550 m_freem(sc->Rx_list[i].m);
551 }
552 bus_dmamap_destroy(sc->tl_dmatag,
553 sc->Rx_list[i].m_dmamap);
554 sc->Rx_list[i].m = NULL;
555 }
556 free(sc->Rx_list, M_DEVBUF);
557 sc->Rx_list = NULL;
558 bus_dmamap_unload(sc->tl_dmatag, sc->Rx_dmamap);
559 bus_dmamap_destroy(sc->tl_dmatag, sc->Rx_dmamap);
560 sc->hw_Rx_list = NULL;
561 while ((Tx = sc->active_Tx) != NULL) {
562 Tx->hw_list->stat = 0;
563 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap);
564 bus_dmamap_destroy(sc->tl_dmatag, Tx->m_dmamap);
565 m_freem(Tx->m);
566 sc->active_Tx = Tx->next;
567 Tx->next = sc->Free_Tx;
568 sc->Free_Tx = Tx;
569 }
570 sc->last_Tx = NULL;
571 free(sc->Tx_list, M_DEVBUF);
572 sc->Tx_list = NULL;
573 bus_dmamap_unload(sc->tl_dmatag, sc->Tx_dmamap);
574 bus_dmamap_destroy(sc->tl_dmatag, sc->Tx_dmamap);
575 sc->hw_Tx_list = NULL;
576 }
577 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
578 ifp->if_timer = 0;
579 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE;
580 }
581
582 static void
tl_restart(void * v)583 tl_restart(void *v)
584 {
585
586 tl_init(v);
587 }
588
589 static int
tl_init(struct ifnet * ifp)590 tl_init(struct ifnet *ifp)
591 {
592 tl_softc_t *sc = ifp->if_softc;
593 int i, s, error;
594 bus_size_t boundary;
595 prop_number_t prop_boundary;
596 const char *errstring;
597 char *nullbuf;
598
599 s = splnet();
600 /* cancel any pending IO */
601 tl_stop(ifp, 1);
602 tl_reset(sc);
603 if ((sc->tl_if.if_flags & IFF_UP) == 0) {
604 splx(s);
605 return 0;
606 }
607 /* Set various register to reasonable value */
608 /* setup NetCmd in promisc mode if needed */
609 i = (ifp->if_flags & IFF_PROMISC) ? TL_NETCOMMAND_CAF : 0;
610 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd,
611 TL_NETCOMMAND_NRESET | TL_NETCOMMAND_NWRAP | i);
612 /* Max receive size : MCLBYTES */
613 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxL, MCLBYTES & 0xff);
614 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxH,
615 (MCLBYTES >> 8) & 0xff);
616
617 /* init MAC addr */
618 for (i = 0; i < ETHER_ADDR_LEN; i++)
619 tl_intreg_write_byte(sc, TL_INT_Areg0 + i , sc->tl_enaddr[i]);
620 /* add multicast filters */
621 tl_addr_filter(sc);
622 #ifdef TLDEBUG_ADDR
623 printf("Wrote Mac addr, Areg & hash registers are now: \n");
624 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4)
625 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i));
626 #endif
627
628 /* Pre-allocate receivers mbuf, make the lists */
629 sc->Rx_list = malloc(sizeof(struct Rx_list) * TL_NBUF, M_DEVBUF,
630 M_NOWAIT | M_ZERO);
631 sc->Tx_list = malloc(sizeof(struct Tx_list) * TL_NBUF, M_DEVBUF,
632 M_NOWAIT | M_ZERO);
633 if (sc->Rx_list == NULL || sc->Tx_list == NULL) {
634 errstring = "out of memory for lists";
635 error = ENOMEM;
636 goto bad;
637 }
638
639 /*
640 * Some boards (Set Engineering GFE) do not permit DMA transfers
641 * across page boundaries.
642 */
643 prop_boundary = prop_dictionary_get(device_properties(sc->sc_dev),
644 "tl-dma-page-boundary");
645 if (prop_boundary != NULL) {
646 KASSERT(prop_object_type(prop_boundary) == PROP_TYPE_NUMBER);
647 boundary
648 = (bus_size_t)prop_number_unsigned_value(prop_boundary);
649 } else {
650 boundary = 0;
651 }
652
653 error = bus_dmamap_create(sc->tl_dmatag,
654 sizeof(struct tl_Rx_list) * TL_NBUF, 1,
655 sizeof(struct tl_Rx_list) * TL_NBUF, 0, BUS_DMA_WAITOK,
656 &sc->Rx_dmamap);
657 if (error == 0)
658 error = bus_dmamap_create(sc->tl_dmatag,
659 sizeof(struct tl_Tx_list) * TL_NBUF, 1,
660 sizeof(struct tl_Tx_list) * TL_NBUF, boundary,
661 BUS_DMA_WAITOK, &sc->Tx_dmamap);
662 if (error == 0)
663 error = bus_dmamap_create(sc->tl_dmatag, ETHER_MIN_TX, 1,
664 ETHER_MIN_TX, boundary, BUS_DMA_WAITOK,
665 &sc->null_dmamap);
666 if (error) {
667 errstring = "can't allocate DMA maps for lists";
668 goto bad;
669 }
670 memset(sc->ctrl, 0, PAGE_SIZE);
671 sc->hw_Rx_list = (void *)sc->ctrl;
672 sc->hw_Tx_list =
673 (void *)(sc->ctrl + sizeof(struct tl_Rx_list) * TL_NBUF);
674 nullbuf = sc->ctrl + sizeof(struct tl_Rx_list) * TL_NBUF +
675 sizeof(struct tl_Tx_list) * TL_NBUF;
676 error = bus_dmamap_load(sc->tl_dmatag, sc->Rx_dmamap,
677 sc->hw_Rx_list, sizeof(struct tl_Rx_list) * TL_NBUF, NULL,
678 BUS_DMA_WAITOK);
679 if (error == 0)
680 error = bus_dmamap_load(sc->tl_dmatag, sc->Tx_dmamap,
681 sc->hw_Tx_list, sizeof(struct tl_Tx_list) * TL_NBUF, NULL,
682 BUS_DMA_WAITOK);
683 if (error == 0)
684 error = bus_dmamap_load(sc->tl_dmatag, sc->null_dmamap,
685 nullbuf, ETHER_MIN_TX, NULL, BUS_DMA_WAITOK);
686 if (error) {
687 errstring = "can't DMA map DMA memory for lists";
688 goto bad;
689 }
690 for (i = 0; i < TL_NBUF; i++) {
691 error = bus_dmamap_create(sc->tl_dmatag, MCLBYTES,
692 1, MCLBYTES, boundary, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW,
693 &sc->Rx_list[i].m_dmamap);
694 if (error == 0) {
695 error = bus_dmamap_create(sc->tl_dmatag, MCLBYTES,
696 TL_NSEG, MCLBYTES, boundary,
697 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW,
698 &sc->Tx_list[i].m_dmamap);
699 }
700 if (error) {
701 errstring = "can't allocate DMA maps for mbufs";
702 goto bad;
703 }
704 sc->Rx_list[i].hw_list = &sc->hw_Rx_list[i];
705 sc->Rx_list[i].hw_listaddr = sc->Rx_dmamap->dm_segs[0].ds_addr
706 + sizeof(struct tl_Rx_list) * i;
707 sc->Tx_list[i].hw_list = &sc->hw_Tx_list[i];
708 sc->Tx_list[i].hw_listaddr = sc->Tx_dmamap->dm_segs[0].ds_addr
709 + sizeof(struct tl_Tx_list) * i;
710 if (tl_add_RxBuff(sc, &sc->Rx_list[i], NULL) == 0) {
711 errstring = "out of mbuf for receive list";
712 error = ENOMEM;
713 goto bad;
714 }
715 if (i > 0) { /* chain the list */
716 sc->Rx_list[i - 1].next = &sc->Rx_list[i];
717 sc->hw_Rx_list[i - 1].fwd =
718 htole32(sc->Rx_list[i].hw_listaddr);
719 sc->Tx_list[i - 1].next = &sc->Tx_list[i];
720 }
721 }
722 sc->hw_Rx_list[TL_NBUF - 1].fwd = 0;
723 sc->Rx_list[TL_NBUF - 1].next = NULL;
724 sc->hw_Tx_list[TL_NBUF - 1].fwd = 0;
725 sc->Tx_list[TL_NBUF - 1].next = NULL;
726
727 sc->active_Rx = &sc->Rx_list[0];
728 sc->last_Rx = &sc->Rx_list[TL_NBUF - 1];
729 sc->active_Tx = sc->last_Tx = NULL;
730 sc->Free_Tx = &sc->Tx_list[0];
731 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0,
732 sizeof(struct tl_Rx_list) * TL_NBUF,
733 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
734 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0,
735 sizeof(struct tl_Tx_list) * TL_NBUF,
736 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
737 bus_dmamap_sync(sc->tl_dmatag, sc->null_dmamap, 0, ETHER_MIN_TX,
738 BUS_DMASYNC_PREWRITE);
739
740 /* set media */
741 if ((error = mii_mediachg(&sc->tl_mii)) == ENXIO)
742 error = 0;
743 else if (error != 0) {
744 errstring = "could not set media";
745 goto bad;
746 }
747
748 /* start ticks calls */
749 callout_reset(&sc->tl_tick_ch, hz, tl_ticks, sc);
750 /* write address of Rx list and enable interrupts */
751 TL_HR_WRITE(sc, TL_HOST_CH_PARM, sc->Rx_list[0].hw_listaddr);
752 TL_HR_WRITE(sc, TL_HOST_CMD,
753 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | HOST_CMD_IntOn);
754 sc->tl_if.if_flags |= IFF_RUNNING;
755 sc->tl_if.if_flags &= ~IFF_OACTIVE;
756 splx(s);
757 return 0;
758 bad:
759 printf("%s: %s\n", device_xname(sc->sc_dev), errstring);
760 splx(s);
761 return error;
762 }
763
764
765 static uint32_t
tl_intreg_read(tl_softc_t * sc,uint32_t reg)766 tl_intreg_read(tl_softc_t *sc, uint32_t reg)
767 {
768
769 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK);
770 return TL_HR_READ(sc, TL_HOST_DIO_DATA);
771 }
772
773 static uint8_t
tl_intreg_read_byte(tl_softc_t * sc,uint32_t reg)774 tl_intreg_read_byte(tl_softc_t *sc, uint32_t reg)
775 {
776
777 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR,
778 (reg & (~0x07)) & TL_HOST_DIOADR_MASK);
779 return TL_HR_READ_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x07));
780 }
781
782 static void
tl_intreg_write(tl_softc_t * sc,uint32_t reg,uint32_t val)783 tl_intreg_write(tl_softc_t *sc, uint32_t reg, uint32_t val)
784 {
785
786 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK);
787 TL_HR_WRITE(sc, TL_HOST_DIO_DATA, val);
788 }
789
790 static void
tl_intreg_write_byte(tl_softc_t * sc,uint32_t reg,uint8_t val)791 tl_intreg_write_byte(tl_softc_t *sc, uint32_t reg, uint8_t val)
792 {
793
794 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR,
795 (reg & (~0x03)) & TL_HOST_DIOADR_MASK);
796 TL_HR_WRITE_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x03), val);
797 }
798
799 void
tl_mii_sync(struct tl_softc * sc)800 tl_mii_sync(struct tl_softc *sc)
801 {
802 int i;
803
804 netsio_clr(sc, TL_NETSIO_MTXEN);
805 for (i = 0; i < 32; i++) {
806 netsio_clr(sc, TL_NETSIO_MCLK);
807 netsio_set(sc, TL_NETSIO_MCLK);
808 }
809 }
810
811 void
tl_mii_sendbits(struct tl_softc * sc,uint32_t data,int nbits)812 tl_mii_sendbits(struct tl_softc *sc, uint32_t data, int nbits)
813 {
814 int i;
815
816 netsio_set(sc, TL_NETSIO_MTXEN);
817 for (i = 1 << (nbits - 1); i; i = i >> 1) {
818 netsio_clr(sc, TL_NETSIO_MCLK);
819 netsio_read(sc, TL_NETSIO_MCLK);
820 if (data & i)
821 netsio_set(sc, TL_NETSIO_MDATA);
822 else
823 netsio_clr(sc, TL_NETSIO_MDATA);
824 netsio_set(sc, TL_NETSIO_MCLK);
825 netsio_read(sc, TL_NETSIO_MCLK);
826 }
827 }
828
829 int
tl_mii_read(device_t self,int phy,int reg,uint16_t * val)830 tl_mii_read(device_t self, int phy, int reg, uint16_t *val)
831 {
832 struct tl_softc *sc = device_private(self);
833 uint16_t data = 0;
834 int i, err;
835
836 /*
837 * Read the PHY register by manually driving the MII control lines.
838 */
839
840 tl_mii_sync(sc);
841 tl_mii_sendbits(sc, MII_COMMAND_START, 2);
842 tl_mii_sendbits(sc, MII_COMMAND_READ, 2);
843 tl_mii_sendbits(sc, phy, 5);
844 tl_mii_sendbits(sc, reg, 5);
845
846 netsio_clr(sc, TL_NETSIO_MTXEN);
847 netsio_clr(sc, TL_NETSIO_MCLK);
848 netsio_set(sc, TL_NETSIO_MCLK);
849 netsio_clr(sc, TL_NETSIO_MCLK);
850
851 err = netsio_read(sc, TL_NETSIO_MDATA);
852 netsio_set(sc, TL_NETSIO_MCLK);
853
854 /* Even if an error occurs, must still clock out the cycle. */
855 for (i = 0; i < 16; i++) {
856 data <<= 1;
857 netsio_clr(sc, TL_NETSIO_MCLK);
858 if (err == 0 && netsio_read(sc, TL_NETSIO_MDATA))
859 data |= 1;
860 netsio_set(sc, TL_NETSIO_MCLK);
861 }
862 netsio_clr(sc, TL_NETSIO_MCLK);
863 netsio_set(sc, TL_NETSIO_MCLK);
864
865 *val = data;
866 return err;
867 }
868
869 int
tl_mii_write(device_t self,int phy,int reg,uint16_t val)870 tl_mii_write(device_t self, int phy, int reg, uint16_t val)
871 {
872 struct tl_softc *sc = device_private(self);
873
874 /*
875 * Write the PHY register by manually driving the MII control lines.
876 */
877
878 tl_mii_sync(sc);
879 tl_mii_sendbits(sc, MII_COMMAND_START, 2);
880 tl_mii_sendbits(sc, MII_COMMAND_WRITE, 2);
881 tl_mii_sendbits(sc, phy, 5);
882 tl_mii_sendbits(sc, reg, 5);
883 tl_mii_sendbits(sc, MII_COMMAND_ACK, 2);
884 tl_mii_sendbits(sc, val, 16);
885
886 netsio_clr(sc, TL_NETSIO_MCLK);
887 netsio_set(sc, TL_NETSIO_MCLK);
888
889 return 0;
890 }
891
892 void
tl_statchg(struct ifnet * ifp)893 tl_statchg(struct ifnet *ifp)
894 {
895 tl_softc_t *sc = ifp->if_softc;
896 uint32_t reg;
897
898 #ifdef TLDEBUG
899 printf("%s: media %x\n", __func__, sc->tl_mii.mii_media.ifm_media);
900 #endif
901
902 /*
903 * We must keep the ThunderLAN and the PHY in sync as
904 * to the status of full-duplex!
905 */
906 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetCmd);
907 if (sc->tl_mii.mii_media_active & IFM_FDX)
908 reg |= TL_NETCOMMAND_DUPLEX;
909 else
910 reg &= ~TL_NETCOMMAND_DUPLEX;
911 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, reg);
912 }
913
914 /********** I2C glue **********/
915
916 static int
tl_i2c_send_start(void * cookie,int flags)917 tl_i2c_send_start(void *cookie, int flags)
918 {
919
920 return i2c_bitbang_send_start(cookie, flags, &tl_i2cbb_ops);
921 }
922
923 static int
tl_i2c_send_stop(void * cookie,int flags)924 tl_i2c_send_stop(void *cookie, int flags)
925 {
926
927 return i2c_bitbang_send_stop(cookie, flags, &tl_i2cbb_ops);
928 }
929
930 static int
tl_i2c_initiate_xfer(void * cookie,i2c_addr_t addr,int flags)931 tl_i2c_initiate_xfer(void *cookie, i2c_addr_t addr, int flags)
932 {
933
934 return i2c_bitbang_initiate_xfer(cookie, addr, flags, &tl_i2cbb_ops);
935 }
936
937 static int
tl_i2c_read_byte(void * cookie,uint8_t * valp,int flags)938 tl_i2c_read_byte(void *cookie, uint8_t *valp, int flags)
939 {
940
941 return i2c_bitbang_read_byte(cookie, valp, flags, &tl_i2cbb_ops);
942 }
943
944 static int
tl_i2c_write_byte(void * cookie,uint8_t val,int flags)945 tl_i2c_write_byte(void *cookie, uint8_t val, int flags)
946 {
947
948 return i2c_bitbang_write_byte(cookie, val, flags, &tl_i2cbb_ops);
949 }
950
951 /********** I2C bit-bang glue **********/
952
953 static void
tl_i2cbb_set_bits(void * cookie,uint32_t bits)954 tl_i2cbb_set_bits(void *cookie, uint32_t bits)
955 {
956 struct tl_softc *sc = cookie;
957 uint8_t reg;
958
959 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio);
960 reg = (reg & ~(TL_NETSIO_EDATA | TL_NETSIO_ECLOCK)) | bits;
961 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, reg);
962 }
963
964 static void
tl_i2cbb_set_dir(void * cookie,uint32_t bits)965 tl_i2cbb_set_dir(void *cookie, uint32_t bits)
966 {
967 struct tl_softc *sc = cookie;
968 uint8_t reg;
969
970 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio);
971 reg = (reg & ~TL_NETSIO_ETXEN) | bits;
972 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, reg);
973 }
974
975 static uint32_t
tl_i2cbb_read(void * cookie)976 tl_i2cbb_read(void *cookie)
977 {
978
979 return tl_intreg_read_byte(cookie, TL_INT_NET + TL_INT_NetSio);
980 }
981
982 /********** End of I2C stuff **********/
983
984 static int
tl_intr(void * v)985 tl_intr(void *v)
986 {
987 tl_softc_t *sc = v;
988 struct ifnet *ifp = &sc->tl_if;
989 struct Rx_list *Rx;
990 struct Tx_list *Tx;
991 struct mbuf *m;
992 uint32_t int_type, int_reg;
993 int ack = 0;
994 int size;
995
996 int_reg = TL_HR_READ(sc, TL_HOST_INTR_DIOADR);
997 int_type = int_reg & TL_INTR_MASK;
998 if (int_type == 0)
999 return 0;
1000 #if defined(TLDEBUG_RX) || defined(TLDEBUG_TX)
1001 printf("%s: interrupt type %x, intr_reg %x\n",
1002 device_xname(sc->sc_dev), int_type, int_reg);
1003 #endif
1004 /* disable interrupts */
1005 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff);
1006 switch (int_type & TL_INTR_MASK) {
1007 case TL_INTR_RxEOF:
1008 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0,
1009 sizeof(struct tl_Rx_list) * TL_NBUF,
1010 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1011 while (le32toh(sc->active_Rx->hw_list->stat) &
1012 TL_RX_CSTAT_CPLT) {
1013 /* dequeue and requeue at end of list */
1014 ack++;
1015 Rx = sc->active_Rx;
1016 sc->active_Rx = Rx->next;
1017 bus_dmamap_sync(sc->tl_dmatag, Rx->m_dmamap, 0,
1018 Rx->m_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
1019 bus_dmamap_unload(sc->tl_dmatag, Rx->m_dmamap);
1020 m = Rx->m;
1021 size = le32toh(Rx->hw_list->stat) >> 16;
1022 #ifdef TLDEBUG_RX
1023 printf("%s: RX list complete, Rx %p, size=%d\n",
1024 __func__, Rx, size);
1025 #endif
1026 if (tl_add_RxBuff(sc, Rx, m) == 0) {
1027 /*
1028 * No new mbuf, reuse the same. This means
1029 * that this packet
1030 * is lost
1031 */
1032 m = NULL;
1033 #ifdef TL_PRIV_STATS
1034 sc->ierr_nomem++;
1035 #endif
1036 #ifdef TLDEBUG
1037 printf("%s: out of mbuf, lost input packet\n",
1038 device_xname(sc->sc_dev));
1039 #endif
1040 }
1041 Rx->next = NULL;
1042 Rx->hw_list->fwd = 0;
1043 sc->last_Rx->hw_list->fwd = htole32(Rx->hw_listaddr);
1044 sc->last_Rx->next = Rx;
1045 sc->last_Rx = Rx;
1046
1047 /* deliver packet */
1048 if (m) {
1049 if (size < sizeof(struct ether_header)) {
1050 m_freem(m);
1051 continue;
1052 }
1053 m_set_rcvif(m, ifp);
1054 m->m_pkthdr.len = m->m_len = size;
1055 #ifdef TLDEBUG_RX
1056 {
1057 struct ether_header *eh =
1058 mtod(m, struct ether_header *);
1059 printf("%s: Rx packet:\n", __func__);
1060 ether_printheader(eh);
1061 }
1062 #endif
1063 if_percpuq_enqueue(ifp->if_percpuq, m);
1064 }
1065 }
1066 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0,
1067 sizeof(struct tl_Rx_list) * TL_NBUF,
1068 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1069 #ifdef TLDEBUG_RX
1070 printf("TL_INTR_RxEOF: ack %d\n", ack);
1071 #else
1072 if (ack == 0) {
1073 printf("%s: EOF intr without anything to read !\n",
1074 device_xname(sc->sc_dev));
1075 tl_reset(sc);
1076 /* schedule reinit of the board */
1077 callout_reset(&sc->tl_restart_ch, 1, tl_restart, ifp);
1078 return 1;
1079 }
1080 #endif
1081 break;
1082 case TL_INTR_RxEOC:
1083 ack++;
1084 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0,
1085 sizeof(struct tl_Rx_list) * TL_NBUF,
1086 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1087 #ifdef TLDEBUG_RX
1088 printf("TL_INTR_RxEOC: ack %d\n", ack);
1089 #endif
1090 #ifdef DIAGNOSTIC
1091 if (le32toh(sc->active_Rx->hw_list->stat) & TL_RX_CSTAT_CPLT) {
1092 printf("%s: Rx EOC interrupt and active Tx list not "
1093 "cleared\n", device_xname(sc->sc_dev));
1094 return 0;
1095 } else
1096 #endif
1097 {
1098 /*
1099 * write address of Rx list and send Rx GO command, ack
1100 * interrupt and enable interrupts in one command
1101 */
1102 TL_HR_WRITE(sc, TL_HOST_CH_PARM, sc->active_Rx->hw_listaddr);
1103 TL_HR_WRITE(sc, TL_HOST_CMD,
1104 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | ack | int_type |
1105 HOST_CMD_ACK | HOST_CMD_IntOn);
1106 return 1;
1107 }
1108 case TL_INTR_TxEOF:
1109 case TL_INTR_TxEOC:
1110 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0,
1111 sizeof(struct tl_Tx_list) * TL_NBUF,
1112 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1113 while ((Tx = sc->active_Tx) != NULL) {
1114 if ((le32toh(Tx->hw_list->stat) & TL_TX_CSTAT_CPLT)
1115 == 0)
1116 break;
1117 ack++;
1118 #ifdef TLDEBUG_TX
1119 printf("TL_INTR_TxEOC: list 0x%x done\n",
1120 (int)Tx->hw_listaddr);
1121 #endif
1122 Tx->hw_list->stat = 0;
1123 bus_dmamap_sync(sc->tl_dmatag, Tx->m_dmamap, 0,
1124 Tx->m_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
1125 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap);
1126 m_freem(Tx->m);
1127 Tx->m = NULL;
1128 sc->active_Tx = Tx->next;
1129 if (sc->active_Tx == NULL)
1130 sc->last_Tx = NULL;
1131 Tx->next = sc->Free_Tx;
1132 sc->Free_Tx = Tx;
1133 }
1134 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0,
1135 sizeof(struct tl_Tx_list) * TL_NBUF,
1136 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1137 /* if this was an EOC, ACK immediately */
1138 if (ack)
1139 sc->tl_if.if_flags &= ~IFF_OACTIVE;
1140 if (int_type == TL_INTR_TxEOC) {
1141 #ifdef TLDEBUG_TX
1142 printf("TL_INTR_TxEOC: ack %d (will be set to 1)\n",
1143 ack);
1144 #endif
1145 TL_HR_WRITE(sc, TL_HOST_CMD, 1 | int_type |
1146 HOST_CMD_ACK | HOST_CMD_IntOn);
1147 if (sc->active_Tx != NULL) {
1148 /* needs a Tx go command */
1149 TL_HR_WRITE(sc, TL_HOST_CH_PARM,
1150 sc->active_Tx->hw_listaddr);
1151 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO);
1152 }
1153 sc->tl_if.if_timer = 0;
1154 if_schedule_deferred_start(&sc->tl_if);
1155 return 1;
1156 }
1157 #ifdef TLDEBUG
1158 else {
1159 printf("TL_INTR_TxEOF: ack %d\n", ack);
1160 }
1161 #endif
1162 sc->tl_if.if_timer = 0;
1163 if_schedule_deferred_start(&sc->tl_if);
1164 break;
1165 case TL_INTR_Stat:
1166 ack++;
1167 #ifdef TLDEBUG
1168 printf("TL_INTR_Stat: ack %d\n", ack);
1169 #endif
1170 tl_read_stats(sc);
1171 break;
1172 case TL_INTR_Adc:
1173 if (int_reg & TL_INTVec_MASK) {
1174 /* adapter check conditions */
1175 printf("%s: check condition, intvect=0x%x, "
1176 "ch_param=0x%x\n", device_xname(sc->sc_dev),
1177 int_reg & TL_INTVec_MASK,
1178 TL_HR_READ(sc, TL_HOST_CH_PARM));
1179 tl_reset(sc);
1180 /* schedule reinit of the board */
1181 callout_reset(&sc->tl_restart_ch, 1, tl_restart, ifp);
1182 return 1;
1183 } else {
1184 uint8_t netstat;
1185 /* Network status */
1186 netstat =
1187 tl_intreg_read_byte(sc, TL_INT_NET+TL_INT_NetSts);
1188 printf("%s: network status, NetSts=%x\n",
1189 device_xname(sc->sc_dev), netstat);
1190 /* Ack interrupts */
1191 tl_intreg_write_byte(sc, TL_INT_NET+TL_INT_NetSts,
1192 netstat);
1193 ack++;
1194 }
1195 break;
1196 default:
1197 printf("%s: unhandled interrupt code %x!\n",
1198 device_xname(sc->sc_dev), int_type);
1199 ack++;
1200 }
1201
1202 if (ack) {
1203 /* Ack the interrupt and enable interrupts */
1204 TL_HR_WRITE(sc, TL_HOST_CMD, ack | int_type | HOST_CMD_ACK |
1205 HOST_CMD_IntOn);
1206 rnd_add_uint32(&sc->rnd_source, int_reg);
1207 return 1;
1208 }
1209 /* ack = 0 ; interrupt was perhaps not our. Just enable interrupts */
1210 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOn);
1211 return 0;
1212 }
1213
1214 static int
tl_ifioctl(struct ifnet * ifp,unsigned long cmd,void * data)1215 tl_ifioctl(struct ifnet *ifp, unsigned long cmd, void *data)
1216 {
1217 struct tl_softc *sc = ifp->if_softc;
1218 int s, error;
1219
1220 s = splnet();
1221 error = ether_ioctl(ifp, cmd, data);
1222 if (error == ENETRESET) {
1223 if (ifp->if_flags & IFF_RUNNING)
1224 tl_addr_filter(sc);
1225 error = 0;
1226 }
1227 splx(s);
1228 return error;
1229 }
1230
1231 static void
tl_ifstart(struct ifnet * ifp)1232 tl_ifstart(struct ifnet *ifp)
1233 {
1234 tl_softc_t *sc = ifp->if_softc;
1235 struct mbuf *mb_head;
1236 struct Tx_list *Tx;
1237 int segment, size;
1238 int again, error;
1239
1240 if ((sc->tl_if.if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
1241 return;
1242 txloop:
1243 /* If we don't have more space ... */
1244 if (sc->Free_Tx == NULL) {
1245 #ifdef TLDEBUG
1246 printf("%s: No free TX list\n", __func__);
1247 #endif
1248 sc->tl_if.if_flags |= IFF_OACTIVE;
1249 return;
1250 }
1251 /* Grab a paquet for output */
1252 IFQ_DEQUEUE(&ifp->if_snd, mb_head);
1253 if (mb_head == NULL) {
1254 #ifdef TLDEBUG_TX
1255 printf("%s: nothing to send\n", __func__);
1256 #endif
1257 return;
1258 }
1259 Tx = sc->Free_Tx;
1260 sc->Free_Tx = Tx->next;
1261 Tx->next = NULL;
1262 again = 0;
1263 /*
1264 * Go through each of the mbufs in the chain and initialize
1265 * the transmit list descriptors with the physical address
1266 * and size of the mbuf.
1267 */
1268 tbdinit:
1269 memset(Tx->hw_list, 0, sizeof(struct tl_Tx_list));
1270 Tx->m = mb_head;
1271 size = mb_head->m_pkthdr.len;
1272 if ((error = bus_dmamap_load_mbuf(sc->tl_dmatag, Tx->m_dmamap, mb_head,
1273 BUS_DMA_NOWAIT)) || (size < ETHER_MIN_TX &&
1274 Tx->m_dmamap->dm_nsegs == TL_NSEG)) {
1275 struct mbuf *mn;
1276 /*
1277 * We ran out of segments, or we will. We have to recopy this
1278 * mbuf chain first.
1279 */
1280 if (error == 0)
1281 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap);
1282 if (again) {
1283 /* already copied, can't do much more */
1284 m_freem(mb_head);
1285 goto bad;
1286 }
1287 again = 1;
1288 #ifdef TLDEBUG_TX
1289 printf("%s: need to copy mbuf\n", __func__);
1290 #endif
1291 #ifdef TL_PRIV_STATS
1292 sc->oerr_mcopy++;
1293 #endif
1294 MGETHDR(mn, M_DONTWAIT, MT_DATA);
1295 if (mn == NULL) {
1296 m_freem(mb_head);
1297 goto bad;
1298 }
1299 if (mb_head->m_pkthdr.len > MHLEN) {
1300 MCLGET(mn, M_DONTWAIT);
1301 if ((mn->m_flags & M_EXT) == 0) {
1302 m_freem(mn);
1303 m_freem(mb_head);
1304 goto bad;
1305 }
1306 }
1307 m_copydata(mb_head, 0, mb_head->m_pkthdr.len,
1308 mtod(mn, void *));
1309 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len;
1310 m_freem(mb_head);
1311 mb_head = mn;
1312 goto tbdinit;
1313 }
1314 for (segment = 0; segment < Tx->m_dmamap->dm_nsegs; segment++) {
1315 Tx->hw_list->seg[segment].data_addr =
1316 htole32(Tx->m_dmamap->dm_segs[segment].ds_addr);
1317 Tx->hw_list->seg[segment].data_count =
1318 htole32(Tx->m_dmamap->dm_segs[segment].ds_len);
1319 }
1320 bus_dmamap_sync(sc->tl_dmatag, Tx->m_dmamap, 0,
1321 Tx->m_dmamap->dm_mapsize,
1322 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1323 /* We are at end of mbuf chain. check the size and
1324 * see if it needs to be extended
1325 */
1326 if (size < ETHER_MIN_TX) {
1327 #ifdef DIAGNOSTIC
1328 if (segment >= TL_NSEG) {
1329 panic("%s: too much segments (%d)", __func__, segment);
1330 }
1331 #endif
1332 /*
1333 * add the nullbuf in the seg
1334 */
1335 Tx->hw_list->seg[segment].data_count =
1336 htole32(ETHER_MIN_TX - size);
1337 Tx->hw_list->seg[segment].data_addr =
1338 htole32(sc->null_dmamap->dm_segs[0].ds_addr);
1339 size = ETHER_MIN_TX;
1340 segment++;
1341 }
1342 /* The list is done, finish the list init */
1343 Tx->hw_list->seg[segment - 1].data_count |=
1344 htole32(TL_LAST_SEG);
1345 Tx->hw_list->stat = htole32((size << 16) | 0x3000);
1346 #ifdef TLDEBUG_TX
1347 printf("%s: sending, Tx : stat = 0x%x\n", device_xname(sc->sc_dev),
1348 le32toh(Tx->hw_list->stat));
1349 #if 0
1350 for (segment = 0; segment < TL_NSEG; segment++) {
1351 printf(" seg %d addr 0x%x len 0x%x\n",
1352 segment,
1353 le32toh(Tx->hw_list->seg[segment].data_addr),
1354 le32toh(Tx->hw_list->seg[segment].data_count));
1355 }
1356 #endif
1357 #endif
1358 if (sc->active_Tx == NULL) {
1359 sc->active_Tx = sc->last_Tx = Tx;
1360 #ifdef TLDEBUG_TX
1361 printf("%s: Tx GO, addr=0x%ux\n", device_xname(sc->sc_dev),
1362 (int)Tx->hw_listaddr);
1363 #endif
1364 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0,
1365 sizeof(struct tl_Tx_list) * TL_NBUF,
1366 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1367 TL_HR_WRITE(sc, TL_HOST_CH_PARM, Tx->hw_listaddr);
1368 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO);
1369 } else {
1370 #ifdef TLDEBUG_TX
1371 printf("%s: Tx addr=0x%ux queued\n", device_xname(sc->sc_dev),
1372 (int)Tx->hw_listaddr);
1373 #endif
1374 sc->last_Tx->hw_list->fwd = htole32(Tx->hw_listaddr);
1375 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0,
1376 sizeof(struct tl_Tx_list) * TL_NBUF,
1377 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1378 sc->last_Tx->next = Tx;
1379 sc->last_Tx = Tx;
1380 #ifdef DIAGNOSTIC
1381 if (sc->last_Tx->hw_list->fwd & 0x7)
1382 printf("%s: physical addr 0x%x of list not properly "
1383 "aligned\n",
1384 device_xname(sc->sc_dev),
1385 sc->last_Rx->hw_list->fwd);
1386 #endif
1387 }
1388 /* Pass packet to bpf if there is a listener */
1389 bpf_mtap(ifp, mb_head, BPF_D_OUT);
1390 /*
1391 * Set a 5 second timer just in case we don't hear from the card again.
1392 */
1393 ifp->if_timer = 5;
1394 goto txloop;
1395 bad:
1396 #ifdef TLDEBUG
1397 printf("%s: Out of mbuf, Tx pkt lost\n", __func__);
1398 #endif
1399 Tx->next = sc->Free_Tx;
1400 sc->Free_Tx = Tx;
1401 }
1402
1403 static void
tl_ifwatchdog(struct ifnet * ifp)1404 tl_ifwatchdog(struct ifnet *ifp)
1405 {
1406 tl_softc_t *sc = ifp->if_softc;
1407
1408 if ((ifp->if_flags & IFF_RUNNING) == 0)
1409 return;
1410 printf("%s: device timeout\n", device_xname(sc->sc_dev));
1411 if_statinc(ifp, if_oerrors);
1412 tl_init(ifp);
1413 }
1414
1415 static int
tl_add_RxBuff(tl_softc_t * sc,struct Rx_list * Rx,struct mbuf * oldm)1416 tl_add_RxBuff(tl_softc_t *sc, struct Rx_list *Rx, struct mbuf *oldm)
1417 {
1418 struct mbuf *m;
1419 int error;
1420
1421 MGETHDR(m, M_DONTWAIT, MT_DATA);
1422 if (m != NULL) {
1423 MCLGET(m, M_DONTWAIT);
1424 if ((m->m_flags & M_EXT) == 0) {
1425 m_freem(m);
1426 if (oldm == NULL)
1427 return 0;
1428 m = oldm;
1429 m->m_data = m->m_ext.ext_buf;
1430 }
1431 } else {
1432 if (oldm == NULL)
1433 return 0;
1434 m = oldm;
1435 m->m_data = m->m_ext.ext_buf;
1436 }
1437
1438 /* (re)init the Rx_list struct */
1439
1440 Rx->m = m;
1441 if ((error = bus_dmamap_load(sc->tl_dmatag, Rx->m_dmamap,
1442 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT)) != 0) {
1443 printf("%s: bus_dmamap_load() failed (error %d) for "
1444 "tl_add_RxBuff ", device_xname(sc->sc_dev), error);
1445 printf("size %d (%d)\n", m->m_pkthdr.len, MCLBYTES);
1446 m_freem(m);
1447 Rx->m = NULL;
1448 return 0;
1449 }
1450 bus_dmamap_sync(sc->tl_dmatag, Rx->m_dmamap, 0,
1451 Rx->m_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
1452 /*
1453 * Move the data pointer up so that the incoming data packet
1454 * will be 32-bit aligned.
1455 */
1456 m->m_data += 2;
1457
1458 Rx->hw_list->stat =
1459 htole32(((Rx->m_dmamap->dm_segs[0].ds_len - 2) << 16) | 0x3000);
1460 Rx->hw_list->seg.data_count =
1461 htole32(Rx->m_dmamap->dm_segs[0].ds_len - 2);
1462 Rx->hw_list->seg.data_addr =
1463 htole32(Rx->m_dmamap->dm_segs[0].ds_addr + 2);
1464 return (m != oldm);
1465 }
1466
1467 static void
tl_ticks(void * v)1468 tl_ticks(void *v)
1469 {
1470 tl_softc_t *sc = v;
1471
1472 tl_read_stats(sc);
1473
1474 /* Tick the MII. */
1475 mii_tick(&sc->tl_mii);
1476
1477 /* read statistics every seconds */
1478 callout_reset(&sc->tl_tick_ch, hz, tl_ticks, sc);
1479 }
1480
1481 static void
tl_read_stats(tl_softc_t * sc)1482 tl_read_stats(tl_softc_t *sc)
1483 {
1484 uint32_t reg;
1485 int ierr_overr;
1486 int ierr_code;
1487 int ierr_crc;
1488 int oerr_underr;
1489 int oerr_deferred;
1490 int oerr_coll;
1491 int oerr_multicoll;
1492 int oerr_exesscoll;
1493 int oerr_latecoll;
1494 int oerr_carrloss;
1495 struct ifnet *ifp = &sc->tl_if;
1496
1497 net_stat_ref_t nsr = IF_STAT_GETREF(ifp);
1498
1499 reg = tl_intreg_read(sc, TL_INT_STATS_TX);
1500 if_statadd_ref(ifp, nsr, if_opackets, reg & 0x00ffffff);
1501 oerr_underr = reg >> 24;
1502
1503 reg = tl_intreg_read(sc, TL_INT_STATS_RX);
1504 ierr_overr = reg >> 24;
1505
1506 reg = tl_intreg_read(sc, TL_INT_STATS_FERR);
1507 ierr_crc = (reg & TL_FERR_CRC) >> 16;
1508 ierr_code = (reg & TL_FERR_CODE) >> 24;
1509 oerr_deferred = (reg & TL_FERR_DEF);
1510
1511 reg = tl_intreg_read(sc, TL_INT_STATS_COLL);
1512 oerr_multicoll = (reg & TL_COL_MULTI);
1513 oerr_coll = (reg & TL_COL_SINGLE) >> 16;
1514
1515 reg = tl_intreg_read(sc, TL_INT_LERR);
1516 oerr_exesscoll = (reg & TL_LERR_ECOLL);
1517 oerr_latecoll = (reg & TL_LERR_LCOLL) >> 8;
1518 oerr_carrloss = (reg & TL_LERR_CL) >> 16;
1519
1520 if_statadd_ref(ifp, nsr, if_oerrors,
1521 oerr_underr + oerr_exesscoll + oerr_latecoll + oerr_carrloss);
1522 if_statadd_ref(ifp, nsr, if_collisions, oerr_coll + oerr_multicoll);
1523 if_statadd_ref(ifp, nsr, if_ierrors,
1524 ierr_overr + ierr_code + ierr_crc);
1525 IF_STAT_PUTREF(ifp);
1526
1527 if (ierr_overr)
1528 printf("%s: receiver ring buffer overrun\n",
1529 device_xname(sc->sc_dev));
1530 if (oerr_underr)
1531 printf("%s: transmit buffer underrun\n",
1532 device_xname(sc->sc_dev));
1533 #ifdef TL_PRIV_STATS
1534 sc->ierr_overr += ierr_overr;
1535 sc->ierr_code += ierr_code;
1536 sc->ierr_crc += ierr_crc;
1537 sc->oerr_underr += oerr_underr;
1538 sc->oerr_deferred += oerr_deferred;
1539 sc->oerr_coll += oerr_coll;
1540 sc->oerr_multicoll += oerr_multicoll;
1541 sc->oerr_exesscoll += oerr_exesscoll;
1542 sc->oerr_latecoll += oerr_latecoll;
1543 sc->oerr_carrloss += oerr_carrloss;
1544 #endif
1545 }
1546
1547 static void
tl_addr_filter(tl_softc_t * sc)1548 tl_addr_filter(tl_softc_t *sc)
1549 {
1550 struct ethercom *ec = &sc->tl_ec;
1551 struct ether_multistep step;
1552 struct ether_multi *enm;
1553 uint32_t hash[2] = {0, 0};
1554 int i;
1555
1556 sc->tl_if.if_flags &= ~IFF_ALLMULTI;
1557 ETHER_LOCK(ec);
1558 ETHER_FIRST_MULTI(step, ec, enm);
1559 while (enm != NULL) {
1560 #ifdef TLDEBUG
1561 printf("%s: addrs %s %s\n", __func__,
1562 ether_sprintf(enm->enm_addrlo),
1563 ether_sprintf(enm->enm_addrhi));
1564 #endif
1565 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) == 0) {
1566 i = tl_multicast_hash(enm->enm_addrlo);
1567 hash[i / 32] |= 1 << (i%32);
1568 } else {
1569 hash[0] = hash[1] = 0xffffffff;
1570 sc->tl_if.if_flags |= IFF_ALLMULTI;
1571 break;
1572 }
1573 ETHER_NEXT_MULTI(step, enm);
1574 }
1575 ETHER_UNLOCK(ec);
1576 #ifdef TLDEBUG
1577 printf("%s: hash1 %x has2 %x\n", __func__, hash[0], hash[1]);
1578 #endif
1579 tl_intreg_write(sc, TL_INT_HASH1, hash[0]);
1580 tl_intreg_write(sc, TL_INT_HASH2, hash[1]);
1581 }
1582
1583 static int
tl_multicast_hash(uint8_t * a)1584 tl_multicast_hash(uint8_t *a)
1585 {
1586 int hash;
1587
1588 #define DA(addr, bit) (addr[5 - (bit / 8)] & (1 << (bit % 8)))
1589 #define xor8(a, b, c, d, e, f, g, h) \
1590 (((a != 0) + (b != 0) + (c != 0) + (d != 0) + \
1591 (e != 0) + (f != 0) + (g != 0) + (h != 0)) & 1)
1592
1593 hash = xor8(DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24), DA(a,30),
1594 DA(a,36), DA(a,42));
1595 hash |= xor8(DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25), DA(a,31),
1596 DA(a,37), DA(a,43)) << 1;
1597 hash |= xor8(DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26), DA(a,32),
1598 DA(a,38), DA(a,44)) << 2;
1599 hash |= xor8(DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27), DA(a,33),
1600 DA(a,39), DA(a,45)) << 3;
1601 hash |= xor8(DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28), DA(a,34),
1602 DA(a,40), DA(a,46)) << 4;
1603 hash |= xor8(DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29), DA(a,35),
1604 DA(a,41), DA(a,47)) << 5;
1605
1606 return hash;
1607 }
1608
1609 #if defined(TLDEBUG_RX)
1610 void
ether_printheader(struct ether_header * eh)1611 ether_printheader(struct ether_header *eh)
1612 {
1613 uint8_t *c = (uint8_t *)eh;
1614 int i;
1615
1616 for (i = 0; i < sizeof(struct ether_header); i++)
1617 printf("%02x ", (u_int)c[i]);
1618 printf("\n");
1619 }
1620 #endif
1621