1 //===-- MipsAsmBackend.cpp - Mips Asm Backend ----------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the MipsAsmBackend class. 10 // 11 //===----------------------------------------------------------------------===// 12 // 13 14 #include "MCTargetDesc/MipsAsmBackend.h" 15 #include "MCTargetDesc/MipsABIInfo.h" 16 #include "MCTargetDesc/MipsFixupKinds.h" 17 #include "MCTargetDesc/MipsMCTargetDesc.h" 18 #include "llvm/ADT/StringSwitch.h" 19 #include "llvm/MC/MCAsmBackend.h" 20 #include "llvm/MC/MCAssembler.h" 21 #include "llvm/MC/MCContext.h" 22 #include "llvm/MC/MCELFObjectWriter.h" 23 #include "llvm/MC/MCFixupKindInfo.h" 24 #include "llvm/MC/MCObjectWriter.h" 25 #include "llvm/MC/MCSubtargetInfo.h" 26 #include "llvm/MC/MCTargetOptions.h" 27 #include "llvm/MC/MCValue.h" 28 #include "llvm/Support/ErrorHandling.h" 29 #include "llvm/Support/MathExtras.h" 30 #include "llvm/Support/raw_ostream.h" 31 32 using namespace llvm; 33 34 // Prepare value for the target space for it 35 static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value, 36 MCContext &Ctx) { 37 38 unsigned Kind = Fixup.getKind(); 39 40 // Add/subtract and shift 41 switch (Kind) { 42 default: 43 return 0; 44 case FK_Data_2: 45 case Mips::fixup_Mips_LO16: 46 case Mips::fixup_Mips_GPREL16: 47 case Mips::fixup_Mips_GPOFF_HI: 48 case Mips::fixup_Mips_GPOFF_LO: 49 case Mips::fixup_Mips_GOT_PAGE: 50 case Mips::fixup_Mips_GOT_OFST: 51 case Mips::fixup_Mips_GOT_DISP: 52 case Mips::fixup_Mips_GOT_LO16: 53 case Mips::fixup_Mips_CALL_LO16: 54 case Mips::fixup_MICROMIPS_GPOFF_HI: 55 case Mips::fixup_MICROMIPS_GPOFF_LO: 56 case Mips::fixup_MICROMIPS_LO16: 57 case Mips::fixup_MICROMIPS_GOT_PAGE: 58 case Mips::fixup_MICROMIPS_GOT_OFST: 59 case Mips::fixup_MICROMIPS_GOT_DISP: 60 case Mips::fixup_MIPS_PCLO16: 61 Value &= 0xffff; 62 break; 63 case FK_DTPRel_4: 64 case FK_DTPRel_8: 65 case FK_TPRel_4: 66 case FK_TPRel_8: 67 case FK_GPRel_4: 68 case FK_Data_4: 69 case FK_Data_8: 70 case Mips::fixup_Mips_SUB: 71 case Mips::fixup_MICROMIPS_SUB: 72 break; 73 case Mips::fixup_Mips_PC16: 74 // The displacement is then divided by 4 to give us an 18 bit 75 // address range. Forcing a signed division because Value can be negative. 76 Value = (int64_t)Value / 4; 77 // We now check if Value can be encoded as a 16-bit signed immediate. 78 if (!isInt<16>(Value)) { 79 Ctx.reportError(Fixup.getLoc(), "out of range PC16 fixup"); 80 return 0; 81 } 82 break; 83 case Mips::fixup_MIPS_PC19_S2: 84 case Mips::fixup_MICROMIPS_PC19_S2: 85 // Forcing a signed division because Value can be negative. 86 Value = (int64_t)Value / 4; 87 // We now check if Value can be encoded as a 19-bit signed immediate. 88 if (!isInt<19>(Value)) { 89 Ctx.reportError(Fixup.getLoc(), "out of range PC19 fixup"); 90 return 0; 91 } 92 break; 93 case Mips::fixup_Mips_26: 94 // So far we are only using this type for jumps. 95 // The displacement is then divided by 4 to give us an 28 bit 96 // address range. 97 Value >>= 2; 98 break; 99 case Mips::fixup_Mips_HI16: 100 case Mips::fixup_Mips_GOT: 101 case Mips::fixup_MICROMIPS_GOT16: 102 case Mips::fixup_Mips_GOT_HI16: 103 case Mips::fixup_Mips_CALL_HI16: 104 case Mips::fixup_MICROMIPS_HI16: 105 case Mips::fixup_MIPS_PCHI16: 106 // Get the 2nd 16-bits. Also add 1 if bit 15 is 1. 107 Value = ((Value + 0x8000) >> 16) & 0xffff; 108 break; 109 case Mips::fixup_Mips_HIGHER: 110 case Mips::fixup_MICROMIPS_HIGHER: 111 // Get the 3rd 16-bits. 112 Value = ((Value + 0x80008000LL) >> 32) & 0xffff; 113 break; 114 case Mips::fixup_Mips_HIGHEST: 115 case Mips::fixup_MICROMIPS_HIGHEST: 116 // Get the 4th 16-bits. 117 Value = ((Value + 0x800080008000LL) >> 48) & 0xffff; 118 break; 119 case Mips::fixup_MICROMIPS_26_S1: 120 Value >>= 1; 121 break; 122 case Mips::fixup_MICROMIPS_PC7_S1: 123 Value -= 4; 124 // Forcing a signed division because Value can be negative. 125 Value = (int64_t) Value / 2; 126 // We now check if Value can be encoded as a 7-bit signed immediate. 127 if (!isInt<7>(Value)) { 128 Ctx.reportError(Fixup.getLoc(), "out of range PC7 fixup"); 129 return 0; 130 } 131 break; 132 case Mips::fixup_MICROMIPS_PC10_S1: 133 Value -= 2; 134 // Forcing a signed division because Value can be negative. 135 Value = (int64_t) Value / 2; 136 // We now check if Value can be encoded as a 10-bit signed immediate. 137 if (!isInt<10>(Value)) { 138 Ctx.reportError(Fixup.getLoc(), "out of range PC10 fixup"); 139 return 0; 140 } 141 break; 142 case Mips::fixup_MICROMIPS_PC16_S1: 143 Value -= 4; 144 // Forcing a signed division because Value can be negative. 145 Value = (int64_t)Value / 2; 146 // We now check if Value can be encoded as a 16-bit signed immediate. 147 if (!isInt<16>(Value)) { 148 Ctx.reportError(Fixup.getLoc(), "out of range PC16 fixup"); 149 return 0; 150 } 151 break; 152 case Mips::fixup_MIPS_PC18_S3: 153 // Forcing a signed division because Value can be negative. 154 Value = (int64_t)Value / 8; 155 // We now check if Value can be encoded as a 18-bit signed immediate. 156 if (!isInt<18>(Value)) { 157 Ctx.reportError(Fixup.getLoc(), "out of range PC18 fixup"); 158 return 0; 159 } 160 break; 161 case Mips::fixup_MICROMIPS_PC18_S3: 162 // Check alignment. 163 if ((Value & 7)) { 164 Ctx.reportError(Fixup.getLoc(), "out of range PC18 fixup"); 165 } 166 // Forcing a signed division because Value can be negative. 167 Value = (int64_t)Value / 8; 168 // We now check if Value can be encoded as a 18-bit signed immediate. 169 if (!isInt<18>(Value)) { 170 Ctx.reportError(Fixup.getLoc(), "out of range PC18 fixup"); 171 return 0; 172 } 173 break; 174 case Mips::fixup_MIPS_PC21_S2: 175 // Forcing a signed division because Value can be negative. 176 Value = (int64_t) Value / 4; 177 // We now check if Value can be encoded as a 21-bit signed immediate. 178 if (!isInt<21>(Value)) { 179 Ctx.reportError(Fixup.getLoc(), "out of range PC21 fixup"); 180 return 0; 181 } 182 break; 183 case Mips::fixup_MIPS_PC26_S2: 184 // Forcing a signed division because Value can be negative. 185 Value = (int64_t) Value / 4; 186 // We now check if Value can be encoded as a 26-bit signed immediate. 187 if (!isInt<26>(Value)) { 188 Ctx.reportError(Fixup.getLoc(), "out of range PC26 fixup"); 189 return 0; 190 } 191 break; 192 case Mips::fixup_MICROMIPS_PC26_S1: 193 // Forcing a signed division because Value can be negative. 194 Value = (int64_t)Value / 2; 195 // We now check if Value can be encoded as a 26-bit signed immediate. 196 if (!isInt<26>(Value)) { 197 Ctx.reportError(Fixup.getLoc(), "out of range PC26 fixup"); 198 return 0; 199 } 200 break; 201 case Mips::fixup_MICROMIPS_PC21_S1: 202 // Forcing a signed division because Value can be negative. 203 Value = (int64_t)Value / 2; 204 // We now check if Value can be encoded as a 21-bit signed immediate. 205 if (!isInt<21>(Value)) { 206 Ctx.reportError(Fixup.getLoc(), "out of range PC21 fixup"); 207 return 0; 208 } 209 break; 210 } 211 212 return Value; 213 } 214 215 std::unique_ptr<MCObjectTargetWriter> 216 MipsAsmBackend::createObjectTargetWriter() const { 217 return createMipsELFObjectWriter(TheTriple, IsN32); 218 } 219 220 // Little-endian fixup data byte ordering: 221 // mips32r2: a | b | x | x 222 // microMIPS: x | x | a | b 223 224 static bool needsMMLEByteOrder(unsigned Kind) { 225 return Kind != Mips::fixup_MICROMIPS_PC10_S1 && 226 Kind >= Mips::fixup_MICROMIPS_26_S1 && 227 Kind < Mips::LastTargetFixupKind; 228 } 229 230 // Calculate index for microMIPS specific little endian byte order 231 static unsigned calculateMMLEIndex(unsigned i) { 232 assert(i <= 3 && "Index out of range!"); 233 234 return (1 - i / 2) * 2 + i % 2; 235 } 236 237 /// ApplyFixup - Apply the \p Value for given \p Fixup into the provided 238 /// data fragment, at the offset specified by the fixup and following the 239 /// fixup kind as appropriate. 240 void MipsAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, 241 const MCValue &Target, 242 MutableArrayRef<char> Data, uint64_t Value, 243 bool IsResolved, 244 const MCSubtargetInfo *STI) const { 245 MCFixupKind Kind = Fixup.getKind(); 246 MCContext &Ctx = Asm.getContext(); 247 Value = adjustFixupValue(Fixup, Value, Ctx); 248 249 if (!Value) 250 return; // Doesn't change encoding. 251 252 // Where do we start in the object 253 unsigned Offset = Fixup.getOffset(); 254 // Number of bytes we need to fixup 255 unsigned NumBytes = (getFixupKindInfo(Kind).TargetSize + 7) / 8; 256 // Used to point to big endian bytes 257 unsigned FullSize; 258 259 switch ((unsigned)Kind) { 260 case FK_Data_2: 261 case Mips::fixup_Mips_16: 262 case Mips::fixup_MICROMIPS_PC10_S1: 263 FullSize = 2; 264 break; 265 case FK_Data_8: 266 case Mips::fixup_Mips_64: 267 FullSize = 8; 268 break; 269 case FK_Data_4: 270 default: 271 FullSize = 4; 272 break; 273 } 274 275 // Grab current value, if any, from bits. 276 uint64_t CurVal = 0; 277 278 bool microMipsLEByteOrder = needsMMLEByteOrder((unsigned) Kind); 279 280 for (unsigned i = 0; i != NumBytes; ++i) { 281 unsigned Idx = Endian == llvm::endianness::little 282 ? (microMipsLEByteOrder ? calculateMMLEIndex(i) : i) 283 : (FullSize - 1 - i); 284 CurVal |= (uint64_t)((uint8_t)Data[Offset + Idx]) << (i*8); 285 } 286 287 uint64_t Mask = ((uint64_t)(-1) >> 288 (64 - getFixupKindInfo(Kind).TargetSize)); 289 CurVal |= Value & Mask; 290 291 // Write out the fixed up bytes back to the code/data bits. 292 for (unsigned i = 0; i != NumBytes; ++i) { 293 unsigned Idx = Endian == llvm::endianness::little 294 ? (microMipsLEByteOrder ? calculateMMLEIndex(i) : i) 295 : (FullSize - 1 - i); 296 Data[Offset + Idx] = (uint8_t)((CurVal >> (i*8)) & 0xff); 297 } 298 } 299 300 std::optional<MCFixupKind> MipsAsmBackend::getFixupKind(StringRef Name) const { 301 unsigned Type = llvm::StringSwitch<unsigned>(Name) 302 .Case("BFD_RELOC_NONE", ELF::R_MIPS_NONE) 303 .Case("BFD_RELOC_16", ELF::R_MIPS_16) 304 .Case("BFD_RELOC_32", ELF::R_MIPS_32) 305 .Case("BFD_RELOC_64", ELF::R_MIPS_64) 306 .Default(-1u); 307 if (Type != -1u) 308 return static_cast<MCFixupKind>(FirstLiteralRelocationKind + Type); 309 310 return StringSwitch<std::optional<MCFixupKind>>(Name) 311 .Case("R_MIPS_NONE", FK_NONE) 312 .Case("R_MIPS_32", FK_Data_4) 313 .Case("R_MIPS_CALL_HI16", (MCFixupKind)Mips::fixup_Mips_CALL_HI16) 314 .Case("R_MIPS_CALL_LO16", (MCFixupKind)Mips::fixup_Mips_CALL_LO16) 315 .Case("R_MIPS_CALL16", (MCFixupKind)Mips::fixup_Mips_CALL16) 316 .Case("R_MIPS_GOT16", (MCFixupKind)Mips::fixup_Mips_GOT) 317 .Case("R_MIPS_GOT_PAGE", (MCFixupKind)Mips::fixup_Mips_GOT_PAGE) 318 .Case("R_MIPS_GOT_OFST", (MCFixupKind)Mips::fixup_Mips_GOT_OFST) 319 .Case("R_MIPS_GOT_DISP", (MCFixupKind)Mips::fixup_Mips_GOT_DISP) 320 .Case("R_MIPS_GOT_HI16", (MCFixupKind)Mips::fixup_Mips_GOT_HI16) 321 .Case("R_MIPS_GOT_LO16", (MCFixupKind)Mips::fixup_Mips_GOT_LO16) 322 .Case("R_MIPS_TLS_GOTTPREL", (MCFixupKind)Mips::fixup_Mips_GOTTPREL) 323 .Case("R_MIPS_TLS_DTPREL_HI16", (MCFixupKind)Mips::fixup_Mips_DTPREL_HI) 324 .Case("R_MIPS_TLS_DTPREL_LO16", (MCFixupKind)Mips::fixup_Mips_DTPREL_LO) 325 .Case("R_MIPS_TLS_GD", (MCFixupKind)Mips::fixup_Mips_TLSGD) 326 .Case("R_MIPS_TLS_LDM", (MCFixupKind)Mips::fixup_Mips_TLSLDM) 327 .Case("R_MIPS_TLS_TPREL_HI16", (MCFixupKind)Mips::fixup_Mips_TPREL_HI) 328 .Case("R_MIPS_TLS_TPREL_LO16", (MCFixupKind)Mips::fixup_Mips_TPREL_LO) 329 .Case("R_MICROMIPS_CALL16", (MCFixupKind)Mips::fixup_MICROMIPS_CALL16) 330 .Case("R_MICROMIPS_GOT_DISP", (MCFixupKind)Mips::fixup_MICROMIPS_GOT_DISP) 331 .Case("R_MICROMIPS_GOT_PAGE", (MCFixupKind)Mips::fixup_MICROMIPS_GOT_PAGE) 332 .Case("R_MICROMIPS_GOT_OFST", (MCFixupKind)Mips::fixup_MICROMIPS_GOT_OFST) 333 .Case("R_MICROMIPS_GOT16", (MCFixupKind)Mips::fixup_MICROMIPS_GOT16) 334 .Case("R_MICROMIPS_TLS_GOTTPREL", 335 (MCFixupKind)Mips::fixup_MICROMIPS_GOTTPREL) 336 .Case("R_MICROMIPS_TLS_DTPREL_HI16", 337 (MCFixupKind)Mips::fixup_MICROMIPS_TLS_DTPREL_HI16) 338 .Case("R_MICROMIPS_TLS_DTPREL_LO16", 339 (MCFixupKind)Mips::fixup_MICROMIPS_TLS_DTPREL_LO16) 340 .Case("R_MICROMIPS_TLS_GD", (MCFixupKind)Mips::fixup_MICROMIPS_TLS_GD) 341 .Case("R_MICROMIPS_TLS_LDM", (MCFixupKind)Mips::fixup_MICROMIPS_TLS_LDM) 342 .Case("R_MICROMIPS_TLS_TPREL_HI16", 343 (MCFixupKind)Mips::fixup_MICROMIPS_TLS_TPREL_HI16) 344 .Case("R_MICROMIPS_TLS_TPREL_LO16", 345 (MCFixupKind)Mips::fixup_MICROMIPS_TLS_TPREL_LO16) 346 .Case("R_MIPS_JALR", (MCFixupKind)Mips::fixup_Mips_JALR) 347 .Case("R_MICROMIPS_JALR", (MCFixupKind)Mips::fixup_MICROMIPS_JALR) 348 .Default(MCAsmBackend::getFixupKind(Name)); 349 } 350 351 const MCFixupKindInfo &MipsAsmBackend:: 352 getFixupKindInfo(MCFixupKind Kind) const { 353 const static MCFixupKindInfo LittleEndianInfos[] = { 354 // This table *must* be in same the order of fixup_* kinds in 355 // MipsFixupKinds.h. 356 // 357 // name offset bits flags 358 { "fixup_Mips_16", 0, 16, 0 }, 359 { "fixup_Mips_32", 0, 32, 0 }, 360 { "fixup_Mips_REL32", 0, 32, 0 }, 361 { "fixup_Mips_26", 0, 26, 0 }, 362 { "fixup_Mips_HI16", 0, 16, 0 }, 363 { "fixup_Mips_LO16", 0, 16, 0 }, 364 { "fixup_Mips_GPREL16", 0, 16, 0 }, 365 { "fixup_Mips_LITERAL", 0, 16, 0 }, 366 { "fixup_Mips_GOT", 0, 16, 0 }, 367 { "fixup_Mips_PC16", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 368 { "fixup_Mips_CALL16", 0, 16, 0 }, 369 { "fixup_Mips_GPREL32", 0, 32, 0 }, 370 { "fixup_Mips_SHIFT5", 6, 5, 0 }, 371 { "fixup_Mips_SHIFT6", 6, 5, 0 }, 372 { "fixup_Mips_64", 0, 64, 0 }, 373 { "fixup_Mips_TLSGD", 0, 16, 0 }, 374 { "fixup_Mips_GOTTPREL", 0, 16, 0 }, 375 { "fixup_Mips_TPREL_HI", 0, 16, 0 }, 376 { "fixup_Mips_TPREL_LO", 0, 16, 0 }, 377 { "fixup_Mips_TLSLDM", 0, 16, 0 }, 378 { "fixup_Mips_DTPREL_HI", 0, 16, 0 }, 379 { "fixup_Mips_DTPREL_LO", 0, 16, 0 }, 380 { "fixup_Mips_Branch_PCRel", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 381 { "fixup_Mips_GPOFF_HI", 0, 16, 0 }, 382 { "fixup_MICROMIPS_GPOFF_HI",0, 16, 0 }, 383 { "fixup_Mips_GPOFF_LO", 0, 16, 0 }, 384 { "fixup_MICROMIPS_GPOFF_LO",0, 16, 0 }, 385 { "fixup_Mips_GOT_PAGE", 0, 16, 0 }, 386 { "fixup_Mips_GOT_OFST", 0, 16, 0 }, 387 { "fixup_Mips_GOT_DISP", 0, 16, 0 }, 388 { "fixup_Mips_HIGHER", 0, 16, 0 }, 389 { "fixup_MICROMIPS_HIGHER", 0, 16, 0 }, 390 { "fixup_Mips_HIGHEST", 0, 16, 0 }, 391 { "fixup_MICROMIPS_HIGHEST", 0, 16, 0 }, 392 { "fixup_Mips_GOT_HI16", 0, 16, 0 }, 393 { "fixup_Mips_GOT_LO16", 0, 16, 0 }, 394 { "fixup_Mips_CALL_HI16", 0, 16, 0 }, 395 { "fixup_Mips_CALL_LO16", 0, 16, 0 }, 396 { "fixup_Mips_PC18_S3", 0, 18, MCFixupKindInfo::FKF_IsPCRel }, 397 { "fixup_MIPS_PC19_S2", 0, 19, MCFixupKindInfo::FKF_IsPCRel }, 398 { "fixup_MIPS_PC21_S2", 0, 21, MCFixupKindInfo::FKF_IsPCRel }, 399 { "fixup_MIPS_PC26_S2", 0, 26, MCFixupKindInfo::FKF_IsPCRel }, 400 { "fixup_MIPS_PCHI16", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 401 { "fixup_MIPS_PCLO16", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 402 { "fixup_MICROMIPS_26_S1", 0, 26, 0 }, 403 { "fixup_MICROMIPS_HI16", 0, 16, 0 }, 404 { "fixup_MICROMIPS_LO16", 0, 16, 0 }, 405 { "fixup_MICROMIPS_GOT16", 0, 16, 0 }, 406 { "fixup_MICROMIPS_PC7_S1", 0, 7, MCFixupKindInfo::FKF_IsPCRel }, 407 { "fixup_MICROMIPS_PC10_S1", 0, 10, MCFixupKindInfo::FKF_IsPCRel }, 408 { "fixup_MICROMIPS_PC16_S1", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 409 { "fixup_MICROMIPS_PC26_S1", 0, 26, MCFixupKindInfo::FKF_IsPCRel }, 410 { "fixup_MICROMIPS_PC19_S2", 0, 19, MCFixupKindInfo::FKF_IsPCRel }, 411 { "fixup_MICROMIPS_PC18_S3", 0, 18, MCFixupKindInfo::FKF_IsPCRel }, 412 { "fixup_MICROMIPS_PC21_S1", 0, 21, MCFixupKindInfo::FKF_IsPCRel }, 413 { "fixup_MICROMIPS_CALL16", 0, 16, 0 }, 414 { "fixup_MICROMIPS_GOT_DISP", 0, 16, 0 }, 415 { "fixup_MICROMIPS_GOT_PAGE", 0, 16, 0 }, 416 { "fixup_MICROMIPS_GOT_OFST", 0, 16, 0 }, 417 { "fixup_MICROMIPS_TLS_GD", 0, 16, 0 }, 418 { "fixup_MICROMIPS_TLS_LDM", 0, 16, 0 }, 419 { "fixup_MICROMIPS_TLS_DTPREL_HI16", 0, 16, 0 }, 420 { "fixup_MICROMIPS_TLS_DTPREL_LO16", 0, 16, 0 }, 421 { "fixup_MICROMIPS_GOTTPREL", 0, 16, 0 }, 422 { "fixup_MICROMIPS_TLS_TPREL_HI16", 0, 16, 0 }, 423 { "fixup_MICROMIPS_TLS_TPREL_LO16", 0, 16, 0 }, 424 { "fixup_Mips_SUB", 0, 64, 0 }, 425 { "fixup_MICROMIPS_SUB", 0, 64, 0 }, 426 { "fixup_Mips_JALR", 0, 32, 0 }, 427 { "fixup_MICROMIPS_JALR", 0, 32, 0 } 428 }; 429 static_assert(std::size(LittleEndianInfos) == Mips::NumTargetFixupKinds, 430 "Not all MIPS little endian fixup kinds added!"); 431 432 const static MCFixupKindInfo BigEndianInfos[] = { 433 // This table *must* be in same the order of fixup_* kinds in 434 // MipsFixupKinds.h. 435 // 436 // name offset bits flags 437 { "fixup_Mips_16", 16, 16, 0 }, 438 { "fixup_Mips_32", 0, 32, 0 }, 439 { "fixup_Mips_REL32", 0, 32, 0 }, 440 { "fixup_Mips_26", 6, 26, 0 }, 441 { "fixup_Mips_HI16", 16, 16, 0 }, 442 { "fixup_Mips_LO16", 16, 16, 0 }, 443 { "fixup_Mips_GPREL16", 16, 16, 0 }, 444 { "fixup_Mips_LITERAL", 16, 16, 0 }, 445 { "fixup_Mips_GOT", 16, 16, 0 }, 446 { "fixup_Mips_PC16", 16, 16, MCFixupKindInfo::FKF_IsPCRel }, 447 { "fixup_Mips_CALL16", 16, 16, 0 }, 448 { "fixup_Mips_GPREL32", 0, 32, 0 }, 449 { "fixup_Mips_SHIFT5", 21, 5, 0 }, 450 { "fixup_Mips_SHIFT6", 21, 5, 0 }, 451 { "fixup_Mips_64", 0, 64, 0 }, 452 { "fixup_Mips_TLSGD", 16, 16, 0 }, 453 { "fixup_Mips_GOTTPREL", 16, 16, 0 }, 454 { "fixup_Mips_TPREL_HI", 16, 16, 0 }, 455 { "fixup_Mips_TPREL_LO", 16, 16, 0 }, 456 { "fixup_Mips_TLSLDM", 16, 16, 0 }, 457 { "fixup_Mips_DTPREL_HI", 16, 16, 0 }, 458 { "fixup_Mips_DTPREL_LO", 16, 16, 0 }, 459 { "fixup_Mips_Branch_PCRel",16, 16, MCFixupKindInfo::FKF_IsPCRel }, 460 { "fixup_Mips_GPOFF_HI", 16, 16, 0 }, 461 { "fixup_MICROMIPS_GPOFF_HI", 16, 16, 0 }, 462 { "fixup_Mips_GPOFF_LO", 16, 16, 0 }, 463 { "fixup_MICROMIPS_GPOFF_LO", 16, 16, 0 }, 464 { "fixup_Mips_GOT_PAGE", 16, 16, 0 }, 465 { "fixup_Mips_GOT_OFST", 16, 16, 0 }, 466 { "fixup_Mips_GOT_DISP", 16, 16, 0 }, 467 { "fixup_Mips_HIGHER", 16, 16, 0 }, 468 { "fixup_MICROMIPS_HIGHER", 16, 16, 0 }, 469 { "fixup_Mips_HIGHEST", 16, 16, 0 }, 470 { "fixup_MICROMIPS_HIGHEST",16, 16, 0 }, 471 { "fixup_Mips_GOT_HI16", 16, 16, 0 }, 472 { "fixup_Mips_GOT_LO16", 16, 16, 0 }, 473 { "fixup_Mips_CALL_HI16", 16, 16, 0 }, 474 { "fixup_Mips_CALL_LO16", 16, 16, 0 }, 475 { "fixup_Mips_PC18_S3", 14, 18, MCFixupKindInfo::FKF_IsPCRel }, 476 { "fixup_MIPS_PC19_S2", 13, 19, MCFixupKindInfo::FKF_IsPCRel }, 477 { "fixup_MIPS_PC21_S2", 11, 21, MCFixupKindInfo::FKF_IsPCRel }, 478 { "fixup_MIPS_PC26_S2", 6, 26, MCFixupKindInfo::FKF_IsPCRel }, 479 { "fixup_MIPS_PCHI16", 16, 16, MCFixupKindInfo::FKF_IsPCRel }, 480 { "fixup_MIPS_PCLO16", 16, 16, MCFixupKindInfo::FKF_IsPCRel }, 481 { "fixup_MICROMIPS_26_S1", 6, 26, 0 }, 482 { "fixup_MICROMIPS_HI16", 16, 16, 0 }, 483 { "fixup_MICROMIPS_LO16", 16, 16, 0 }, 484 { "fixup_MICROMIPS_GOT16", 16, 16, 0 }, 485 { "fixup_MICROMIPS_PC7_S1", 9, 7, MCFixupKindInfo::FKF_IsPCRel }, 486 { "fixup_MICROMIPS_PC10_S1", 6, 10, MCFixupKindInfo::FKF_IsPCRel }, 487 { "fixup_MICROMIPS_PC16_S1",16, 16, MCFixupKindInfo::FKF_IsPCRel }, 488 { "fixup_MICROMIPS_PC26_S1", 6, 26, MCFixupKindInfo::FKF_IsPCRel }, 489 { "fixup_MICROMIPS_PC19_S2",13, 19, MCFixupKindInfo::FKF_IsPCRel }, 490 { "fixup_MICROMIPS_PC18_S3",14, 18, MCFixupKindInfo::FKF_IsPCRel }, 491 { "fixup_MICROMIPS_PC21_S1",11, 21, MCFixupKindInfo::FKF_IsPCRel }, 492 { "fixup_MICROMIPS_CALL16", 16, 16, 0 }, 493 { "fixup_MICROMIPS_GOT_DISP", 16, 16, 0 }, 494 { "fixup_MICROMIPS_GOT_PAGE", 16, 16, 0 }, 495 { "fixup_MICROMIPS_GOT_OFST", 16, 16, 0 }, 496 { "fixup_MICROMIPS_TLS_GD", 16, 16, 0 }, 497 { "fixup_MICROMIPS_TLS_LDM", 16, 16, 0 }, 498 { "fixup_MICROMIPS_TLS_DTPREL_HI16", 16, 16, 0 }, 499 { "fixup_MICROMIPS_TLS_DTPREL_LO16", 16, 16, 0 }, 500 { "fixup_MICROMIPS_GOTTPREL", 16, 16, 0 }, 501 { "fixup_MICROMIPS_TLS_TPREL_HI16", 16, 16, 0 }, 502 { "fixup_MICROMIPS_TLS_TPREL_LO16", 16, 16, 0 }, 503 { "fixup_Mips_SUB", 0, 64, 0 }, 504 { "fixup_MICROMIPS_SUB", 0, 64, 0 }, 505 { "fixup_Mips_JALR", 0, 32, 0 }, 506 { "fixup_MICROMIPS_JALR", 0, 32, 0 } 507 }; 508 static_assert(std::size(BigEndianInfos) == Mips::NumTargetFixupKinds, 509 "Not all MIPS big endian fixup kinds added!"); 510 511 if (Kind >= FirstLiteralRelocationKind) 512 return MCAsmBackend::getFixupKindInfo(FK_NONE); 513 if (Kind < FirstTargetFixupKind) 514 return MCAsmBackend::getFixupKindInfo(Kind); 515 516 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && 517 "Invalid kind!"); 518 519 if (Endian == llvm::endianness::little) 520 return LittleEndianInfos[Kind - FirstTargetFixupKind]; 521 return BigEndianInfos[Kind - FirstTargetFixupKind]; 522 } 523 524 /// WriteNopData - Write an (optimal) nop sequence of Count bytes 525 /// to the given output. If the target cannot generate such a sequence, 526 /// it should return an error. 527 /// 528 /// \return - True on success. 529 bool MipsAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count, 530 const MCSubtargetInfo *STI) const { 531 // Check for a less than instruction size number of bytes 532 // FIXME: 16 bit instructions are not handled yet here. 533 // We shouldn't be using a hard coded number for instruction size. 534 535 // If the count is not 4-byte aligned, we must be writing data into the text 536 // section (otherwise we have unaligned instructions, and thus have far 537 // bigger problems), so just write zeros instead. 538 OS.write_zeros(Count); 539 return true; 540 } 541 542 bool MipsAsmBackend::shouldForceRelocation(const MCAssembler &Asm, 543 const MCFixup &Fixup, 544 const MCValue &Target, 545 const uint64_t, 546 const MCSubtargetInfo *STI) { 547 if (Fixup.getKind() >= FirstLiteralRelocationKind) 548 return true; 549 const unsigned FixupKind = Fixup.getKind(); 550 switch (FixupKind) { 551 default: 552 return false; 553 // All these relocations require special processing 554 // at linking time. Delegate this work to a linker. 555 case Mips::fixup_Mips_CALL_HI16: 556 case Mips::fixup_Mips_CALL_LO16: 557 case Mips::fixup_Mips_CALL16: 558 case Mips::fixup_Mips_GOT: 559 case Mips::fixup_Mips_GOT_PAGE: 560 case Mips::fixup_Mips_GOT_OFST: 561 case Mips::fixup_Mips_GOT_DISP: 562 case Mips::fixup_Mips_GOT_HI16: 563 case Mips::fixup_Mips_GOT_LO16: 564 case Mips::fixup_Mips_GOTTPREL: 565 case Mips::fixup_Mips_DTPREL_HI: 566 case Mips::fixup_Mips_DTPREL_LO: 567 case Mips::fixup_Mips_TLSGD: 568 case Mips::fixup_Mips_TLSLDM: 569 case Mips::fixup_Mips_TPREL_HI: 570 case Mips::fixup_Mips_TPREL_LO: 571 case Mips::fixup_Mips_JALR: 572 case Mips::fixup_MICROMIPS_CALL16: 573 case Mips::fixup_MICROMIPS_GOT_DISP: 574 case Mips::fixup_MICROMIPS_GOT_PAGE: 575 case Mips::fixup_MICROMIPS_GOT_OFST: 576 case Mips::fixup_MICROMIPS_GOT16: 577 case Mips::fixup_MICROMIPS_GOTTPREL: 578 case Mips::fixup_MICROMIPS_TLS_DTPREL_HI16: 579 case Mips::fixup_MICROMIPS_TLS_DTPREL_LO16: 580 case Mips::fixup_MICROMIPS_TLS_GD: 581 case Mips::fixup_MICROMIPS_TLS_LDM: 582 case Mips::fixup_MICROMIPS_TLS_TPREL_HI16: 583 case Mips::fixup_MICROMIPS_TLS_TPREL_LO16: 584 case Mips::fixup_MICROMIPS_JALR: 585 return true; 586 } 587 } 588 589 bool MipsAsmBackend::isMicroMips(const MCSymbol *Sym) const { 590 if (const auto *ElfSym = dyn_cast<const MCSymbolELF>(Sym)) { 591 if (ElfSym->getOther() & ELF::STO_MIPS_MICROMIPS) 592 return true; 593 } 594 return false; 595 } 596 597 namespace { 598 599 class WindowsMipsAsmBackend : public MipsAsmBackend { 600 public: 601 WindowsMipsAsmBackend(const Target &T, const MCRegisterInfo &MRI, 602 const MCSubtargetInfo &STI) 603 : MipsAsmBackend(T, MRI, STI.getTargetTriple(), STI.getCPU(), false) {} 604 605 std::unique_ptr<MCObjectTargetWriter> 606 createObjectTargetWriter() const override { 607 return createMipsWinCOFFObjectWriter(); 608 } 609 }; 610 611 } // end anonymous namespace 612 613 MCAsmBackend *llvm::createMipsAsmBackend(const Target &T, 614 const MCSubtargetInfo &STI, 615 const MCRegisterInfo &MRI, 616 const MCTargetOptions &Options) { 617 const Triple &TheTriple = STI.getTargetTriple(); 618 if (TheTriple.isOSWindows() && TheTriple.isOSBinFormatCOFF()) 619 return new WindowsMipsAsmBackend(T, MRI, STI); 620 621 MipsABIInfo ABI = MipsABIInfo::computeTargetABI(STI.getTargetTriple(), 622 STI.getCPU(), Options); 623 return new MipsAsmBackend(T, MRI, STI.getTargetTriple(), STI.getCPU(), 624 ABI.IsN32()); 625 } 626