1 /* $NetBSD: amdgpu_nbio_v6_1.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $ */
2
3 /*
4 * Copyright 2016 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25 #include <sys/cdefs.h>
26 __KERNEL_RCSID(0, "$NetBSD: amdgpu_nbio_v6_1.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $");
27
28 #include "amdgpu.h"
29 #include "amdgpu_atombios.h"
30 #include "nbio_v6_1.h"
31
32 #include "nbio/nbio_6_1_default.h"
33 #include "nbio/nbio_6_1_offset.h"
34 #include "nbio/nbio_6_1_sh_mask.h"
35 #include "nbio/nbio_6_1_smn.h"
36 #include "vega10_enum.h"
37
nbio_v6_1_get_rev_id(struct amdgpu_device * adev)38 static u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev)
39 {
40 u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
41
42 tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
43 tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
44
45 return tmp;
46 }
47
nbio_v6_1_mc_access_enable(struct amdgpu_device * adev,bool enable)48 static void nbio_v6_1_mc_access_enable(struct amdgpu_device *adev, bool enable)
49 {
50 if (enable)
51 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN,
52 BIF_FB_EN__FB_READ_EN_MASK |
53 BIF_FB_EN__FB_WRITE_EN_MASK);
54 else
55 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0);
56 }
57
nbio_v6_1_hdp_flush(struct amdgpu_device * adev,struct amdgpu_ring * ring)58 static void nbio_v6_1_hdp_flush(struct amdgpu_device *adev,
59 struct amdgpu_ring *ring)
60 {
61 if (!ring || !ring->funcs->emit_wreg)
62 WREG32_SOC15_NO_KIQ(NBIO, 0,
63 mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL,
64 0);
65 else
66 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
67 NBIO, 0, mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL), 0);
68 }
69
nbio_v6_1_get_memsize(struct amdgpu_device * adev)70 static u32 nbio_v6_1_get_memsize(struct amdgpu_device *adev)
71 {
72 return RREG32_SOC15(NBIO, 0, mmRCC_PF_0_0_RCC_CONFIG_MEMSIZE);
73 }
74
nbio_v6_1_sdma_doorbell_range(struct amdgpu_device * adev,int instance,bool use_doorbell,int doorbell_index,int doorbell_size)75 static void nbio_v6_1_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
76 bool use_doorbell, int doorbell_index, int doorbell_size)
77 {
78 u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
79 SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE);
80
81 u32 doorbell_range = RREG32(reg);
82
83 if (use_doorbell) {
84 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
85 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, doorbell_size);
86 } else
87 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
88
89 WREG32(reg, doorbell_range);
90
91 }
92
nbio_v6_1_enable_doorbell_aperture(struct amdgpu_device * adev,bool enable)93 static void nbio_v6_1_enable_doorbell_aperture(struct amdgpu_device *adev,
94 bool enable)
95 {
96 WREG32_FIELD15(NBIO, 0, RCC_PF_0_0_RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0);
97 }
98
nbio_v6_1_enable_doorbell_selfring_aperture(struct amdgpu_device * adev,bool enable)99 static void nbio_v6_1_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
100 bool enable)
101 {
102 u32 tmp = 0;
103
104 if (enable) {
105 tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_EN, 1) |
106 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_MODE, 1) |
107 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_SIZE, 0);
108
109 WREG32_SOC15(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW,
110 lower_32_bits(adev->doorbell.base));
111 WREG32_SOC15(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH,
112 upper_32_bits(adev->doorbell.base));
113 }
114
115 WREG32_SOC15(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, tmp);
116 }
117
118
nbio_v6_1_ih_doorbell_range(struct amdgpu_device * adev,bool use_doorbell,int doorbell_index)119 static void nbio_v6_1_ih_doorbell_range(struct amdgpu_device *adev,
120 bool use_doorbell, int doorbell_index)
121 {
122 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE);
123
124 if (use_doorbell) {
125 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index);
126 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
127 BIF_IH_DOORBELL_RANGE, SIZE, 6);
128 } else
129 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0);
130
131 WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range);
132 }
133
nbio_v6_1_ih_control(struct amdgpu_device * adev)134 static void nbio_v6_1_ih_control(struct amdgpu_device *adev)
135 {
136 u32 interrupt_cntl;
137
138 /* setup interrupt control */
139 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
140 interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL);
141 /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
142 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
143 */
144 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
145 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
146 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
147 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl);
148 }
149
nbio_v6_1_update_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable)150 static void nbio_v6_1_update_medium_grain_clock_gating(struct amdgpu_device *adev,
151 bool enable)
152 {
153 uint32_t def, data;
154
155 def = data = RREG32_PCIE(smnCPM_CONTROL);
156 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG)) {
157 data |= (CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
158 CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK |
159 CPM_CONTROL__TXCLK_PERM_GATE_ENABLE_MASK |
160 CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK |
161 CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK |
162 CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK |
163 CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK);
164 } else {
165 data &= ~(CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
166 CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK |
167 CPM_CONTROL__TXCLK_PERM_GATE_ENABLE_MASK |
168 CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK |
169 CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK |
170 CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK |
171 CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK);
172 }
173
174 if (def != data)
175 WREG32_PCIE(smnCPM_CONTROL, data);
176 }
177
nbio_v6_1_update_medium_grain_light_sleep(struct amdgpu_device * adev,bool enable)178 static void nbio_v6_1_update_medium_grain_light_sleep(struct amdgpu_device *adev,
179 bool enable)
180 {
181 uint32_t def, data;
182
183 def = data = RREG32_PCIE(smnPCIE_CNTL2);
184 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
185 data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
186 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
187 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
188 } else {
189 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
190 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
191 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
192 }
193
194 if (def != data)
195 WREG32_PCIE(smnPCIE_CNTL2, data);
196 }
197
nbio_v6_1_get_clockgating_state(struct amdgpu_device * adev,u32 * flags)198 static void nbio_v6_1_get_clockgating_state(struct amdgpu_device *adev,
199 u32 *flags)
200 {
201 int data;
202
203 /* AMD_CG_SUPPORT_BIF_MGCG */
204 data = RREG32_PCIE(smnCPM_CONTROL);
205 if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK)
206 *flags |= AMD_CG_SUPPORT_BIF_MGCG;
207
208 /* AMD_CG_SUPPORT_BIF_LS */
209 data = RREG32_PCIE(smnPCIE_CNTL2);
210 if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
211 *flags |= AMD_CG_SUPPORT_BIF_LS;
212 }
213
nbio_v6_1_get_hdp_flush_req_offset(struct amdgpu_device * adev)214 static u32 nbio_v6_1_get_hdp_flush_req_offset(struct amdgpu_device *adev)
215 {
216 return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_REQ);
217 }
218
nbio_v6_1_get_hdp_flush_done_offset(struct amdgpu_device * adev)219 static u32 nbio_v6_1_get_hdp_flush_done_offset(struct amdgpu_device *adev)
220 {
221 return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_DONE);
222 }
223
nbio_v6_1_get_pcie_index_offset(struct amdgpu_device * adev)224 static u32 nbio_v6_1_get_pcie_index_offset(struct amdgpu_device *adev)
225 {
226 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2);
227 }
228
nbio_v6_1_get_pcie_data_offset(struct amdgpu_device * adev)229 static u32 nbio_v6_1_get_pcie_data_offset(struct amdgpu_device *adev)
230 {
231 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
232 }
233
234 const struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg = {
235 .ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK,
236 .ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK,
237 .ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK,
238 .ref_and_mask_cp3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK,
239 .ref_and_mask_cp4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK,
240 .ref_and_mask_cp5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK,
241 .ref_and_mask_cp6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK,
242 .ref_and_mask_cp7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK,
243 .ref_and_mask_cp8 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK,
244 .ref_and_mask_cp9 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK,
245 .ref_and_mask_sdma0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK,
246 .ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK
247 };
248
nbio_v6_1_detect_hw_virt(struct amdgpu_device * adev)249 static void nbio_v6_1_detect_hw_virt(struct amdgpu_device *adev)
250 {
251 uint32_t reg;
252
253 reg = RREG32_SOC15(NBIO, 0, mmRCC_PF_0_0_RCC_IOV_FUNC_IDENTIFIER);
254 if (reg & 1)
255 adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF;
256
257 if (reg & 0x80000000)
258 adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV;
259
260 if (!reg) {
261 if (is_virtual_machine()) /* passthrough mode exclus sriov mod */
262 adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
263 }
264 }
265
nbio_v6_1_init_registers(struct amdgpu_device * adev)266 static void nbio_v6_1_init_registers(struct amdgpu_device *adev)
267 {
268 uint32_t def, data;
269
270 def = data = RREG32_PCIE(smnPCIE_CONFIG_CNTL);
271 data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
272 data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);
273
274 if (def != data)
275 WREG32_PCIE(smnPCIE_CONFIG_CNTL, data);
276
277 def = data = RREG32_PCIE(smnPCIE_CI_CNTL);
278 data = REG_SET_FIELD(data, PCIE_CI_CNTL, CI_SLV_ORDERING_DIS, 1);
279
280 if (def != data)
281 WREG32_PCIE(smnPCIE_CI_CNTL, data);
282 }
283
284 const struct amdgpu_nbio_funcs nbio_v6_1_funcs = {
285 .get_hdp_flush_req_offset = nbio_v6_1_get_hdp_flush_req_offset,
286 .get_hdp_flush_done_offset = nbio_v6_1_get_hdp_flush_done_offset,
287 .get_pcie_index_offset = nbio_v6_1_get_pcie_index_offset,
288 .get_pcie_data_offset = nbio_v6_1_get_pcie_data_offset,
289 .get_rev_id = nbio_v6_1_get_rev_id,
290 .mc_access_enable = nbio_v6_1_mc_access_enable,
291 .hdp_flush = nbio_v6_1_hdp_flush,
292 .get_memsize = nbio_v6_1_get_memsize,
293 .sdma_doorbell_range = nbio_v6_1_sdma_doorbell_range,
294 .enable_doorbell_aperture = nbio_v6_1_enable_doorbell_aperture,
295 .enable_doorbell_selfring_aperture = nbio_v6_1_enable_doorbell_selfring_aperture,
296 .ih_doorbell_range = nbio_v6_1_ih_doorbell_range,
297 .update_medium_grain_clock_gating = nbio_v6_1_update_medium_grain_clock_gating,
298 .update_medium_grain_light_sleep = nbio_v6_1_update_medium_grain_light_sleep,
299 .get_clockgating_state = nbio_v6_1_get_clockgating_state,
300 .ih_control = nbio_v6_1_ih_control,
301 .init_registers = nbio_v6_1_init_registers,
302 .detect_hw_virt = nbio_v6_1_detect_hw_virt,
303 };
304