1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2001-2024 Intel Corporation 3 */ 4 5 #ifndef _IDPF_LAN_TXRX_H_ 6 #define _IDPF_LAN_TXRX_H_ 7 8 #include "idpf_osdep.h" 9 10 enum idpf_rss_hash { 11 IDPF_HASH_INVALID = 0, 12 /* Values 1 - 28 are reserved for future use */ 13 IDPF_HASH_NONF_UNICAST_IPV4_UDP = 29, 14 IDPF_HASH_NONF_MULTICAST_IPV4_UDP, 15 IDPF_HASH_NONF_IPV4_UDP, 16 IDPF_HASH_NONF_IPV4_TCP_SYN_NO_ACK, 17 IDPF_HASH_NONF_IPV4_TCP, 18 IDPF_HASH_NONF_IPV4_SCTP, 19 IDPF_HASH_NONF_IPV4_OTHER, 20 IDPF_HASH_FRAG_IPV4, 21 /* Values 37-38 are reserved */ 22 IDPF_HASH_NONF_UNICAST_IPV6_UDP = 39, 23 IDPF_HASH_NONF_MULTICAST_IPV6_UDP, 24 IDPF_HASH_NONF_IPV6_UDP, 25 IDPF_HASH_NONF_IPV6_TCP_SYN_NO_ACK, 26 IDPF_HASH_NONF_IPV6_TCP, 27 IDPF_HASH_NONF_IPV6_SCTP, 28 IDPF_HASH_NONF_IPV6_OTHER, 29 IDPF_HASH_FRAG_IPV6, 30 IDPF_HASH_NONF_RSVD47, 31 IDPF_HASH_NONF_FCOE_OX, 32 IDPF_HASH_NONF_FCOE_RX, 33 IDPF_HASH_NONF_FCOE_OTHER, 34 /* Values 51-62 are reserved */ 35 IDPF_HASH_L2_PAYLOAD = 63, 36 IDPF_HASH_MAX 37 }; 38 39 /* Supported RSS offloads */ 40 #define IDPF_DEFAULT_RSS_HASH \ 41 (BIT_ULL(IDPF_HASH_NONF_IPV4_UDP) | \ 42 BIT_ULL(IDPF_HASH_NONF_IPV4_SCTP) | \ 43 BIT_ULL(IDPF_HASH_NONF_IPV4_TCP) | \ 44 BIT_ULL(IDPF_HASH_NONF_IPV4_OTHER) | \ 45 BIT_ULL(IDPF_HASH_FRAG_IPV4) | \ 46 BIT_ULL(IDPF_HASH_NONF_IPV6_UDP) | \ 47 BIT_ULL(IDPF_HASH_NONF_IPV6_TCP) | \ 48 BIT_ULL(IDPF_HASH_NONF_IPV6_SCTP) | \ 49 BIT_ULL(IDPF_HASH_NONF_IPV6_OTHER) | \ 50 BIT_ULL(IDPF_HASH_FRAG_IPV6) | \ 51 BIT_ULL(IDPF_HASH_L2_PAYLOAD)) 52 53 #define IDPF_DEFAULT_RSS_HASH_EXPANDED (IDPF_DEFAULT_RSS_HASH | \ 54 BIT_ULL(IDPF_HASH_NONF_IPV4_TCP_SYN_NO_ACK) | \ 55 BIT_ULL(IDPF_HASH_NONF_UNICAST_IPV4_UDP) | \ 56 BIT_ULL(IDPF_HASH_NONF_MULTICAST_IPV4_UDP) | \ 57 BIT_ULL(IDPF_HASH_NONF_IPV6_TCP_SYN_NO_ACK) | \ 58 BIT_ULL(IDPF_HASH_NONF_UNICAST_IPV6_UDP) | \ 59 BIT_ULL(IDPF_HASH_NONF_MULTICAST_IPV6_UDP)) 60 61 /* For idpf_splitq_base_tx_compl_desc */ 62 #define IDPF_TXD_COMPLQ_GEN_S 15 63 #define IDPF_TXD_COMPLQ_GEN_M BIT_ULL(IDPF_TXD_COMPLQ_GEN_S) 64 #define IDPF_TXD_COMPLQ_COMPL_TYPE_S 11 65 #define IDPF_TXD_COMPLQ_COMPL_TYPE_M GENMASK_ULL(13, 11) 66 #define IDPF_TXD_COMPLQ_QID_S 0 67 #define IDPF_TXD_COMPLQ_QID_M GENMASK_ULL(9, 0) 68 69 /* For base mode TX descriptors */ 70 71 #define IDPF_TXD_CTX_QW0_TUNN_L4T_CS_S 23 72 #define IDPF_TXD_CTX_QW0_TUNN_L4T_CS_M \ 73 BIT_ULL(IDPF_TXD_CTX_QW0_TUNN_L4T_CS_S) 74 #define IDPF_TXD_CTX_QW0_TUNN_DECTTL_S 19 75 #define IDPF_TXD_CTX_QW0_TUNN_DECTTL_M GENMASK_ULL(22, 19) 76 #define IDPF_TXD_CTX_QW0_TUNN_NATLEN_S 12 77 #define IDPF_TXD_CTX_QW0_TUNN_NATLEN_M GENMASK_ULL(18, 12) 78 #define IDPF_TXD_CTX_QW0_TUNN_EIP_NOINC_S 11 79 #define IDPF_TXD_CTX_QW0_TUNN_EIP_NOINC_M \ 80 BIT_ULL(IDPF_TXD_CTX_QW0_TUNN_EIP_NOINC_S) 81 #define IDPF_TXD_CTX_EIP_NOINC_IPID_CONST \ 82 IDPF_TXD_CTX_QW0_TUNN_EIP_NOINC_M 83 #define IDPF_TXD_CTX_QW0_TUNN_NATT_S 9 84 #define IDPF_TXD_CTX_QW0_TUNN_NATT_M GENMASK_ULL(10, 9) 85 #define IDPF_TXD_CTX_UDP_TUNNELING BIT_ULL(9) 86 #define IDPF_TXD_CTX_GRE_TUNNELING BIT_ULL(10) 87 #define IDPF_TXD_CTX_QW0_TUNN_EXT_IPLEN_S 2 88 #define IDPF_TXD_CTX_QW0_TUNN_EXT_IPLEN_M GENMASK_ULL(7, 2) 89 #define IDPF_TXD_CTX_QW0_TUNN_EXT_IP_S 0 90 #define IDPF_TXD_CTX_QW0_TUNN_EXT_IP_M GENMASK_ULL(1, 0) 91 92 #define IDPF_TXD_CTX_QW1_MSS_S 50 93 #define IDPF_TXD_CTX_QW1_MSS_M GENMASK_ULL(63, 50) 94 #define IDPF_TXD_CTX_QW1_TSO_LEN_S 30 95 #define IDPF_TXD_CTX_QW1_TSO_LEN_M GENMASK_ULL(47, 30) 96 #define IDPF_TXD_CTX_QW1_CMD_S 4 97 #define IDPF_TXD_CTX_QW1_CMD_M GENMASK_ULL(15, 4) 98 #define IDPF_TXD_CTX_QW1_DTYPE_S 0 99 #define IDPF_TXD_CTX_QW1_DTYPE_M GENMASK_ULL(3, 0) 100 #define IDPF_TXD_QW1_L2TAG1_S 48 101 #define IDPF_TXD_QW1_L2TAG1_M GENMASK_ULL(63, 48) 102 #define IDPF_TXD_QW1_TX_BUF_SZ_S 34 103 #define IDPF_TXD_QW1_TX_BUF_SZ_M GENMASK_ULL(47, 34) 104 #define IDPF_TXD_QW1_OFFSET_S 16 105 #define IDPF_TXD_QW1_OFFSET_M GENMASK_ULL(33, 16) 106 #define IDPF_TXD_QW1_CMD_S 4 107 #define IDPF_TXD_QW1_CMD_M GENMASK_ULL(15, 4) 108 #define IDPF_TXD_QW1_DTYPE_S 0 109 #define IDPF_TXD_QW1_DTYPE_M GENMASK_ULL(3, 0) 110 111 /* TX Completion Descriptor Completion Types */ 112 #define IDPF_TXD_COMPLT_ITR_FLUSH 0 113 #define IDPF_TXD_COMPLT_RULE_MISS 1 114 #define IDPF_TXD_COMPLT_RS 2 115 #define IDPF_TXD_COMPLT_REINJECTED 3 116 #define IDPF_TXD_COMPLT_RE 4 117 #define IDPF_TXD_COMPLT_SW_MARKER 5 118 119 enum idpf_tx_desc_dtype_value { 120 IDPF_TX_DESC_DTYPE_DATA = 0, 121 IDPF_TX_DESC_DTYPE_CTX = 1, 122 /* DTYPE 2 is reserved 123 * DTYPE 3 is free for future use 124 * DTYPE 4 is reserved 125 */ 126 IDPF_TX_DESC_DTYPE_FLEX_TSO_CTX = 5, 127 /* DTYPE 6 is reserved */ 128 IDPF_TX_DESC_DTYPE_FLEX_L2TAG1_L2TAG2 = 7, 129 /* DTYPE 8, 9 are free for future use 130 * DTYPE 10 is reserved 131 * DTYPE 11 is free for future use 132 */ 133 IDPF_TX_DESC_DTYPE_FLEX_FLOW_SCHE = 12, 134 /* DTYPE 13, 14 are free for future use */ 135 /* DESC_DONE - HW has completed write-back of descriptor */ 136 IDPF_TX_DESC_DTYPE_DESC_DONE = 15, 137 }; 138 139 enum idpf_tx_ctx_desc_cmd_bits { 140 IDPF_TX_CTX_DESC_TSO = 0x01, 141 IDPF_TX_CTX_DESC_TSYN = 0x02, 142 IDPF_TX_CTX_DESC_IL2TAG2 = 0x04, 143 IDPF_TX_CTX_DESC_RSVD = 0x08, 144 IDPF_TX_CTX_DESC_SWTCH_NOTAG = 0x00, 145 IDPF_TX_CTX_DESC_SWTCH_UPLINK = 0x10, 146 IDPF_TX_CTX_DESC_SWTCH_LOCAL = 0x20, 147 IDPF_TX_CTX_DESC_SWTCH_VSI = 0x30, 148 IDPF_TX_CTX_DESC_FILT_AU_EN = 0x40, 149 IDPF_TX_CTX_DESC_FILT_AU_EVICT = 0x80, 150 IDPF_TX_CTX_DESC_RSVD1 = 0xF00 151 }; 152 153 enum idpf_tx_desc_len_fields { 154 /* Note: These are predefined bit offsets */ 155 IDPF_TX_DESC_LEN_MACLEN_S = 0, /* 7 BITS */ 156 IDPF_TX_DESC_LEN_IPLEN_S = 7, /* 7 BITS */ 157 IDPF_TX_DESC_LEN_L4_LEN_S = 14 /* 4 BITS */ 158 }; 159 160 #define IDPF_TXD_QW1_MACLEN_M GENMASK_ULL(6, 0) 161 #define IDPF_TXD_QW1_IPLEN_M GENMASK_ULL(13, 7) 162 #define IDPF_TXD_QW1_L4LEN_M GENMASK_ULL(17, 14) 163 #define IDPF_TXD_QW1_FCLEN_M GENMASK_ULL(17, 14) 164 165 enum idpf_tx_base_desc_cmd_bits { 166 IDPF_TX_DESC_CMD_EOP = 0x0001, 167 IDPF_TX_DESC_CMD_RS = 0x0002, 168 /* only on VFs else RSVD */ 169 IDPF_TX_DESC_CMD_ICRC = 0x0004, 170 IDPF_TX_DESC_CMD_IL2TAG1 = 0x0008, 171 IDPF_TX_DESC_CMD_RSVD1 = 0x0010, 172 IDPF_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */ 173 IDPF_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */ 174 IDPF_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */ 175 IDPF_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */ 176 IDPF_TX_DESC_CMD_RSVD2 = 0x0080, 177 IDPF_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */ 178 IDPF_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */ 179 IDPF_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */ 180 IDPF_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */ 181 IDPF_TX_DESC_CMD_RSVD3 = 0x0400, 182 IDPF_TX_DESC_CMD_RSVD4 = 0x0800, 183 }; 184 185 /* Transmit descriptors */ 186 /* splitq tx buf, singleq tx buf and singleq compl desc */ 187 struct idpf_base_tx_desc { 188 __le64 buf_addr; /* Address of descriptor's data buf */ 189 __le64 qw1; /* type_cmd_offset_bsz_l2tag1 */ 190 };/* read used with buffer queues*/ 191 192 struct idpf_splitq_tx_compl_desc { 193 /* qid=[10:0] comptype=[13:11] rsvd=[14] gen=[15] */ 194 __le16 qid_comptype_gen; 195 union { 196 __le16 q_head; /* Queue head */ 197 __le16 compl_tag; /* Completion tag */ 198 } q_head_compl_tag; 199 u32 rsvd; 200 201 };/* writeback used with completion queues*/ 202 203 /* Context descriptors */ 204 struct idpf_base_tx_ctx_desc { 205 struct { 206 __le32 tunneling_params; 207 __le16 l2tag2; 208 __le16 rsvd1; 209 } qw0; 210 __le64 qw1; /* type_cmd_tlen_mss/rt_hint */ 211 }; 212 213 /* Common cmd field defines for all desc except Flex Flow Scheduler (0x0C) */ 214 enum idpf_tx_flex_desc_cmd_bits { 215 IDPF_TX_FLEX_DESC_CMD_EOP = 0x01, 216 IDPF_TX_FLEX_DESC_CMD_RS = 0x02, 217 IDPF_TX_FLEX_DESC_CMD_RE = 0x04, 218 IDPF_TX_FLEX_DESC_CMD_IL2TAG1 = 0x08, 219 IDPF_TX_FLEX_DESC_CMD_DUMMY = 0x10, 220 IDPF_TX_FLEX_DESC_CMD_CS_EN = 0x20, 221 IDPF_TX_FLEX_DESC_CMD_FILT_AU_EN = 0x40, 222 IDPF_TX_FLEX_DESC_CMD_FILT_AU_EVICT = 0x80, 223 }; 224 225 struct idpf_flex_tx_desc { 226 __le64 buf_addr; /* Packet buffer address */ 227 struct { 228 #define IDPF_FLEX_TXD_QW1_DTYPE_S 0 229 #define IDPF_FLEX_TXD_QW1_DTYPE_M GENMASK(4, 0) 230 #define IDPF_FLEX_TXD_QW1_CMD_S 5 231 #define IDPF_FLEX_TXD_QW1_CMD_M GENMASK(15, 5) 232 __le16 cmd_dtype; 233 union { 234 /* DTYPE=IDPF_TX_DESC_DTYPE_FLEX_L2TAG1_L2TAG2 (0x07) */ 235 struct { 236 __le16 l2tag1; 237 __le16 l2tag2; 238 } l2tags; 239 }; 240 __le16 buf_size; 241 } qw1; 242 }; 243 244 struct idpf_flex_tx_sched_desc { 245 __le64 buf_addr; /* Packet buffer address */ 246 247 /* DTYPE = IDPF_TX_DESC_DTYPE_FLEX_FLOW_SCHE_16B (0x0C) */ 248 struct { 249 u8 cmd_dtype; 250 #define IDPF_TXD_FLEX_FLOW_DTYPE_M 0x1F 251 #define IDPF_TXD_FLEX_FLOW_CMD_EOP 0x20 252 #define IDPF_TXD_FLEX_FLOW_CMD_CS_EN 0x40 253 #define IDPF_TXD_FLEX_FLOW_CMD_RE 0x80 254 255 u8 rsvd[3]; 256 257 __le16 compl_tag; 258 __le16 rxr_bufsize; 259 #define IDPF_TXD_FLEX_FLOW_RXR 0x4000 260 #define IDPF_TXD_FLEX_FLOW_BUFSIZE_M 0x3FFF 261 } qw1; 262 }; 263 264 /* Common cmd fields for all flex context descriptors 265 * Note: these defines already account for the 5 bit dtype in the cmd_dtype 266 * field 267 */ 268 enum idpf_tx_flex_ctx_desc_cmd_bits { 269 IDPF_TX_FLEX_CTX_DESC_CMD_TSO = 0x0020, 270 IDPF_TX_FLEX_CTX_DESC_CMD_TSYN_EN = 0x0040, 271 IDPF_TX_FLEX_CTX_DESC_CMD_L2TAG2 = 0x0080, 272 IDPF_TX_FLEX_CTX_DESC_CMD_SWTCH_UPLNK = 0x0200, /* 2 bits */ 273 IDPF_TX_FLEX_CTX_DESC_CMD_SWTCH_LOCAL = 0x0400, /* 2 bits */ 274 IDPF_TX_FLEX_CTX_DESC_CMD_SWTCH_TARGETVSI = 0x0600, /* 2 bits */ 275 }; 276 277 /* Standard flex descriptor TSO context quad word */ 278 struct idpf_flex_tx_tso_ctx_qw { 279 __le32 flex_tlen; 280 #define IDPF_TXD_FLEX_CTX_TLEN_M 0x3FFFF 281 #define IDPF_TXD_FLEX_TSO_CTX_FLEX_S 24 282 __le16 mss_rt; 283 #define IDPF_TXD_FLEX_CTX_MSS_RT_M 0x3FFF 284 u8 hdr_len; 285 u8 flex; 286 }; 287 288 union idpf_flex_tx_ctx_desc { 289 /* DTYPE = IDPF_TX_DESC_DTYPE_CTX (0x01) */ 290 struct { 291 struct { 292 u8 rsv[4]; 293 __le16 l2tag2; 294 u8 rsv_2[2]; 295 } qw0; 296 struct { 297 __le16 cmd_dtype; 298 __le16 tsyn_reg_l; 299 #define IDPF_TX_DESC_CTX_TSYN_L_M GENMASK(15, 14) 300 __le16 tsyn_reg_h; 301 #define IDPF_TX_DESC_CTX_TSYN_H_M GENMASK(15, 0) 302 __le16 mss; 303 #define IDPF_TX_DESC_CTX_MSS_M GENMASK(14, 2) 304 } qw1; 305 } tsyn; 306 307 /* DTYPE = IDPF_TX_DESC_DTYPE_FLEX_TSO_CTX (0x05) */ 308 struct { 309 struct idpf_flex_tx_tso_ctx_qw qw0; 310 struct { 311 __le16 cmd_dtype; 312 u8 flex[6]; 313 } qw1; 314 } tso; 315 }; 316 317 #endif /* _IDPF_LAN_TXRX_H_ */ 318