xref: /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_mmhub_v2_0.c (revision 41ec02673d281bbb3d38e6c78504ce6e30c228c1)
1 /*	$NetBSD: amdgpu_mmhub_v2_0.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $	*/
2 
3 /*
4  * Copyright 2019 Advanced Micro Devices, Inc.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  */
25 
26 #include <sys/cdefs.h>
27 __KERNEL_RCSID(0, "$NetBSD: amdgpu_mmhub_v2_0.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $");
28 
29 #include "amdgpu.h"
30 #include "mmhub_v2_0.h"
31 
32 #include "mmhub/mmhub_2_0_0_offset.h"
33 #include "mmhub/mmhub_2_0_0_sh_mask.h"
34 #include "mmhub/mmhub_2_0_0_default.h"
35 #include "navi10_enum.h"
36 
37 #include "soc15_common.h"
38 
mmhub_v2_0_setup_vm_pt_regs(struct amdgpu_device * adev,uint32_t vmid,uint64_t page_table_base)39 void mmhub_v2_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
40 				uint64_t page_table_base)
41 {
42 	/* two registers distance between mmMMVM_CONTEXT0_* to mmMMVM_CONTEXT1_* */
43 	int offset = mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32
44 			- mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
45 
46 	WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
47 			offset * vmid, lower_32_bits(page_table_base));
48 
49 	WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
50 			offset * vmid, upper_32_bits(page_table_base));
51 }
52 
mmhub_v2_0_init_gart_aperture_regs(struct amdgpu_device * adev)53 static void mmhub_v2_0_init_gart_aperture_regs(struct amdgpu_device *adev)
54 {
55 	uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
56 
57 	mmhub_v2_0_setup_vm_pt_regs(adev, 0, pt_base);
58 
59 	WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
60 		     (u32)(adev->gmc.gart_start >> 12));
61 	WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
62 		     (u32)(adev->gmc.gart_start >> 44));
63 
64 	WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
65 		     (u32)(adev->gmc.gart_end >> 12));
66 	WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
67 		     (u32)(adev->gmc.gart_end >> 44));
68 }
69 
mmhub_v2_0_init_system_aperture_regs(struct amdgpu_device * adev)70 static void mmhub_v2_0_init_system_aperture_regs(struct amdgpu_device *adev)
71 {
72 	uint64_t value;
73 	uint32_t tmp;
74 
75 	/* Disable AGP. */
76 	WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BASE, 0);
77 	WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_TOP, 0);
78 	WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BOT, 0x00FFFFFF);
79 
80 	/* Program the system aperture low logical page number. */
81 	WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR,
82 		     adev->gmc.vram_start >> 18);
83 	WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
84 		     adev->gmc.vram_end >> 18);
85 
86 	/* Set default page address. */
87 	value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +
88 		adev->vm_manager.vram_base_offset;
89 	WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
90 		     (u32)(value >> 12));
91 	WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
92 		     (u32)(value >> 44));
93 
94 	/* Program "protection fault". */
95 	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
96 		     (u32)(adev->dummy_page_addr >> 12));
97 	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
98 		     (u32)((u64)adev->dummy_page_addr >> 44));
99 
100 	tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2);
101 	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,
102 			    ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
103 	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2, tmp);
104 }
105 
mmhub_v2_0_init_tlb_regs(struct amdgpu_device * adev)106 static void mmhub_v2_0_init_tlb_regs(struct amdgpu_device *adev)
107 {
108 	uint32_t tmp;
109 
110 	/* Setup TLB control */
111 	tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL);
112 
113 	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
114 	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
115 	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
116 			    ENABLE_ADVANCED_DRIVER_MODEL, 1);
117 	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
118 			    SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
119 	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
120 	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
121 			    MTYPE, MTYPE_UC); /* UC, uncached */
122 
123 	WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp);
124 }
125 
mmhub_v2_0_init_cache_regs(struct amdgpu_device * adev)126 static void mmhub_v2_0_init_cache_regs(struct amdgpu_device *adev)
127 {
128 	uint32_t tmp;
129 
130 	/* Setup L2 cache */
131 	tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL);
132 	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);
133 	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
134 	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,
135 			    ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
136 	/* XXX for emulation, Refer to closed source code.*/
137 	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
138 			    0);
139 	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
140 	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
141 	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
142 	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL, tmp);
143 
144 	tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2);
145 	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
146 	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
147 	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2, tmp);
148 
149 	tmp = mmMMVM_L2_CNTL3_DEFAULT;
150 	if (adev->gmc.translate_further) {
151 		tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);
152 		tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
153 				    L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
154 	} else {
155 		tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);
156 		tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
157 				    L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
158 	}
159 	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, tmp);
160 
161 	tmp = mmMMVM_L2_CNTL4_DEFAULT;
162 	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
163 	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
164 	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL4, tmp);
165 }
166 
mmhub_v2_0_enable_system_domain(struct amdgpu_device * adev)167 static void mmhub_v2_0_enable_system_domain(struct amdgpu_device *adev)
168 {
169 	uint32_t tmp;
170 
171 	tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL);
172 	tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
173 	tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
174 	tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,
175 			    RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
176 	WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, tmp);
177 }
178 
mmhub_v2_0_disable_identity_aperture(struct amdgpu_device * adev)179 static void mmhub_v2_0_disable_identity_aperture(struct amdgpu_device *adev)
180 {
181 	WREG32_SOC15(MMHUB, 0,
182 		     mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
183 		     0xFFFFFFFF);
184 	WREG32_SOC15(MMHUB, 0,
185 		     mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
186 		     0x0000000F);
187 
188 	WREG32_SOC15(MMHUB, 0,
189 		     mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0);
190 	WREG32_SOC15(MMHUB, 0,
191 		     mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0);
192 
193 	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32,
194 		     0);
195 	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32,
196 		     0);
197 }
198 
mmhub_v2_0_setup_vmid_config(struct amdgpu_device * adev)199 static void mmhub_v2_0_setup_vmid_config(struct amdgpu_device *adev)
200 {
201 	int i;
202 	uint32_t tmp;
203 
204 	for (i = 0; i <= 14; i++) {
205 		tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, i);
206 		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
207 		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
208 				    adev->vm_manager.num_level);
209 		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
210 				    RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
211 		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
212 				    DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
213 				    1);
214 		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
215 				    PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
216 		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
217 				    VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
218 		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
219 				    READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
220 		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
221 				    WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
222 		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
223 				    EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
224 		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
225 				    PAGE_TABLE_BLOCK_SIZE,
226 				    adev->vm_manager.block_size - 9);
227 		/* Send no-retry XNACK on fault to suppress VM fault storm. */
228 		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
229 				    RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
230 				    !amdgpu_noretry);
231 		WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, i, tmp);
232 		WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0);
233 		WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0);
234 		WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, i*2,
235 			lower_32_bits(adev->vm_manager.max_pfn - 1));
236 		WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2,
237 			upper_32_bits(adev->vm_manager.max_pfn - 1));
238 	}
239 }
240 
mmhub_v2_0_program_invalidation(struct amdgpu_device * adev)241 static void mmhub_v2_0_program_invalidation(struct amdgpu_device *adev)
242 {
243 	unsigned i;
244 
245 	for (i = 0; i < 18; ++i) {
246 		WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
247 				    2 * i, 0xffffffff);
248 		WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
249 				    2 * i, 0x1f);
250 	}
251 }
252 
mmhub_v2_0_gart_enable(struct amdgpu_device * adev)253 int mmhub_v2_0_gart_enable(struct amdgpu_device *adev)
254 {
255 	if (amdgpu_sriov_vf(adev)) {
256 		/*
257 		 * MMMC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
258 		 * VF copy registers so vbios post doesn't program them, for
259 		 * SRIOV driver need to program them
260 		 */
261 		WREG32_SOC15(MMHUB, 0, mmMMMC_VM_FB_LOCATION_BASE,
262 			     adev->gmc.vram_start >> 24);
263 		WREG32_SOC15(MMHUB, 0, mmMMMC_VM_FB_LOCATION_TOP,
264 			     adev->gmc.vram_end >> 24);
265 	}
266 
267 	/* GART Enable. */
268 	mmhub_v2_0_init_gart_aperture_regs(adev);
269 	mmhub_v2_0_init_system_aperture_regs(adev);
270 	mmhub_v2_0_init_tlb_regs(adev);
271 	mmhub_v2_0_init_cache_regs(adev);
272 
273 	mmhub_v2_0_enable_system_domain(adev);
274 	mmhub_v2_0_disable_identity_aperture(adev);
275 	mmhub_v2_0_setup_vmid_config(adev);
276 	mmhub_v2_0_program_invalidation(adev);
277 
278 	return 0;
279 }
280 
mmhub_v2_0_gart_disable(struct amdgpu_device * adev)281 void mmhub_v2_0_gart_disable(struct amdgpu_device *adev)
282 {
283 	u32 tmp;
284 	u32 i;
285 
286 	/* Disable all tables */
287 	for (i = 0; i < 16; i++)
288 		WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, i, 0);
289 
290 	/* Setup TLB control */
291 	tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL);
292 	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
293 	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
294 			    ENABLE_ADVANCED_DRIVER_MODEL, 0);
295 	WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp);
296 
297 	/* Setup L2 cache */
298 	tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL);
299 	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0);
300 	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL, tmp);
301 	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, 0);
302 }
303 
304 /**
305  * mmhub_v2_0_set_fault_enable_default - update GART/VM fault handling
306  *
307  * @adev: amdgpu_device pointer
308  * @value: true redirects VM faults to the default page
309  */
mmhub_v2_0_set_fault_enable_default(struct amdgpu_device * adev,bool value)310 void mmhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev, bool value)
311 {
312 	u32 tmp;
313 	tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL);
314 	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
315 			    RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
316 	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
317 			    PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
318 	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
319 			    PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
320 	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
321 			    PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
322 	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
323 			    TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
324 			    value);
325 	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
326 			    NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
327 	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
328 			    DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
329 	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
330 			    VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
331 	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
332 			    READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
333 	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
334 			    WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
335 	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
336 			    EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
337 	if (!value) {
338 		tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
339 				CRASH_ON_NO_RETRY_FAULT, 1);
340 		tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
341 				CRASH_ON_RETRY_FAULT, 1);
342 	}
343 	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL, tmp);
344 }
345 
mmhub_v2_0_init(struct amdgpu_device * adev)346 void mmhub_v2_0_init(struct amdgpu_device *adev)
347 {
348 	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
349 
350 	hub->ctx0_ptb_addr_lo32 =
351 		SOC15_REG_OFFSET(MMHUB, 0,
352 				 mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
353 	hub->ctx0_ptb_addr_hi32 =
354 		SOC15_REG_OFFSET(MMHUB, 0,
355 				 mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
356 	hub->vm_inv_eng0_sem =
357 		SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_SEM);
358 	hub->vm_inv_eng0_req =
359 		SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_REQ);
360 	hub->vm_inv_eng0_ack =
361 		SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ACK);
362 	hub->vm_context0_cntl =
363 		SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL);
364 	hub->vm_l2_pro_fault_status =
365 		SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_STATUS);
366 	hub->vm_l2_pro_fault_cntl =
367 		SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL);
368 
369 }
370 
mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable)371 static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
372 							bool enable)
373 {
374 	uint32_t def, data, def1, data1;
375 
376 	def  = data  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);
377 
378 	def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);
379 
380 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
381 		data |= MM_ATC_L2_MISC_CG__ENABLE_MASK;
382 
383 		data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
384 		           DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
385 		           DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
386 		           DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
387 		           DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
388 		           DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
389 
390 	} else {
391 		data &= ~MM_ATC_L2_MISC_CG__ENABLE_MASK;
392 
393 		data1 |= (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
394 			  DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
395 			  DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
396 			  DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
397 			  DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
398 			  DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
399 	}
400 
401 	if (def != data)
402 		WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data);
403 
404 	if (def1 != data1)
405 		WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2, data1);
406 }
407 
mmhub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device * adev,bool enable)408 static void mmhub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
409 						       bool enable)
410 {
411 	uint32_t def, data;
412 
413 	def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);
414 
415 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
416 		data |= MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
417 	else
418 		data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
419 
420 	if (def != data)
421 		WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data);
422 }
423 
mmhub_v2_0_set_clockgating(struct amdgpu_device * adev,enum amd_clockgating_state state)424 int mmhub_v2_0_set_clockgating(struct amdgpu_device *adev,
425 			       enum amd_clockgating_state state)
426 {
427 	if (amdgpu_sriov_vf(adev))
428 		return 0;
429 
430 	switch (adev->asic_type) {
431 	case CHIP_NAVI10:
432 	case CHIP_NAVI14:
433 	case CHIP_NAVI12:
434 		mmhub_v2_0_update_medium_grain_clock_gating(adev,
435 				state == AMD_CG_STATE_GATE);
436 		mmhub_v2_0_update_medium_grain_light_sleep(adev,
437 				state == AMD_CG_STATE_GATE);
438 		break;
439 	default:
440 		break;
441 	}
442 
443 	return 0;
444 }
445 
mmhub_v2_0_get_clockgating(struct amdgpu_device * adev,u32 * flags)446 void mmhub_v2_0_get_clockgating(struct amdgpu_device *adev, u32 *flags)
447 {
448 	int data, data1;
449 
450 	if (amdgpu_sriov_vf(adev))
451 		*flags = 0;
452 
453 	data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);
454 
455 	data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);
456 
457 	/* AMD_CG_SUPPORT_MC_MGCG */
458 	if ((data & MM_ATC_L2_MISC_CG__ENABLE_MASK) &&
459 	    !(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
460 		       DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
461 		       DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
462 		       DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
463 		       DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
464 		       DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK)))
465 		*flags |= AMD_CG_SUPPORT_MC_MGCG;
466 
467 	/* AMD_CG_SUPPORT_MC_LS */
468 	if (data & MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)
469 		*flags |= AMD_CG_SUPPORT_MC_LS;
470 }
471