1 /* $NetBSD: amdgpu_mmhub_v1_0.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $ */
2
3 /*
4 * Copyright 2016 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25 #include <sys/cdefs.h>
26 __KERNEL_RCSID(0, "$NetBSD: amdgpu_mmhub_v1_0.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $");
27
28 #include "amdgpu.h"
29 #include "amdgpu_ras.h"
30 #include "mmhub_v1_0.h"
31
32 #include "mmhub/mmhub_1_0_offset.h"
33 #include "mmhub/mmhub_1_0_sh_mask.h"
34 #include "mmhub/mmhub_1_0_default.h"
35 #include "vega10_enum.h"
36 #include "soc15.h"
37 #include "soc15_common.h"
38
39 #define mmDAGB0_CNTL_MISC2_RV 0x008f
40 #define mmDAGB0_CNTL_MISC2_RV_BASE_IDX 0
41
mmhub_v1_0_get_fb_location(struct amdgpu_device * adev)42 u64 mmhub_v1_0_get_fb_location(struct amdgpu_device *adev)
43 {
44 u64 base = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE);
45 u64 top = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP);
46
47 base &= MC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
48 base <<= 24;
49
50 top &= MC_VM_FB_LOCATION_TOP__FB_TOP_MASK;
51 top <<= 24;
52
53 adev->gmc.fb_start = base;
54 adev->gmc.fb_end = top;
55
56 return base;
57 }
58
mmhub_v1_0_setup_vm_pt_regs(struct amdgpu_device * adev,uint32_t vmid,uint64_t page_table_base)59 void mmhub_v1_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
60 uint64_t page_table_base)
61 {
62 /* two registers distance between mmVM_CONTEXT0_* to mmVM_CONTEXT1_* */
63 int offset = mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32
64 - mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
65
66 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
67 offset * vmid, lower_32_bits(page_table_base));
68
69 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
70 offset * vmid, upper_32_bits(page_table_base));
71 }
72
mmhub_v1_0_init_gart_aperture_regs(struct amdgpu_device * adev)73 static void mmhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev)
74 {
75 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
76
77 mmhub_v1_0_setup_vm_pt_regs(adev, 0, pt_base);
78
79 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
80 (u32)(adev->gmc.gart_start >> 12));
81 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
82 (u32)(adev->gmc.gart_start >> 44));
83
84 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
85 (u32)(adev->gmc.gart_end >> 12));
86 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
87 (u32)(adev->gmc.gart_end >> 44));
88 }
89
mmhub_v1_0_init_system_aperture_regs(struct amdgpu_device * adev)90 static void mmhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
91 {
92 uint64_t value;
93 uint32_t tmp;
94
95 /* Program the AGP BAR */
96 WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BASE, 0);
97 WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
98 WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
99
100 /* Program the system aperture low logical page number. */
101 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
102 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
103
104 if (adev->asic_type == CHIP_RAVEN && adev->rev_id >= 0x8)
105 /*
106 * Raven2 has a HW issue that it is unable to use the vram which
107 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
108 * workaround that increase system aperture high address (add 1)
109 * to get rid of the VM fault and hardware hang.
110 */
111 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
112 max((adev->gmc.fb_end >> 18) + 0x1,
113 adev->gmc.agp_end >> 18));
114 else
115 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
116 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
117
118 if (amdgpu_sriov_vf(adev))
119 return;
120
121 /* Set default page address. */
122 value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +
123 adev->vm_manager.vram_base_offset;
124 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
125 (u32)(value >> 12));
126 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
127 (u32)(value >> 44));
128
129 /* Program "protection fault". */
130 WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
131 (u32)(adev->dummy_page_addr >> 12));
132 WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
133 (u32)((u64)adev->dummy_page_addr >> 44));
134
135 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2);
136 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,
137 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
138 WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2, tmp);
139 }
140
mmhub_v1_0_init_tlb_regs(struct amdgpu_device * adev)141 static void mmhub_v1_0_init_tlb_regs(struct amdgpu_device *adev)
142 {
143 uint32_t tmp;
144
145 /* Setup TLB control */
146 tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL);
147
148 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
149 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
150 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
151 ENABLE_ADVANCED_DRIVER_MODEL, 1);
152 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
153 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
154 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
155 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
156 MTYPE, MTYPE_UC);/* XXX for emulation. */
157 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
158
159 WREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
160 }
161
mmhub_v1_0_init_cache_regs(struct amdgpu_device * adev)162 static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
163 {
164 uint32_t tmp;
165
166 if (amdgpu_sriov_vf(adev))
167 return;
168
169 /* Setup L2 cache */
170 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL);
171 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
172 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
173 /* XXX for emulation, Refer to closed source code.*/
174 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
175 0);
176 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
177 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
178 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
179 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL, tmp);
180
181 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2);
182 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
183 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
184 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2, tmp);
185
186 if (adev->gmc.translate_further) {
187 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
188 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
189 L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
190 } else {
191 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
192 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
193 L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
194 }
195 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, tmp);
196
197 tmp = mmVM_L2_CNTL4_DEFAULT;
198 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
199 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
200 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL4, tmp);
201 }
202
mmhub_v1_0_enable_system_domain(struct amdgpu_device * adev)203 static void mmhub_v1_0_enable_system_domain(struct amdgpu_device *adev)
204 {
205 uint32_t tmp;
206
207 tmp = RREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL);
208 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
209 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
210 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL,
211 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
212 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL, tmp);
213 }
214
mmhub_v1_0_disable_identity_aperture(struct amdgpu_device * adev)215 static void mmhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev)
216 {
217 if (amdgpu_sriov_vf(adev))
218 return;
219
220 WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
221 0XFFFFFFFF);
222 WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
223 0x0000000F);
224
225 WREG32_SOC15(MMHUB, 0,
226 mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0);
227 WREG32_SOC15(MMHUB, 0,
228 mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0);
229
230 WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32,
231 0);
232 WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32,
233 0);
234 }
235
mmhub_v1_0_setup_vmid_config(struct amdgpu_device * adev)236 static void mmhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
237 {
238 unsigned num_level, block_size;
239 uint32_t tmp;
240 int i;
241
242 num_level = adev->vm_manager.num_level;
243 block_size = adev->vm_manager.block_size;
244 if (adev->gmc.translate_further)
245 num_level -= 1;
246 else
247 block_size -= 9;
248
249 for (i = 0; i <= 14; i++) {
250 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i);
251 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
252 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
253 num_level);
254 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
255 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
256 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
257 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
258 1);
259 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
260 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
261 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
262 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
263 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
264 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
265 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
266 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
267 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
268 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
269 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
270 PAGE_TABLE_BLOCK_SIZE,
271 block_size);
272 /* Send no-retry XNACK on fault to suppress VM fault storm. */
273 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
274 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
275 !amdgpu_noretry);
276 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i, tmp);
277 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0);
278 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0);
279 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, i*2,
280 lower_32_bits(adev->vm_manager.max_pfn - 1));
281 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2,
282 upper_32_bits(adev->vm_manager.max_pfn - 1));
283 }
284 }
285
mmhub_v1_0_program_invalidation(struct amdgpu_device * adev)286 static void mmhub_v1_0_program_invalidation(struct amdgpu_device *adev)
287 {
288 unsigned i;
289
290 for (i = 0; i < 18; ++i) {
291 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
292 2 * i, 0xffffffff);
293 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
294 2 * i, 0x1f);
295 }
296 }
297
mmhub_v1_0_update_power_gating(struct amdgpu_device * adev,bool enable)298 void mmhub_v1_0_update_power_gating(struct amdgpu_device *adev,
299 bool enable)
300 {
301 if (amdgpu_sriov_vf(adev))
302 return;
303
304 if (enable && adev->pg_flags & AMD_PG_SUPPORT_MMHUB) {
305 if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_powergating_by_smu)
306 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GMC, true);
307
308 }
309 }
310
mmhub_v1_0_gart_enable(struct amdgpu_device * adev)311 int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
312 {
313 if (amdgpu_sriov_vf(adev)) {
314 /*
315 * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
316 * VF copy registers so vbios post doesn't program them, for
317 * SRIOV driver need to program them
318 */
319 WREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE,
320 adev->gmc.vram_start >> 24);
321 WREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP,
322 adev->gmc.vram_end >> 24);
323 }
324
325 /* GART Enable. */
326 mmhub_v1_0_init_gart_aperture_regs(adev);
327 mmhub_v1_0_init_system_aperture_regs(adev);
328 mmhub_v1_0_init_tlb_regs(adev);
329 mmhub_v1_0_init_cache_regs(adev);
330
331 mmhub_v1_0_enable_system_domain(adev);
332 mmhub_v1_0_disable_identity_aperture(adev);
333 mmhub_v1_0_setup_vmid_config(adev);
334 mmhub_v1_0_program_invalidation(adev);
335
336 return 0;
337 }
338
mmhub_v1_0_gart_disable(struct amdgpu_device * adev)339 void mmhub_v1_0_gart_disable(struct amdgpu_device *adev)
340 {
341 u32 tmp;
342 u32 i;
343
344 /* Disable all tables */
345 for (i = 0; i < 16; i++)
346 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL, i, 0);
347
348 /* Setup TLB control */
349 tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL);
350 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
351 tmp = REG_SET_FIELD(tmp,
352 MC_VM_MX_L1_TLB_CNTL,
353 ENABLE_ADVANCED_DRIVER_MODEL,
354 0);
355 WREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
356
357 if (!amdgpu_sriov_vf(adev)) {
358 /* Setup L2 cache */
359 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL);
360 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
361 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL, tmp);
362 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, 0);
363 }
364 }
365
366 /**
367 * mmhub_v1_0_set_fault_enable_default - update GART/VM fault handling
368 *
369 * @adev: amdgpu_device pointer
370 * @value: true redirects VM faults to the default page
371 */
mmhub_v1_0_set_fault_enable_default(struct amdgpu_device * adev,bool value)372 void mmhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, bool value)
373 {
374 u32 tmp;
375
376 if (amdgpu_sriov_vf(adev))
377 return;
378
379 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
380 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
381 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
382 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
383 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
384 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
385 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
386 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
387 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
388 tmp = REG_SET_FIELD(tmp,
389 VM_L2_PROTECTION_FAULT_CNTL,
390 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
391 value);
392 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
393 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
394 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
395 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
396 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
397 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
398 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
399 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
400 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
401 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
402 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
403 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
404 if (!value) {
405 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
406 CRASH_ON_NO_RETRY_FAULT, 1);
407 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
408 CRASH_ON_RETRY_FAULT, 1);
409 }
410
411 WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp);
412 }
413
mmhub_v1_0_init(struct amdgpu_device * adev)414 void mmhub_v1_0_init(struct amdgpu_device *adev)
415 {
416 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
417
418 hub->ctx0_ptb_addr_lo32 =
419 SOC15_REG_OFFSET(MMHUB, 0,
420 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
421 hub->ctx0_ptb_addr_hi32 =
422 SOC15_REG_OFFSET(MMHUB, 0,
423 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
424 hub->vm_inv_eng0_sem =
425 SOC15_REG_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_SEM);
426 hub->vm_inv_eng0_req =
427 SOC15_REG_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_REQ);
428 hub->vm_inv_eng0_ack =
429 SOC15_REG_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ACK);
430 hub->vm_context0_cntl =
431 SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL);
432 hub->vm_l2_pro_fault_status =
433 SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_STATUS);
434 hub->vm_l2_pro_fault_cntl =
435 SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
436
437 }
438
mmhub_v1_0_update_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable)439 static void mmhub_v1_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
440 bool enable)
441 {
442 uint32_t def, data, def1, data1, def2 = 0, data2 = 0;
443
444 def = data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG);
445
446 if (adev->asic_type != CHIP_RAVEN) {
447 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);
448 def2 = data2 = RREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2);
449 } else
450 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_RV);
451
452 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
453 data |= ATC_L2_MISC_CG__ENABLE_MASK;
454
455 data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
456 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
457 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
458 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
459 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
460 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
461
462 if (adev->asic_type != CHIP_RAVEN)
463 data2 &= ~(DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
464 DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
465 DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
466 DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
467 DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
468 DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
469 } else {
470 data &= ~ATC_L2_MISC_CG__ENABLE_MASK;
471
472 data1 |= (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
473 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
474 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
475 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
476 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
477 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
478
479 if (adev->asic_type != CHIP_RAVEN)
480 data2 |= (DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
481 DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
482 DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
483 DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
484 DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
485 DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
486 }
487
488 if (def != data)
489 WREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG, data);
490
491 if (def1 != data1) {
492 if (adev->asic_type != CHIP_RAVEN)
493 WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2, data1);
494 else
495 WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_RV, data1);
496 }
497
498 if (adev->asic_type != CHIP_RAVEN && def2 != data2)
499 WREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2, data2);
500 }
501
mmhub_v1_0_update_medium_grain_light_sleep(struct amdgpu_device * adev,bool enable)502 static void mmhub_v1_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
503 bool enable)
504 {
505 uint32_t def, data;
506
507 def = data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG);
508
509 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
510 data |= ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
511 else
512 data &= ~ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
513
514 if (def != data)
515 WREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG, data);
516 }
517
mmhub_v1_0_set_clockgating(struct amdgpu_device * adev,enum amd_clockgating_state state)518 int mmhub_v1_0_set_clockgating(struct amdgpu_device *adev,
519 enum amd_clockgating_state state)
520 {
521 if (amdgpu_sriov_vf(adev))
522 return 0;
523
524 switch (adev->asic_type) {
525 case CHIP_VEGA10:
526 case CHIP_VEGA12:
527 case CHIP_VEGA20:
528 case CHIP_RAVEN:
529 case CHIP_RENOIR:
530 mmhub_v1_0_update_medium_grain_clock_gating(adev,
531 state == AMD_CG_STATE_GATE);
532 mmhub_v1_0_update_medium_grain_light_sleep(adev,
533 state == AMD_CG_STATE_GATE);
534 break;
535 default:
536 break;
537 }
538
539 return 0;
540 }
541
mmhub_v1_0_get_clockgating(struct amdgpu_device * adev,u32 * flags)542 void mmhub_v1_0_get_clockgating(struct amdgpu_device *adev, u32 *flags)
543 {
544 int data, data1;
545
546 if (amdgpu_sriov_vf(adev))
547 *flags = 0;
548
549 data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG);
550
551 data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);
552
553 /* AMD_CG_SUPPORT_MC_MGCG */
554 if ((data & ATC_L2_MISC_CG__ENABLE_MASK) &&
555 !(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
556 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
557 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
558 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
559 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
560 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK)))
561 *flags |= AMD_CG_SUPPORT_MC_MGCG;
562
563 /* AMD_CG_SUPPORT_MC_LS */
564 if (data & ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)
565 *flags |= AMD_CG_SUPPORT_MC_LS;
566 }
567
568 static const struct soc15_ras_field_entry mmhub_v1_0_ras_fields[] = {
569 { "MMEA0_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20),
570 SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMRD_CMDMEM_SEC_COUNT),
571 SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMRD_CMDMEM_DED_COUNT),
572 },
573 { "MMEA0_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20),
574 SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMWR_CMDMEM_SEC_COUNT),
575 SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMWR_CMDMEM_DED_COUNT),
576 },
577 { "MMEA0_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20),
578 SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMWR_DATAMEM_SEC_COUNT),
579 SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMWR_DATAMEM_DED_COUNT),
580 },
581 { "MMEA0_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20),
582 SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, RRET_TAGMEM_SEC_COUNT),
583 SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, RRET_TAGMEM_DED_COUNT),
584 },
585 { "MMEA0_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20),
586 SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, WRET_TAGMEM_SEC_COUNT),
587 SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, WRET_TAGMEM_DED_COUNT),
588 },
589 { "MMEA0_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20),
590 SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMRD_PAGEMEM_SED_COUNT),
591 0, 0,
592 },
593 { "MMEA0_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20),
594 SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMWR_PAGEMEM_SED_COUNT),
595 0, 0,
596 },
597 { "MMEA0_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20),
598 SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, IORD_CMDMEM_SED_COUNT),
599 0, 0,
600 },
601 { "MMEA0_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20),
602 SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, IOWR_CMDMEM_SED_COUNT),
603 0, 0,
604 },
605 { "MMEA0_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20),
606 SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, IOWR_DATAMEM_SED_COUNT),
607 0, 0,
608 },
609 { "MMEA0_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20),
610 SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIRD_CMDMEM_SEC_COUNT),
611 SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIRD_CMDMEM_DED_COUNT),
612 },
613 { "MMEA0_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20),
614 SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIWR_CMDMEM_SEC_COUNT),
615 SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIWR_CMDMEM_DED_COUNT),
616 },
617 { "MMEA0_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20),
618 SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIWR_DATAMEM_SEC_COUNT),
619 SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIWR_DATAMEM_DED_COUNT),
620 },
621 { "MMEA0_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20),
622 SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIRD_PAGEMEM_SED_COUNT),
623 0, 0,
624 },
625 { "MMEA0_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20),
626 SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIWR_PAGEMEM_SED_COUNT),
627 0, 0,
628 },
629 { "MMEA1_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20),
630 SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMRD_CMDMEM_SEC_COUNT),
631 SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMRD_CMDMEM_DED_COUNT),
632 },
633 { "MMEA1_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20),
634 SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMWR_CMDMEM_SEC_COUNT),
635 SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMWR_CMDMEM_DED_COUNT),
636 },
637 { "MMEA1_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20),
638 SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMWR_DATAMEM_SEC_COUNT),
639 SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMWR_DATAMEM_DED_COUNT),
640 },
641 { "MMEA1_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20),
642 SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, RRET_TAGMEM_SEC_COUNT),
643 SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, RRET_TAGMEM_DED_COUNT),
644 },
645 { "MMEA1_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20),
646 SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, WRET_TAGMEM_SEC_COUNT),
647 SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, WRET_TAGMEM_DED_COUNT),
648 },
649 { "MMEA1_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20),
650 SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMRD_PAGEMEM_SED_COUNT),
651 0, 0,
652 },
653 { "MMEA1_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20),
654 SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMWR_PAGEMEM_SED_COUNT),
655 0, 0,
656 },
657 { "MMEA1_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20),
658 SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, IORD_CMDMEM_SED_COUNT),
659 0, 0,
660 },
661 { "MMEA1_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20),
662 SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, IOWR_CMDMEM_SED_COUNT),
663 0, 0,
664 },
665 { "MMEA1_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20),
666 SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, IOWR_DATAMEM_SED_COUNT),
667 0, 0,
668 },
669 { "MMEA1_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20),
670 SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIRD_CMDMEM_SEC_COUNT),
671 SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIRD_CMDMEM_DED_COUNT),
672 },
673 { "MMEA1_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20),
674 SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIWR_CMDMEM_SEC_COUNT),
675 SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIWR_CMDMEM_DED_COUNT),
676 },
677 { "MMEA1_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20),
678 SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIWR_DATAMEM_SEC_COUNT),
679 SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIWR_DATAMEM_DED_COUNT),
680 },
681 { "MMEA1_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20),
682 SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIRD_PAGEMEM_SED_COUNT),
683 0, 0,
684 },
685 { "MMEA1_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20),
686 SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIWR_PAGEMEM_SED_COUNT),
687 0, 0,
688 }
689 };
690
691 static const struct soc15_reg_entry mmhub_v1_0_edc_cnt_regs[] = {
692 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20), 0, 0, 0},
693 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20), 0, 0, 0},
694 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20), 0, 0, 0},
695 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20), 0, 0, 0},
696 };
697
mmhub_v1_0_get_ras_error_count(const struct soc15_reg_entry * reg,uint32_t value,uint32_t * sec_count,uint32_t * ded_count)698 static int mmhub_v1_0_get_ras_error_count(const struct soc15_reg_entry *reg,
699 uint32_t value, uint32_t *sec_count, uint32_t *ded_count)
700 {
701 uint32_t i;
702 uint32_t sec_cnt, ded_cnt;
703
704 for (i = 0; i < ARRAY_SIZE(mmhub_v1_0_ras_fields); i++) {
705 if(mmhub_v1_0_ras_fields[i].reg_offset != reg->reg_offset)
706 continue;
707
708 sec_cnt = (value &
709 mmhub_v1_0_ras_fields[i].sec_count_mask) >>
710 mmhub_v1_0_ras_fields[i].sec_count_shift;
711 if (sec_cnt) {
712 DRM_INFO("MMHUB SubBlock %s, SEC %d\n",
713 mmhub_v1_0_ras_fields[i].name,
714 sec_cnt);
715 *sec_count += sec_cnt;
716 }
717
718 ded_cnt = (value &
719 mmhub_v1_0_ras_fields[i].ded_count_mask) >>
720 mmhub_v1_0_ras_fields[i].ded_count_shift;
721 if (ded_cnt) {
722 DRM_INFO("MMHUB SubBlock %s, DED %d\n",
723 mmhub_v1_0_ras_fields[i].name,
724 ded_cnt);
725 *ded_count += ded_cnt;
726 }
727 }
728
729 return 0;
730 }
731
mmhub_v1_0_query_ras_error_count(struct amdgpu_device * adev,void * ras_error_status)732 static void mmhub_v1_0_query_ras_error_count(struct amdgpu_device *adev,
733 void *ras_error_status)
734 {
735 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
736 uint32_t sec_count = 0, ded_count = 0;
737 uint32_t i;
738 uint32_t reg_value;
739
740 err_data->ue_count = 0;
741 err_data->ce_count = 0;
742
743 for (i = 0; i < ARRAY_SIZE(mmhub_v1_0_edc_cnt_regs); i++) {
744 reg_value =
745 RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_0_edc_cnt_regs[i]));
746 if (reg_value)
747 mmhub_v1_0_get_ras_error_count(&mmhub_v1_0_edc_cnt_regs[i],
748 reg_value, &sec_count, &ded_count);
749 }
750
751 err_data->ce_count += sec_count;
752 err_data->ue_count += ded_count;
753 }
754
755 const struct amdgpu_mmhub_funcs mmhub_v1_0_funcs = {
756 .ras_late_init = amdgpu_mmhub_ras_late_init,
757 .query_ras_error_count = mmhub_v1_0_query_ras_error_count,
758 };
759