1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2022 Intel Corporation
3 */
4 #ifndef _QAT_QP_H_
5 #define _QAT_QP_H_
6
7 #include "qat_common.h"
8 #include "adf_transport_access_macros.h"
9
10 #define QAT_CSR_HEAD_WRITE_THRESH 32U
11 /* number of requests to accumulate before writing head CSR */
12
13 #define QAT_QP_MIN_INFL_THRESHOLD 256
14
15 struct qat_qp;
16 struct qat_pci_device;
17
18 /**
19 * Structure associated with each queue.
20 */
21 struct qat_queue {
22 char memz_name[RTE_MEMZONE_NAMESIZE];
23 void *base_addr; /* Base address */
24 rte_iova_t base_phys_addr; /* Queue physical address */
25 uint32_t head; /* Shadow copy of the head */
26 uint32_t tail; /* Shadow copy of the tail */
27 uint32_t modulo_mask;
28 uint32_t msg_size;
29 uint32_t queue_size;
30 uint8_t trailz;
31 uint8_t hw_bundle_number;
32 uint8_t hw_queue_number;
33 /* HW queue aka ring offset on bundle */
34 uint32_t csr_head; /* last written head value */
35 uint32_t csr_tail; /* last written tail value */
36 uint16_t nb_processed_responses;
37 /* number of responses processed since last CSR head write */
38 };
39
40 /**
41 * Type define qat_op_build_request_t function pointer, passed in as argument
42 * in enqueue op burst, where a build request assigned base on the type of
43 * crypto op.
44 *
45 * @param in_op
46 * An input op pointer
47 * @param out_msg
48 * out_meg pointer
49 * @param op_cookie
50 * op cookie pointer
51 * @param opaque
52 * an opaque data may be used to store context may be useful between
53 * 2 enqueue operations.
54 * @param dev_gen
55 * qat device gen id
56 * @return
57 * - 0 if the crypto request is build successfully,
58 * - EINVAL if error
59 **/
60 typedef int (*qat_op_build_request_t)(void *in_op, uint8_t *out_msg,
61 void *op_cookie, struct qat_qp *qp);
62
63 /**
64 * Type define qat_op_dequeue_t function pointer, passed in as argument
65 * in dequeue op burst, where a dequeue op assigned base on the type of
66 * crypto op.
67 *
68 * @param op
69 * An input op pointer
70 * @param resp
71 * qat response msg pointer
72 * @param op_cookie
73 * op cookie pointer
74 * @param dequeue_err_count
75 * dequeue error counter
76 * @return
77 * - 0 if dequeue OP is successful
78 * - EINVAL if error
79 **/
80 typedef int (*qat_op_dequeue_t)(void **op, uint8_t *resp, void *op_cookie,
81 uint64_t *dequeue_err_count __rte_unused);
82
83 #define QAT_BUILD_REQUEST_MAX_OPAQUE_SIZE 2
84
85 struct __rte_cache_aligned qat_qp {
86 void *mmap_bar_addr;
87 struct qat_queue tx_q;
88 struct qat_queue rx_q;
89 struct qat_common_stats stats;
90 struct rte_mempool *op_cookie_pool;
91 void **op_cookies;
92 uint32_t nb_descriptors;
93 uint64_t opaque[QAT_BUILD_REQUEST_MAX_OPAQUE_SIZE];
94 enum qat_device_gen qat_dev_gen;
95 enum qat_service_type service_type;
96 struct qat_pci_device *qat_dev;
97 /**< qat device this qp is on */
98 uint32_t enqueued;
99 alignas(sizeof(uint32_t)) uint32_t dequeued;
100 uint16_t max_inflights;
101 uint16_t min_enq_burst_threshold;
102 };
103
104 /**
105 * Structure with data needed for creation of queue pair.
106 */
107 struct qat_qp_hw_data {
108 enum qat_service_type service_type;
109 uint8_t hw_bundle_num;
110 uint8_t tx_ring_num;
111 uint8_t rx_ring_num;
112 uint16_t tx_msg_size;
113 uint16_t rx_msg_size;
114 };
115
116 /**
117 * Structure with data needed for creation of queue pair.
118 */
119 struct qat_qp_config {
120 const struct qat_qp_hw_data *hw;
121 uint32_t nb_descriptors;
122 uint32_t cookie_size;
123 int socket_id;
124 const char *service_str;
125 };
126
127 uint16_t
128 qat_enqueue_op_burst(void *qp, qat_op_build_request_t op_build_request,
129 void **ops, uint16_t nb_ops);
130
131 uint16_t
132 qat_dequeue_op_burst(void *qp, void **ops,
133 qat_op_dequeue_t qat_dequeue_process_response, uint16_t nb_ops);
134
135 int
136 qat_qp_release(enum qat_device_gen qat_dev_gen, struct qat_qp **qp_addr);
137
138 int
139 qat_qp_setup(struct qat_pci_device *qat_dev,
140 struct qat_qp **qp_addr, uint16_t queue_pair_id,
141 struct qat_qp_config *qat_qp_conf);
142
143 int
144 qat_qps_per_service(struct qat_pci_device *qat_dev,
145 enum qat_service_type service);
146
147 const struct qat_qp_hw_data *
148 qat_qp_get_hw_data(struct qat_pci_device *qat_dev,
149 enum qat_service_type service, uint16_t qp_id);
150
151 int
152 qat_cq_get_fw_version(struct qat_qp *qp);
153
154 #ifdef BUILD_QAT_SYM
155 int
156 qat_cq_get_fw_cipher_crc_cap(struct qat_qp *qp);
157 #endif
158
159 /* Needed for weak function*/
160 int
161 qat_comp_process_response(void **op __rte_unused, uint8_t *resp __rte_unused,
162 void *op_cookie __rte_unused,
163 uint64_t *dequeue_err_count __rte_unused);
164 int
165 qat_read_qp_config(struct qat_pci_device *qat_dev);
166
167 /**
168 * Function prototypes for GENx specific queue pair operations.
169 **/
170 typedef int (*qat_qp_rings_per_service_t)
171 (struct qat_pci_device *, enum qat_service_type);
172
173 typedef void (*qat_qp_build_ring_base_t)(void *, struct qat_queue *);
174
175 typedef void (*qat_qp_adf_arb_enable_t)(const struct qat_queue *, void *,
176 rte_spinlock_t *);
177
178 typedef void (*qat_qp_adf_arb_disable_t)(const struct qat_queue *, void *,
179 rte_spinlock_t *);
180
181 typedef void (*qat_qp_adf_configure_queues_t)(struct qat_qp *);
182
183 typedef void (*qat_qp_csr_write_tail_t)(struct qat_qp *qp, struct qat_queue *q);
184
185 typedef void (*qat_qp_csr_write_head_t)(struct qat_qp *qp, struct qat_queue *q,
186 uint32_t new_head);
187
188 typedef void (*qat_qp_csr_setup_t)(struct qat_pci_device*, void *,
189 struct qat_qp *);
190
191 typedef const struct qat_qp_hw_data * (*qat_qp_get_hw_data_t)(
192 struct qat_pci_device *dev, enum qat_service_type service_type,
193 uint16_t qp_id);
194
195 struct qat_qp_hw_spec_funcs {
196 qat_qp_rings_per_service_t qat_qp_rings_per_service;
197 qat_qp_build_ring_base_t qat_qp_build_ring_base;
198 qat_qp_adf_arb_enable_t qat_qp_adf_arb_enable;
199 qat_qp_adf_arb_disable_t qat_qp_adf_arb_disable;
200 qat_qp_adf_configure_queues_t qat_qp_adf_configure_queues;
201 qat_qp_csr_write_tail_t qat_qp_csr_write_tail;
202 qat_qp_csr_write_head_t qat_qp_csr_write_head;
203 qat_qp_csr_setup_t qat_qp_csr_setup;
204 qat_qp_get_hw_data_t qat_qp_get_hw_data;
205 };
206
207 extern struct qat_qp_hw_spec_funcs*
208 qat_qp_hw_spec[];
209
210 static inline void
txq_write_tail(enum qat_device_gen qat_dev_gen,struct qat_qp * qp,struct qat_queue * q)211 txq_write_tail(enum qat_device_gen qat_dev_gen,
212 struct qat_qp *qp, struct qat_queue *q)
213 {
214 struct qat_qp_hw_spec_funcs *ops =
215 qat_qp_hw_spec[qat_dev_gen];
216
217 /*
218 * Pointer check should be done during
219 * initialization
220 */
221 ops->qat_qp_csr_write_tail(qp, q);
222 }
223
224 #endif /* _QAT_QP_H_ */
225