1 /* Subroutines for insn-output.c for MIPS
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2005 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky, lich@inria.inria.fr.
5 Changes by Michael Meissner, meissner@osf.org.
6 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
7 Brendan Eich, brendan@microunity.com.
8
9 This file is part of GNU CC.
10
11 GNU CC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
14 any later version.
15
16 GNU CC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with GNU CC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
25
26 /* ??? The TARGET_FP_CALL_32 macros are intended to simulate a 32 bit
27 calling convention in 64 bit mode. It doesn't work though, and should
28 be replaced with something better designed. */
29
30 #include "config.h"
31 #include "system.h"
32 #include <signal.h>
33 #include "rtl.h"
34 #include "regs.h"
35 #include "hard-reg-set.h"
36 #include "real.h"
37 #include "insn-config.h"
38 #include "conditions.h"
39 #include "insn-attr.h"
40 #include "recog.h"
41 #include "toplev.h"
42 #include "output.h"
43 #include "tree.h"
44 #include "function.h"
45 #include "expr.h"
46 #include "flags.h"
47 #include "reload.h"
48 #include "output.h"
49 #include "tm_p.h"
50 #include "ggc.h"
51 #include "gstab.h"
52 #include "hashtab.h"
53 #include "debug.h"
54 #include "target.h"
55 #include "target-def.h"
56
57 #ifdef __GNU_STAB__
58 #define STAB_CODE_TYPE enum __stab_debug_code
59 #else
60 #define STAB_CODE_TYPE int
61 #endif
62
63 extern tree lookup_name PARAMS ((tree));
64
65 /* Enumeration for all of the relational tests, so that we can build
66 arrays indexed by the test type, and not worry about the order
67 of EQ, NE, etc. */
68
69 enum internal_test {
70 ITEST_EQ,
71 ITEST_NE,
72 ITEST_GT,
73 ITEST_GE,
74 ITEST_LT,
75 ITEST_LE,
76 ITEST_GTU,
77 ITEST_GEU,
78 ITEST_LTU,
79 ITEST_LEU,
80 ITEST_MAX
81 };
82
83
84 struct constant;
85 struct mips_arg_info;
86 static enum internal_test map_test_to_internal_test PARAMS ((enum rtx_code));
87 static void get_float_compare_codes PARAMS ((enum rtx_code, enum rtx_code *,
88 enum rtx_code *));
89 static int mips16_simple_memory_operand PARAMS ((rtx, rtx,
90 enum machine_mode));
91 static int m16_check_op PARAMS ((rtx, int, int, int));
92 static void block_move_loop PARAMS ((rtx, rtx,
93 unsigned int,
94 int,
95 rtx, rtx));
96 static void block_move_call PARAMS ((rtx, rtx, rtx));
97 static void mips_arg_info PARAMS ((const CUMULATIVE_ARGS *,
98 enum machine_mode,
99 tree, int,
100 struct mips_arg_info *));
101 static rtx mips_add_large_offset_to_sp PARAMS ((HOST_WIDE_INT));
102 static void mips_annotate_frame_insn PARAMS ((rtx, rtx));
103 static rtx mips_frame_set PARAMS ((enum machine_mode,
104 int, int));
105 static void mips_emit_frame_related_store PARAMS ((rtx, rtx,
106 HOST_WIDE_INT));
107 static void save_restore_insns PARAMS ((int, rtx, long));
108 static void mips16_output_gp_offset PARAMS ((FILE *, rtx));
109 static void mips16_fp_args PARAMS ((FILE *, int, int));
110 static void build_mips16_function_stub PARAMS ((FILE *));
111 static void mips16_optimize_gp PARAMS ((rtx));
112 static rtx add_constant PARAMS ((struct constant **,
113 rtx,
114 enum machine_mode));
115 static void dump_constants PARAMS ((struct constant *,
116 rtx));
117 static rtx mips_find_symbol PARAMS ((rtx));
118 static void abort_with_insn PARAMS ((rtx, const char *))
119 ATTRIBUTE_NORETURN;
120 static int symbolic_expression_p PARAMS ((rtx));
121 static bool mips_assemble_integer PARAMS ((rtx, unsigned int, int));
122 static void mips_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
123 static void mips_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
124 static void mips_set_architecture PARAMS ((const struct mips_cpu_info *));
125 static void mips_set_tune PARAMS ((const struct mips_cpu_info *));
126 static bool mips_strict_matching_cpu_name_p PARAMS ((const char *,
127 const char *));
128 static bool mips_matching_cpu_name_p PARAMS ((const char *,
129 const char *));
130 static const struct mips_cpu_info *mips_parse_cpu PARAMS ((const char *,
131 const char *));
132 static const struct mips_cpu_info *mips_cpu_info_from_isa PARAMS ((int));
133 static void copy_file_data PARAMS ((FILE *, FILE *));
134 #ifdef TARGET_IRIX6
135 static void iris6_asm_named_section_1 PARAMS ((const char *,
136 unsigned int,
137 unsigned int));
138 static void iris6_asm_named_section PARAMS ((const char *,
139 unsigned int));
140 static int iris_section_align_entry_eq PARAMS ((const PTR, const PTR));
141 static hashval_t iris_section_align_entry_hash PARAMS ((const PTR));
142 static int iris6_section_align_1 PARAMS ((void **, void *));
143 #endif
144 static int mips_adjust_cost PARAMS ((rtx, rtx, rtx, int));
145 static int mips_issue_rate PARAMS ((void));
146
147 static struct machine_function * mips_init_machine_status PARAMS ((void));
148 static void mips_select_section PARAMS ((tree, int, unsigned HOST_WIDE_INT))
149 ATTRIBUTE_UNUSED;
150 static void mips_unique_section PARAMS ((tree, int))
151 ATTRIBUTE_UNUSED;
152 static void mips_select_rtx_section PARAMS ((enum machine_mode, rtx,
153 unsigned HOST_WIDE_INT));
154 static int mips_use_dfa_pipeline_interface PARAMS ((void));
155 static void mips_encode_section_info PARAMS ((tree, int));
156
157 /* Structure to be filled in by compute_frame_size with register
158 save masks, and offsets for the current function. */
159
160 struct mips_frame_info GTY(())
161 {
162 long total_size; /* # bytes that the entire frame takes up */
163 long var_size; /* # bytes that variables take up */
164 long args_size; /* # bytes that outgoing arguments take up */
165 long extra_size; /* # bytes of extra gunk */
166 int gp_reg_size; /* # bytes needed to store gp regs */
167 int fp_reg_size; /* # bytes needed to store fp regs */
168 long mask; /* mask of saved gp registers */
169 long fmask; /* mask of saved fp registers */
170 long gp_save_offset; /* offset from vfp to store gp registers */
171 long fp_save_offset; /* offset from vfp to store fp registers */
172 long gp_sp_offset; /* offset from new sp to store gp registers */
173 long fp_sp_offset; /* offset from new sp to store fp registers */
174 int initialized; /* != 0 if frame size already calculated */
175 int num_gp; /* number of gp registers saved */
176 int num_fp; /* number of fp registers saved */
177 };
178
179 struct machine_function GTY(()) {
180 /* Pseudo-reg holding the address of the current function when
181 generating embedded PIC code. Created by LEGITIMIZE_ADDRESS,
182 used by mips_finalize_pic if it was created. */
183 rtx embedded_pic_fnaddr_rtx;
184
185 /* Pseudo-reg holding the value of $28 in a mips16 function which
186 refers to GP relative global variables. */
187 rtx mips16_gp_pseudo_rtx;
188
189 /* Current frame information, calculated by compute_frame_size. */
190 struct mips_frame_info frame;
191
192 /* Length of instructions in function; mips16 only. */
193 long insns_len;
194 };
195
196 /* Information about a single argument. */
197 struct mips_arg_info
198 {
199 /* True if the argument is a record or union type. */
200 bool struct_p;
201
202 /* True if the argument is passed in a floating-point register, or
203 would have been if we hadn't run out of registers. */
204 bool fpr_p;
205
206 /* The argument's size, in bytes. */
207 unsigned int num_bytes;
208
209 /* The number of words passed in registers, rounded up. */
210 unsigned int reg_words;
211
212 /* The offset of the first register from GP_ARG_FIRST or FP_ARG_FIRST,
213 or MAX_ARGS_IN_REGISTERS if the argument is passed entirely
214 on the stack. */
215 unsigned int reg_offset;
216
217 /* The number of words that must be passed on the stack, rounded up. */
218 unsigned int stack_words;
219
220 /* The offset from the start of the stack overflow area of the argument's
221 first stack word. Only meaningful when STACK_WORDS is nonzero. */
222 unsigned int stack_offset;
223 };
224
225 /* Global variables for machine-dependent things. */
226
227 /* Threshold for data being put into the small data/bss area, instead
228 of the normal data area (references to the small data/bss area take
229 1 instruction, and use the global pointer, references to the normal
230 data area takes 2 instructions). */
231 int mips_section_threshold = -1;
232
233 /* Count the number of .file directives, so that .loc is up to date. */
234 int num_source_filenames = 0;
235
236 /* Count the number of sdb related labels are generated (to find block
237 start and end boundaries). */
238 int sdb_label_count = 0;
239
240 /* Next label # for each statement for Silicon Graphics IRIS systems. */
241 int sym_lineno = 0;
242
243 /* Nonzero if inside of a function, because the stupid MIPS asm can't
244 handle .files inside of functions. */
245 int inside_function = 0;
246
247 /* Files to separate the text and the data output, so that all of the data
248 can be emitted before the text, which will mean that the assembler will
249 generate smaller code, based on the global pointer. */
250 FILE *asm_out_data_file;
251 FILE *asm_out_text_file;
252
253 /* Linked list of all externals that are to be emitted when optimizing
254 for the global pointer if they haven't been declared by the end of
255 the program with an appropriate .comm or initialization. */
256
257 struct extern_list
258 {
259 struct extern_list *next; /* next external */
260 const char *name; /* name of the external */
261 int size; /* size in bytes */
262 } *extern_head = 0;
263
264 /* Name of the file containing the current function. */
265 const char *current_function_file = "";
266
267 /* Warning given that Mips ECOFF can't support changing files
268 within a function. */
269 int file_in_function_warning = FALSE;
270
271 /* Whether to suppress issuing .loc's because the user attempted
272 to change the filename within a function. */
273 int ignore_line_number = FALSE;
274
275 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
276 int set_noreorder;
277 int set_noat;
278 int set_nomacro;
279 int set_volatile;
280
281 /* The next branch instruction is a branch likely, not branch normal. */
282 int mips_branch_likely;
283
284 /* Count of delay slots and how many are filled. */
285 int dslots_load_total;
286 int dslots_load_filled;
287 int dslots_jump_total;
288 int dslots_jump_filled;
289
290 /* # of nops needed by previous insn */
291 int dslots_number_nops;
292
293 /* Number of 1/2/3 word references to data items (ie, not jal's). */
294 int num_refs[3];
295
296 /* registers to check for load delay */
297 rtx mips_load_reg, mips_load_reg2, mips_load_reg3, mips_load_reg4;
298
299 /* Cached operands, and operator to compare for use in set/branch/trap
300 on condition codes. */
301 rtx branch_cmp[2];
302
303 /* what type of branch to use */
304 enum cmp_type branch_type;
305
306 /* The target cpu for code generation. */
307 enum processor_type mips_arch;
308 const struct mips_cpu_info *mips_arch_info;
309
310 /* The target cpu for optimization and scheduling. */
311 enum processor_type mips_tune;
312 const struct mips_cpu_info *mips_tune_info;
313
314 /* which instruction set architecture to use. */
315 int mips_isa;
316
317 /* which abi to use. */
318 int mips_abi;
319
320 /* Strings to hold which cpu and instruction set architecture to use. */
321 const char *mips_arch_string; /* for -march=<xxx> */
322 const char *mips_tune_string; /* for -mtune=<xxx> */
323 const char *mips_isa_string; /* for -mips{1,2,3,4} */
324 const char *mips_abi_string; /* for -mabi={32,n32,64,eabi} */
325
326 /* Whether we are generating mips16 code. This is a synonym for
327 TARGET_MIPS16, and exists for use as an attribute. */
328 int mips16;
329
330 /* This variable is set by -mno-mips16. We only care whether
331 -mno-mips16 appears or not, and using a string in this fashion is
332 just a way to avoid using up another bit in target_flags. */
333 const char *mips_no_mips16_string;
334
335 /* Whether we are generating mips16 hard float code. In mips16 mode
336 we always set TARGET_SOFT_FLOAT; this variable is nonzero if
337 -msoft-float was not specified by the user, which means that we
338 should arrange to call mips32 hard floating point code. */
339 int mips16_hard_float;
340
341 /* This variable is set by -mentry. We only care whether -mentry
342 appears or not, and using a string in this fashion is just a way to
343 avoid using up another bit in target_flags. */
344 const char *mips_entry_string;
345
346 const char *mips_cache_flush_func = CACHE_FLUSH_FUNC;
347
348 /* Whether we should entry and exit pseudo-ops in mips16 mode. */
349 int mips_entry;
350
351 /* If TRUE, we split addresses into their high and low parts in the RTL. */
352 int mips_split_addresses;
353
354 /* Generating calls to position independent functions? */
355 enum mips_abicalls_type mips_abicalls;
356
357 /* Mode used for saving/restoring general purpose registers. */
358 static enum machine_mode gpr_mode;
359
360 /* Array giving truth value on whether or not a given hard register
361 can support a given mode. */
362 char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
363
364 /* The length of all strings seen when compiling for the mips16. This
365 is used to tell how many strings are in the constant pool, so that
366 we can see if we may have an overflow. This is reset each time the
367 constant pool is output. */
368 int mips_string_length;
369
370 /* When generating mips16 code, a list of all strings that are to be
371 output after the current function. */
372
373 static GTY(()) rtx mips16_strings;
374
375 /* In mips16 mode, we build a list of all the string constants we see
376 in a particular function. */
377
378 struct string_constant
379 {
380 struct string_constant *next;
381 const char *label;
382 };
383
384 static struct string_constant *string_constants;
385
386 /* List of all MIPS punctuation characters used by print_operand. */
387 char mips_print_operand_punct[256];
388
389 /* Map GCC register number to debugger register number. */
390 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
391
392 /* Buffer to use to enclose a load/store operation with %{ %} to
393 turn on .set volatile. */
394 static char volatile_buffer[60];
395
396 /* Hardware names for the registers. If -mrnames is used, this
397 will be overwritten with mips_sw_reg_names. */
398
399 char mips_reg_names[][8] =
400 {
401 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
402 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
403 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
404 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31",
405 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
406 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
407 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
408 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
409 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
410 "$fcc5","$fcc6","$fcc7","$rap", "", "", "", "",
411 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",
412 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",
413 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23",
414 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31",
415 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7",
416 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15",
417 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23",
418 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31",
419 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7",
420 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15",
421 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23",
422 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31"
423 };
424
425 /* Mips software names for the registers, used to overwrite the
426 mips_reg_names array. */
427
428 char mips_sw_reg_names[][8] =
429 {
430 "$zero","$at", "$v0", "$v1", "$a0", "$a1", "$a2", "$a3",
431 "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7",
432 "$s0", "$s1", "$s2", "$s3", "$s4", "$s5", "$s6", "$s7",
433 "$t8", "$t9", "$k0", "$k1", "$gp", "$sp", "$fp", "$ra",
434 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
435 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
436 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
437 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
438 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
439 "$fcc5","$fcc6","$fcc7","$rap", "", "", "", "",
440 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",
441 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",
442 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23",
443 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31",
444 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7",
445 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15",
446 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23",
447 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31",
448 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7",
449 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15",
450 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23",
451 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31"
452 };
453
454 /* Map hard register number to register class */
455 const enum reg_class mips_regno_to_class[] =
456 {
457 GR_REGS, GR_REGS, M16_NA_REGS, M16_NA_REGS,
458 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
459 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
460 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
461 M16_NA_REGS, M16_NA_REGS, GR_REGS, GR_REGS,
462 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
463 T_REG, GR_REGS, GR_REGS, GR_REGS,
464 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
465 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
466 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
467 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
468 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
469 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
470 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
471 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
472 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
473 HI_REG, LO_REG, HILO_REG, ST_REGS,
474 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
475 ST_REGS, ST_REGS, ST_REGS, GR_REGS,
476 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
477 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
478 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
479 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
480 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
481 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
482 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
483 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
484 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
485 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
486 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
487 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
488 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
489 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
490 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
491 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
492 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
493 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
494 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
495 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
496 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
497 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
498 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
499 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
500 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS
501 };
502
503 /* Map register constraint character to register class. */
504 enum reg_class mips_char_to_class[256] =
505 {
506 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
507 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
508 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
509 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
510 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
511 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
512 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
513 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
514 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
515 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
516 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
517 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
518 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
519 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
520 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
521 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
522 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
523 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
524 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
525 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
526 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
527 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
528 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
529 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
530 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
531 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
532 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
533 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
534 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
535 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
536 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
537 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
538 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
539 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
540 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
541 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
542 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
543 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
544 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
545 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
546 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
547 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
548 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
549 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
550 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
551 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
552 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
553 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
554 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
555 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
556 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
557 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
558 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
559 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
560 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
561 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
562 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
563 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
564 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
565 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
566 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
567 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
568 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
569 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
570 };
571
572 /* A table describing all the processors gcc knows about. Names are
573 matched in the order listed. The first mention of an ISA level is
574 taken as the canonical name for that ISA.
575
576 To ease comparison, please keep this table in the same order as
577 gas's mips_cpu_info_table[]. */
578 const struct mips_cpu_info mips_cpu_info_table[] = {
579 /* Entries for generic ISAs */
580 { "mips1", PROCESSOR_R3000, 1 },
581 { "mips2", PROCESSOR_R6000, 2 },
582 { "mips3", PROCESSOR_R4000, 3 },
583 { "mips4", PROCESSOR_R8000, 4 },
584 { "mips32", PROCESSOR_R4KC, 32 },
585 { "mips64", PROCESSOR_R5KC, 64 },
586
587 /* MIPS I */
588 { "r3000", PROCESSOR_R3000, 1 },
589 { "r2000", PROCESSOR_R3000, 1 }, /* = r3000 */
590 { "r3900", PROCESSOR_R3900, 1 },
591
592 /* MIPS II */
593 { "r6000", PROCESSOR_R6000, 2 },
594
595 /* MIPS III */
596 { "r4000", PROCESSOR_R4000, 3 },
597 { "vr4100", PROCESSOR_R4100, 3 },
598 { "vr4111", PROCESSOR_R4111, 3 },
599 { "vr4120", PROCESSOR_R4120, 3 },
600 { "vr4300", PROCESSOR_R4300, 3 },
601 { "r4400", PROCESSOR_R4000, 3 }, /* = r4000 */
602 { "r4600", PROCESSOR_R4600, 3 },
603 { "orion", PROCESSOR_R4600, 3 }, /* = r4600 */
604 { "r4650", PROCESSOR_R4650, 3 },
605
606 /* MIPS IV */
607 { "r8000", PROCESSOR_R8000, 4 },
608 { "vr5000", PROCESSOR_R5000, 4 },
609 { "vr5400", PROCESSOR_R5400, 4 },
610 { "vr5500", PROCESSOR_R5500, 4 },
611
612
613 /* MIPS 32 */
614 { "4kc", PROCESSOR_R4KC, 32 },
615 { "4kp", PROCESSOR_R4KC, 32 }, /* = 4kc */
616
617 /* MIPS 64 */
618 { "5kc", PROCESSOR_R5KC, 64 },
619 { "20kc", PROCESSOR_R20KC, 64 },
620 { "sr71000", PROCESSOR_SR71000, 64 },
621
622 /* Broadcom SB-1 CPU core */
623 { "sb1", PROCESSOR_SB1, 64 },
624
625 /* End marker */
626 { 0, 0, 0 }
627 };
628
629 /* Nonzero if -march should decide the default value of MASK_SOFT_FLOAT. */
630 #ifndef MIPS_MARCH_CONTROLS_SOFT_FLOAT
631 #define MIPS_MARCH_CONTROLS_SOFT_FLOAT 0
632 #endif
633
634 /* Initialize the GCC target structure. */
635 #undef TARGET_ASM_ALIGNED_HI_OP
636 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
637 #undef TARGET_ASM_ALIGNED_SI_OP
638 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
639 #undef TARGET_ASM_INTEGER
640 #define TARGET_ASM_INTEGER mips_assemble_integer
641
642 #if TARGET_IRIX5 && !TARGET_IRIX6
643 #undef TARGET_ASM_UNALIGNED_HI_OP
644 #define TARGET_ASM_UNALIGNED_HI_OP "\t.align 0\n\t.half\t"
645 #undef TARGET_ASM_UNALIGNED_SI_OP
646 #define TARGET_ASM_UNALIGNED_SI_OP "\t.align 0\n\t.word\t"
647 /* The IRIX 6 O32 assembler gives an error for `align 0; .dword', contrary
648 to the documentation, so disable it. */
649 #undef TARGET_ASM_UNALIGNED_DI_OP
650 #define TARGET_ASM_UNALIGNED_DI_OP NULL
651 #endif
652
653 #undef TARGET_ASM_FUNCTION_PROLOGUE
654 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
655 #undef TARGET_ASM_FUNCTION_EPILOGUE
656 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
657 #undef TARGET_ASM_SELECT_RTX_SECTION
658 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
659
660 #undef TARGET_SCHED_ADJUST_COST
661 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
662 #undef TARGET_SCHED_ISSUE_RATE
663 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
664 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
665 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE mips_use_dfa_pipeline_interface
666
667 #undef TARGET_ENCODE_SECTION_INFO
668 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
669
670 struct gcc_target targetm = TARGET_INITIALIZER;
671
672 /* Return truth value of whether OP can be used as an operands
673 where a register or 16 bit unsigned integer is needed. */
674
675 int
uns_arith_operand(op,mode)676 uns_arith_operand (op, mode)
677 rtx op;
678 enum machine_mode mode;
679 {
680 if (GET_CODE (op) == CONST_INT && SMALL_INT_UNSIGNED (op))
681 return 1;
682
683 return register_operand (op, mode);
684 }
685
686 /* Return truth value of whether OP can be used as an operands
687 where a 16 bit integer is needed */
688
689 int
arith_operand(op,mode)690 arith_operand (op, mode)
691 rtx op;
692 enum machine_mode mode;
693 {
694 if (GET_CODE (op) == CONST_INT && SMALL_INT (op))
695 return 1;
696
697 /* On the mips16, a GP relative value is a signed 16 bit offset. */
698 if (TARGET_MIPS16 && GET_CODE (op) == CONST && mips16_gp_offset_p (op))
699 return 1;
700
701 return register_operand (op, mode);
702 }
703
704 /* Return truth value of whether OP can be used as an operand in a two
705 address arithmetic insn (such as set 123456,%o4) of mode MODE. */
706
707 int
arith32_operand(op,mode)708 arith32_operand (op, mode)
709 rtx op;
710 enum machine_mode mode;
711 {
712 if (GET_CODE (op) == CONST_INT)
713 return 1;
714
715 return register_operand (op, mode);
716 }
717
718 /* Return truth value of whether OP is an integer which fits in 16 bits. */
719
720 int
small_int(op,mode)721 small_int (op, mode)
722 rtx op;
723 enum machine_mode mode ATTRIBUTE_UNUSED;
724 {
725 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
726 }
727
728 /* Return truth value of whether OP is a 32 bit integer which is too big to
729 be loaded with one instruction. */
730
731 int
large_int(op,mode)732 large_int (op, mode)
733 rtx op;
734 enum machine_mode mode ATTRIBUTE_UNUSED;
735 {
736 HOST_WIDE_INT value;
737
738 if (GET_CODE (op) != CONST_INT)
739 return 0;
740
741 value = INTVAL (op);
742
743 /* ior reg,$r0,value */
744 if ((value & ~ ((HOST_WIDE_INT) 0x0000ffff)) == 0)
745 return 0;
746
747 /* subu reg,$r0,value */
748 if (((unsigned HOST_WIDE_INT) (value + 32768)) <= 32767)
749 return 0;
750
751 /* lui reg,value>>16 */
752 if ((value & 0x0000ffff) == 0)
753 return 0;
754
755 return 1;
756 }
757
758 /* Return truth value of whether OP is a register or the constant 0.
759 In mips16 mode, we only accept a register, since the mips16 does
760 not have $0. */
761
762 int
reg_or_0_operand(op,mode)763 reg_or_0_operand (op, mode)
764 rtx op;
765 enum machine_mode mode;
766 {
767 switch (GET_CODE (op))
768 {
769 case CONST_INT:
770 if (TARGET_MIPS16)
771 return 0;
772 return INTVAL (op) == 0;
773
774 case CONST_DOUBLE:
775 if (TARGET_MIPS16)
776 return 0;
777 return op == CONST0_RTX (mode);
778
779 case REG:
780 case SUBREG:
781 return register_operand (op, mode);
782
783 default:
784 break;
785 }
786
787 return 0;
788 }
789
790 /* Return truth value of whether OP is a register or the constant 0,
791 even in mips16 mode. */
792
793 int
true_reg_or_0_operand(op,mode)794 true_reg_or_0_operand (op, mode)
795 rtx op;
796 enum machine_mode mode;
797 {
798 switch (GET_CODE (op))
799 {
800 case CONST_INT:
801 return INTVAL (op) == 0;
802
803 case CONST_DOUBLE:
804 return op == CONST0_RTX (mode);
805
806 case REG:
807 case SUBREG:
808 return register_operand (op, mode);
809
810 default:
811 break;
812 }
813
814 return 0;
815 }
816
817 /* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant. */
818
819 int
mips_const_double_ok(op,mode)820 mips_const_double_ok (op, mode)
821 rtx op;
822 enum machine_mode mode;
823 {
824 if (GET_CODE (op) != CONST_DOUBLE)
825 return 0;
826
827 if (mode == VOIDmode)
828 return 1;
829
830 /* We've no zero register in mips16 mode. */
831 if (TARGET_MIPS16)
832 return 0;
833
834 if (mode != SFmode && mode != DFmode)
835 return 0;
836
837 if (op == CONST0_RTX (mode))
838 return 1;
839
840 return 0;
841 }
842
843 /* Accept the floating point constant 1 in the appropriate mode. */
844
845 int
const_float_1_operand(op,mode)846 const_float_1_operand (op, mode)
847 rtx op;
848 enum machine_mode mode;
849 {
850 REAL_VALUE_TYPE d;
851
852 if (GET_CODE (op) != CONST_DOUBLE
853 || mode != GET_MODE (op)
854 || (mode != DFmode && mode != SFmode))
855 return 0;
856
857 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
858
859 return REAL_VALUES_EQUAL (d, dconst1);
860 }
861
862 /* Return true if a memory load or store of REG plus OFFSET in MODE
863 can be represented in a single word on the mips16. */
864
865 static int
mips16_simple_memory_operand(reg,offset,mode)866 mips16_simple_memory_operand (reg, offset, mode)
867 rtx reg;
868 rtx offset;
869 enum machine_mode mode;
870 {
871 unsigned int size;
872 int off;
873
874 if (mode == BLKmode)
875 {
876 /* We can't tell, because we don't know how the value will
877 eventually be accessed. Returning 0 here does no great
878 harm; it just prevents some possible instruction scheduling. */
879 return 0;
880 }
881
882 size = GET_MODE_SIZE (mode);
883
884 if (INTVAL (offset) % size != 0)
885 return 0;
886 if (REGNO (reg) == STACK_POINTER_REGNUM && GET_MODE_SIZE (mode) == 4)
887 off = 0x100;
888 else
889 off = 0x20;
890 if (INTVAL (offset) >= 0 && INTVAL (offset) < (HOST_WIDE_INT)(off * size))
891 return 1;
892 return 0;
893 }
894
895 /* Return truth value if a memory operand fits in a single instruction
896 (ie, register + small offset). */
897
898 int
simple_memory_operand(op,mode)899 simple_memory_operand (op, mode)
900 rtx op;
901 enum machine_mode mode;
902 {
903 rtx addr, plus0, plus1;
904
905 /* Eliminate non-memory operations */
906 if (GET_CODE (op) != MEM)
907 return 0;
908
909 /* dword operations really put out 2 instructions, so eliminate them. */
910 /* ??? This isn't strictly correct. It is OK to accept multiword modes
911 here, since the length attributes are being set correctly, but only
912 if the address is offsettable. LO_SUM is not offsettable. */
913 if (GET_MODE_SIZE (GET_MODE (op)) > (unsigned) UNITS_PER_WORD)
914 return 0;
915
916 /* Decode the address now. */
917 addr = XEXP (op, 0);
918 switch (GET_CODE (addr))
919 {
920 case REG:
921 case LO_SUM:
922 return 1;
923
924 case CONST_INT:
925 if (TARGET_MIPS16)
926 return 0;
927 return SMALL_INT (addr);
928
929 case PLUS:
930 plus0 = XEXP (addr, 0);
931 plus1 = XEXP (addr, 1);
932 if (GET_CODE (plus0) == REG
933 && GET_CODE (plus1) == CONST_INT && SMALL_INT (plus1)
934 && (! TARGET_MIPS16
935 || mips16_simple_memory_operand (plus0, plus1, mode)))
936 return 1;
937
938 else if (GET_CODE (plus1) == REG
939 && GET_CODE (plus0) == CONST_INT && SMALL_INT (plus0)
940 && (! TARGET_MIPS16
941 || mips16_simple_memory_operand (plus1, plus0, mode)))
942 return 1;
943
944 else
945 return 0;
946
947 #if 0
948 /* We used to allow small symbol refs here (ie, stuff in .sdata
949 or .sbss), but this causes some bugs in G++. Also, it won't
950 interfere if the MIPS linker rewrites the store instruction
951 because the function is PIC. */
952
953 case LABEL_REF: /* never gp relative */
954 break;
955
956 case CONST:
957 /* If -G 0, we can never have a GP relative memory operation.
958 Also, save some time if not optimizing. */
959 if (!TARGET_GP_OPT)
960 return 0;
961
962 {
963 rtx offset = const0_rtx;
964 addr = eliminate_constant_term (XEXP (addr, 0), &offset);
965 if (GET_CODE (op) != SYMBOL_REF)
966 return 0;
967
968 /* let's be paranoid.... */
969 if (! SMALL_INT (offset))
970 return 0;
971 }
972
973 /* fall through */
974
975 case SYMBOL_REF:
976 return SYMBOL_REF_FLAG (addr);
977 #endif
978
979 /* This SYMBOL_REF case is for the mips16. If the above case is
980 reenabled, this one should be merged in. */
981 case SYMBOL_REF:
982 /* References to the constant pool on the mips16 use a small
983 offset if the function is small. The only time we care about
984 getting this right is during delayed branch scheduling, so
985 don't need to check until then. The machine_dependent_reorg
986 function will set the total length of the instructions used
987 in the function (cfun->machine->insns_len). If that is small
988 enough, we know for sure that this is a small offset. It
989 would be better if we could take into account the location of
990 the instruction within the function, but we can't, because we
991 don't know where we are. */
992 if (TARGET_MIPS16
993 && CONSTANT_POOL_ADDRESS_P (addr)
994 && cfun->machine->insns_len > 0)
995 {
996 long size;
997
998 size = cfun->machine->insns_len + get_pool_size ();
999 if (GET_MODE_SIZE (mode) == 4)
1000 return size < 4 * 0x100;
1001 else if (GET_MODE_SIZE (mode) == 8)
1002 return size < 8 * 0x20;
1003 else
1004 return 0;
1005 }
1006
1007 return 0;
1008
1009 default:
1010 break;
1011 }
1012
1013 return 0;
1014 }
1015
1016 /* Return nonzero for a memory address that can be used to load or store
1017 a doubleword. */
1018
1019 int
double_memory_operand(op,mode)1020 double_memory_operand (op, mode)
1021 rtx op;
1022 enum machine_mode mode;
1023 {
1024 if (GET_CODE (op) != MEM
1025 || ! memory_operand (op, mode))
1026 {
1027 /* During reload, we accept a pseudo register if it has an
1028 appropriate memory address. If we don't do this, we will
1029 wind up reloading into a register, and then reloading that
1030 register from memory, when we could just reload directly from
1031 memory. */
1032 if (reload_in_progress
1033 && GET_CODE (op) == REG
1034 && REGNO (op) >= FIRST_PSEUDO_REGISTER
1035 && reg_renumber[REGNO (op)] < 0
1036 && reg_equiv_mem[REGNO (op)] != 0
1037 && double_memory_operand (reg_equiv_mem[REGNO (op)], mode))
1038 return 1;
1039
1040 /* All reloaded addresses are valid in TARGET_64BIT mode. This is
1041 the same test performed for 'm' in find_reloads. */
1042
1043 if (reload_in_progress
1044 && TARGET_64BIT
1045 && (GET_CODE (op) == MEM
1046 || (GET_CODE (op) == REG
1047 && REGNO (op) >= FIRST_PSEUDO_REGISTER
1048 && reg_renumber[REGNO (op)] < 0)))
1049 return 1;
1050
1051 if (reload_in_progress
1052 && TARGET_MIPS16
1053 && GET_CODE (op) == MEM)
1054 {
1055 rtx addr;
1056
1057 addr = XEXP (op, 0);
1058
1059 /* During reload on the mips16, we accept a large offset
1060 from the frame pointer or the stack pointer. This large
1061 address will get reloaded anyhow. */
1062 if (GET_CODE (addr) == PLUS
1063 && GET_CODE (XEXP (addr, 0)) == REG
1064 && (REGNO (XEXP (addr, 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
1065 || REGNO (XEXP (addr, 0)) == STACK_POINTER_REGNUM)
1066 && ((GET_CODE (XEXP (addr, 1)) == CONST_INT
1067 && ! SMALL_INT (XEXP (addr, 1)))
1068 || (GET_CODE (XEXP (addr, 1)) == SYMBOL_REF
1069 && CONSTANT_POOL_ADDRESS_P (XEXP (addr, 1)))))
1070 return 1;
1071
1072 /* Similarly, we accept a case where the memory address is
1073 itself on the stack, and will be reloaded. */
1074 if (GET_CODE (addr) == MEM)
1075 {
1076 rtx maddr;
1077
1078 maddr = XEXP (addr, 0);
1079 if (GET_CODE (maddr) == PLUS
1080 && GET_CODE (XEXP (maddr, 0)) == REG
1081 && (REGNO (XEXP (maddr, 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
1082 || REGNO (XEXP (maddr, 0)) == STACK_POINTER_REGNUM)
1083 && ((GET_CODE (XEXP (maddr, 1)) == CONST_INT
1084 && ! SMALL_INT (XEXP (maddr, 1)))
1085 || (GET_CODE (XEXP (maddr, 1)) == SYMBOL_REF
1086 && CONSTANT_POOL_ADDRESS_P (XEXP (maddr, 1)))))
1087 return 1;
1088 }
1089
1090 /* We also accept the same case when we have a 16 bit signed
1091 offset mixed in as well. The large address will get
1092 reloaded, and the 16 bit offset will be OK. */
1093 if (GET_CODE (addr) == PLUS
1094 && GET_CODE (XEXP (addr, 0)) == MEM
1095 && GET_CODE (XEXP (addr, 1)) == CONST_INT
1096 && SMALL_INT (XEXP (addr, 1)))
1097 {
1098 addr = XEXP (XEXP (addr, 0), 0);
1099 if (GET_CODE (addr) == PLUS
1100 && GET_CODE (XEXP (addr, 0)) == REG
1101 && (REGNO (XEXP (addr, 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
1102 || REGNO (XEXP (addr, 0)) == STACK_POINTER_REGNUM)
1103 && ((GET_CODE (XEXP (addr, 1)) == CONST_INT
1104 && ! SMALL_INT (XEXP (addr, 1)))
1105 || (GET_CODE (XEXP (addr, 1)) == SYMBOL_REF
1106 && CONSTANT_POOL_ADDRESS_P (XEXP (addr, 1)))))
1107 return 1;
1108 }
1109 }
1110
1111 return 0;
1112 }
1113
1114 if (TARGET_64BIT)
1115 {
1116 /* In this case we can use an instruction like sd. */
1117 return 1;
1118 }
1119
1120 /* Make sure that 4 added to the address is a valid memory address.
1121 This essentially just checks for overflow in an added constant. */
1122
1123 if (CONSTANT_ADDRESS_P (XEXP (op, 0)))
1124 return 1;
1125
1126 op = adjust_address_nv (op, GET_MODE_CLASS (mode) == MODE_INT
1127 ? SImode : SFmode, 4);
1128 return memory_address_p (GET_MODE (op), XEXP (op, 0));
1129 }
1130
1131 /* Return nonzero if the code of this rtx pattern is EQ or NE. */
1132
1133 int
equality_op(op,mode)1134 equality_op (op, mode)
1135 rtx op;
1136 enum machine_mode mode;
1137 {
1138 if (mode != GET_MODE (op))
1139 return 0;
1140
1141 return GET_CODE (op) == EQ || GET_CODE (op) == NE;
1142 }
1143
1144 /* Return nonzero if the code is a relational operations (EQ, LE, etc.) */
1145
1146 int
cmp_op(op,mode)1147 cmp_op (op, mode)
1148 rtx op;
1149 enum machine_mode mode;
1150 {
1151 if (mode != GET_MODE (op))
1152 return 0;
1153
1154 return GET_RTX_CLASS (GET_CODE (op)) == '<';
1155 }
1156
1157 /* Return nonzero if the code is a relational operation suitable for a
1158 conditional trap instructuion (only EQ, NE, LT, LTU, GE, GEU).
1159 We need this in the insn that expands `trap_if' in order to prevent
1160 combine from erroneously altering the condition. */
1161
1162 int
trap_cmp_op(op,mode)1163 trap_cmp_op (op, mode)
1164 rtx op;
1165 enum machine_mode mode;
1166 {
1167 if (mode != GET_MODE (op))
1168 return 0;
1169
1170 switch (GET_CODE (op))
1171 {
1172 case EQ:
1173 case NE:
1174 case LT:
1175 case LTU:
1176 case GE:
1177 case GEU:
1178 return 1;
1179
1180 default:
1181 return 0;
1182 }
1183 }
1184
1185 /* Return nonzero if the operand is either the PC or a label_ref. */
1186
1187 int
pc_or_label_operand(op,mode)1188 pc_or_label_operand (op, mode)
1189 rtx op;
1190 enum machine_mode mode ATTRIBUTE_UNUSED;
1191 {
1192 if (op == pc_rtx)
1193 return 1;
1194
1195 if (GET_CODE (op) == LABEL_REF)
1196 return 1;
1197
1198 return 0;
1199 }
1200
1201 /* Test for a valid operand for a call instruction.
1202 Don't allow the arg pointer register or virtual regs
1203 since they may change into reg + const, which the patterns
1204 can't handle yet. */
1205
1206 int
call_insn_operand(op,mode)1207 call_insn_operand (op, mode)
1208 rtx op;
1209 enum machine_mode mode ATTRIBUTE_UNUSED;
1210 {
1211 return (CONSTANT_ADDRESS_P (op)
1212 || (GET_CODE (op) == REG && op != arg_pointer_rtx
1213 && ! (REGNO (op) >= FIRST_PSEUDO_REGISTER
1214 && REGNO (op) <= LAST_VIRTUAL_REGISTER)));
1215 }
1216
1217 /* Return nonzero if OPERAND is valid as a source operand for a move
1218 instruction. */
1219
1220 int
move_operand(op,mode)1221 move_operand (op, mode)
1222 rtx op;
1223 enum machine_mode mode;
1224 {
1225 /* Accept any general operand after reload has started; doing so
1226 avoids losing if reload does an in-place replacement of a register
1227 with a SYMBOL_REF or CONST. */
1228 return (general_operand (op, mode)
1229 && (! (mips_split_addresses && mips_check_split (op, mode))
1230 || reload_in_progress || reload_completed)
1231 && ! (TARGET_MIPS16
1232 && GET_CODE (op) == SYMBOL_REF
1233 && ! mips16_constant (op, mode, 1, 0)));
1234 }
1235
1236 /* Return nonzero if OPERAND is valid as a source operand for movdi.
1237 This accepts not only general_operand, but also sign extended
1238 move_operands. Note that we need to accept sign extended constants
1239 in case a sign extended register which is used in an expression,
1240 and is equivalent to a constant, is spilled. We need to accept
1241 sign-extended memory in order to reload registers from stack slots,
1242 and so that we generate efficient code for extendsidi2. */
1243
1244 int
movdi_operand(op,mode)1245 movdi_operand (op, mode)
1246 rtx op;
1247 enum machine_mode mode;
1248 {
1249 if (TARGET_64BIT
1250 && mode == DImode
1251 && GET_CODE (op) == SIGN_EXTEND
1252 && GET_MODE (op) == DImode
1253 && move_operand (XEXP (op, 0), SImode))
1254 return 1;
1255
1256 return (general_operand (op, mode)
1257 && ! (TARGET_MIPS16
1258 && GET_CODE (op) == SYMBOL_REF
1259 && ! mips16_constant (op, mode, 1, 0)));
1260 }
1261
1262 /* Like register_operand, but when in 64 bit mode also accept a sign
1263 extend of a 32 bit register, since the value is known to be already
1264 sign extended. */
1265
1266 int
se_register_operand(op,mode)1267 se_register_operand (op, mode)
1268 rtx op;
1269 enum machine_mode mode;
1270 {
1271 if (TARGET_64BIT
1272 && mode == DImode
1273 && GET_CODE (op) == SIGN_EXTEND
1274 && GET_MODE (op) == DImode
1275 && GET_MODE (XEXP (op, 0)) == SImode
1276 && register_operand (XEXP (op, 0), SImode))
1277 return 1;
1278
1279 return register_operand (op, mode);
1280 }
1281
1282 /* Like reg_or_0_operand, but when in 64 bit mode also accept a sign
1283 extend of a 32 bit register, since the value is known to be already
1284 sign extended. */
1285
1286 int
se_reg_or_0_operand(op,mode)1287 se_reg_or_0_operand (op, mode)
1288 rtx op;
1289 enum machine_mode mode;
1290 {
1291 if (TARGET_64BIT
1292 && mode == DImode
1293 && GET_CODE (op) == SIGN_EXTEND
1294 && GET_MODE (op) == DImode
1295 && GET_MODE (XEXP (op, 0)) == SImode
1296 && register_operand (XEXP (op, 0), SImode))
1297 return 1;
1298
1299 return reg_or_0_operand (op, mode);
1300 }
1301
1302 /* Like uns_arith_operand, but when in 64 bit mode also accept a sign
1303 extend of a 32 bit register, since the value is known to be already
1304 sign extended. */
1305
1306 int
se_uns_arith_operand(op,mode)1307 se_uns_arith_operand (op, mode)
1308 rtx op;
1309 enum machine_mode mode;
1310 {
1311 if (TARGET_64BIT
1312 && mode == DImode
1313 && GET_CODE (op) == SIGN_EXTEND
1314 && GET_MODE (op) == DImode
1315 && GET_MODE (XEXP (op, 0)) == SImode
1316 && register_operand (XEXP (op, 0), SImode))
1317 return 1;
1318
1319 return uns_arith_operand (op, mode);
1320 }
1321
1322 /* Like arith_operand, but when in 64 bit mode also accept a sign
1323 extend of a 32 bit register, since the value is known to be already
1324 sign extended. */
1325
1326 int
se_arith_operand(op,mode)1327 se_arith_operand (op, mode)
1328 rtx op;
1329 enum machine_mode mode;
1330 {
1331 if (TARGET_64BIT
1332 && mode == DImode
1333 && GET_CODE (op) == SIGN_EXTEND
1334 && GET_MODE (op) == DImode
1335 && GET_MODE (XEXP (op, 0)) == SImode
1336 && register_operand (XEXP (op, 0), SImode))
1337 return 1;
1338
1339 return arith_operand (op, mode);
1340 }
1341
1342 /* Like nonmemory_operand, but when in 64 bit mode also accept a sign
1343 extend of a 32 bit register, since the value is known to be already
1344 sign extended. */
1345
1346 int
se_nonmemory_operand(op,mode)1347 se_nonmemory_operand (op, mode)
1348 rtx op;
1349 enum machine_mode mode;
1350 {
1351 if (TARGET_64BIT
1352 && mode == DImode
1353 && GET_CODE (op) == SIGN_EXTEND
1354 && GET_MODE (op) == DImode
1355 && GET_MODE (XEXP (op, 0)) == SImode
1356 && register_operand (XEXP (op, 0), SImode))
1357 return 1;
1358
1359 return nonmemory_operand (op, mode);
1360 }
1361
1362 /* Accept any operand that can appear in a mips16 constant table
1363 instruction. We can't use any of the standard operand functions
1364 because for these instructions we accept values that are not
1365 accepted by LEGITIMATE_CONSTANT, such as arbitrary SYMBOL_REFs. */
1366
1367 int
consttable_operand(op,mode)1368 consttable_operand (op, mode)
1369 rtx op;
1370 enum machine_mode mode ATTRIBUTE_UNUSED;
1371 {
1372 return CONSTANT_P (op);
1373 }
1374
1375 /* Coprocessor operand; return true if rtx is a REG and refers to a
1376 coprocessor. */
1377
1378 int
coprocessor_operand(op,mode)1379 coprocessor_operand (op, mode)
1380 rtx op;
1381 enum machine_mode mode ATTRIBUTE_UNUSED;
1382 {
1383 return (GET_CODE (op) == REG
1384 && COP0_REG_FIRST <= REGNO (op)
1385 && REGNO (op) <= COP3_REG_LAST);
1386 }
1387
1388 int
coprocessor2_operand(op,mode)1389 coprocessor2_operand (op, mode)
1390 rtx op;
1391 enum machine_mode mode ATTRIBUTE_UNUSED;
1392 {
1393 return (GET_CODE (op) == REG
1394 && COP2_REG_FIRST <= REGNO (op)
1395 && REGNO (op) <= COP2_REG_LAST);
1396 }
1397
1398 /* Returns 1 if OP is a symbolic operand, i.e. a symbol_ref or a label_ref,
1399 possibly with an offset. */
1400
1401 int
symbolic_operand(op,mode)1402 symbolic_operand (op, mode)
1403 register rtx op;
1404 enum machine_mode mode;
1405 {
1406 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
1407 return 0;
1408 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
1409 return 1;
1410 if (GET_CODE (op) == CONST
1411 && GET_CODE (XEXP (op,0)) == PLUS
1412 && GET_CODE (XEXP (XEXP (op,0), 0)) == SYMBOL_REF
1413 && GET_CODE (XEXP (XEXP (op,0), 1)) == CONST_INT)
1414 return 1;
1415 return 0;
1416 }
1417
1418 /* Return nonzero if we split the address into high and low parts. */
1419
1420 /* ??? We should also handle reg+array somewhere. We get four
1421 instructions currently, lui %hi/addui %lo/addui reg/lw. Better is
1422 lui %hi/addui reg/lw %lo. Fixing GO_IF_LEGITIMATE_ADDRESS to accept
1423 (plus (reg) (symbol_ref)) doesn't work because the SYMBOL_REF is broken
1424 out of the address, then we have 4 instructions to combine. Perhaps
1425 add a 3->2 define_split for combine. */
1426
1427 /* ??? We could also split a CONST_INT here if it is a large_int().
1428 However, it doesn't seem to be very useful to have %hi(constant).
1429 We would be better off by doing the masking ourselves and then putting
1430 the explicit high part of the constant in the RTL. This will give better
1431 optimization. Also, %hi(constant) needs assembler changes to work.
1432 There is already a define_split that does this. */
1433
1434 int
mips_check_split(address,mode)1435 mips_check_split (address, mode)
1436 rtx address;
1437 enum machine_mode mode;
1438 {
1439 /* ??? This is the same check used in simple_memory_operand.
1440 We use it here because LO_SUM is not offsettable. */
1441 if (GET_MODE_SIZE (mode) > (unsigned) UNITS_PER_WORD)
1442 return 0;
1443
1444 if ((GET_CODE (address) == SYMBOL_REF && ! SYMBOL_REF_FLAG (address))
1445 || (GET_CODE (address) == CONST
1446 && GET_CODE (XEXP (XEXP (address, 0), 0)) == SYMBOL_REF
1447 && ! SYMBOL_REF_FLAG (XEXP (XEXP (address, 0), 0)))
1448 || GET_CODE (address) == LABEL_REF)
1449 return 1;
1450
1451 return 0;
1452 }
1453
1454 /* This function is used to implement REG_MODE_OK_FOR_BASE_P. */
1455
1456 int
mips_reg_mode_ok_for_base_p(reg,mode,strict)1457 mips_reg_mode_ok_for_base_p (reg, mode, strict)
1458 rtx reg;
1459 enum machine_mode mode;
1460 int strict;
1461 {
1462 return (strict
1463 ? REGNO_MODE_OK_FOR_BASE_P (REGNO (reg), mode)
1464 : GP_REG_OR_PSEUDO_NONSTRICT_P (REGNO (reg), mode));
1465 }
1466
1467 /* This function is used to implement GO_IF_LEGITIMATE_ADDRESS. It
1468 returns a nonzero value if XINSN is a legitimate address for a
1469 memory operand of the indicated MODE. STRICT is nonzero if this
1470 function is called during reload. */
1471
1472 int
mips_legitimate_address_p(mode,xinsn,strict)1473 mips_legitimate_address_p (mode, xinsn, strict)
1474 enum machine_mode mode;
1475 rtx xinsn;
1476 int strict;
1477 {
1478 if (TARGET_DEBUG_B_MODE)
1479 {
1480 GO_PRINTF2 ("\n========== GO_IF_LEGITIMATE_ADDRESS, %sstrict\n",
1481 strict ? "" : "not ");
1482 GO_DEBUG_RTX (xinsn);
1483 }
1484
1485 /* Check for constant before stripping off SUBREG, so that we don't
1486 accept (subreg (const_int)) which will fail to reload. */
1487 if (CONSTANT_ADDRESS_P (xinsn)
1488 && ! (mips_split_addresses && mips_check_split (xinsn, mode))
1489 && (! TARGET_MIPS16 || mips16_constant (xinsn, mode, 1, 0)))
1490 return 1;
1491
1492 while (GET_CODE (xinsn) == SUBREG)
1493 xinsn = SUBREG_REG (xinsn);
1494
1495 /* The mips16 can only use the stack pointer as a base register when
1496 loading SImode or DImode values. */
1497 if (GET_CODE (xinsn) == REG
1498 && mips_reg_mode_ok_for_base_p (xinsn, mode, strict))
1499 return 1;
1500
1501 if (GET_CODE (xinsn) == LO_SUM && mips_split_addresses)
1502 {
1503 register rtx xlow0 = XEXP (xinsn, 0);
1504 register rtx xlow1 = XEXP (xinsn, 1);
1505
1506 while (GET_CODE (xlow0) == SUBREG)
1507 xlow0 = SUBREG_REG (xlow0);
1508 if (GET_CODE (xlow0) == REG
1509 && mips_reg_mode_ok_for_base_p (xlow0, mode, strict)
1510 && mips_check_split (xlow1, mode))
1511 return 1;
1512 }
1513
1514 if (GET_CODE (xinsn) == PLUS)
1515 {
1516 register rtx xplus0 = XEXP (xinsn, 0);
1517 register rtx xplus1 = XEXP (xinsn, 1);
1518 register enum rtx_code code0;
1519 register enum rtx_code code1;
1520
1521 while (GET_CODE (xplus0) == SUBREG)
1522 xplus0 = SUBREG_REG (xplus0);
1523 code0 = GET_CODE (xplus0);
1524
1525 while (GET_CODE (xplus1) == SUBREG)
1526 xplus1 = SUBREG_REG (xplus1);
1527 code1 = GET_CODE (xplus1);
1528
1529 /* The mips16 can only use the stack pointer as a base register
1530 when loading SImode or DImode values. */
1531 if (code0 == REG
1532 && mips_reg_mode_ok_for_base_p (xplus0, mode, strict))
1533 {
1534 if (code1 == CONST_INT && SMALL_INT (xplus1))
1535 return 1;
1536
1537 /* On the mips16, we represent GP relative offsets in RTL.
1538 These are 16 bit signed values, and can serve as register
1539 offsets. */
1540 if (TARGET_MIPS16
1541 && mips16_gp_offset_p (xplus1))
1542 return 1;
1543
1544 /* For some code sequences, you actually get better code by
1545 pretending that the MIPS supports an address mode of a
1546 constant address + a register, even though the real
1547 machine doesn't support it. This is because the
1548 assembler can use $r1 to load just the high 16 bits, add
1549 in the register, and fold the low 16 bits into the memory
1550 reference, whereas the compiler generates a 4 instruction
1551 sequence. On the other hand, CSE is not as effective.
1552 It would be a win to generate the lui directly, but the
1553 MIPS assembler does not have syntax to generate the
1554 appropriate relocation. */
1555
1556 /* Also accept CONST_INT addresses here, so no else. */
1557 /* Reject combining an embedded PIC text segment reference
1558 with a register. That requires an additional
1559 instruction. */
1560 /* ??? Reject combining an address with a register for the MIPS
1561 64 bit ABI, because the SGI assembler can not handle this. */
1562 if (!TARGET_DEBUG_A_MODE
1563 && (mips_abi == ABI_32
1564 || mips_abi == ABI_O64
1565 || mips_abi == ABI_EABI)
1566 && CONSTANT_ADDRESS_P (xplus1)
1567 && ! mips_split_addresses
1568 && (!TARGET_EMBEDDED_PIC
1569 || code1 != CONST
1570 || GET_CODE (XEXP (xplus1, 0)) != MINUS)
1571 /* When assembling for machines with 64 bit registers,
1572 the assembler will sign-extend the constant "foo"
1573 in "la x, foo(x)" yielding the wrong result for:
1574 (set (blah:DI) (plus x y)). */
1575 && (!TARGET_64BIT
1576 || (code1 == CONST_INT
1577 && trunc_int_for_mode (INTVAL (xplus1),
1578 SImode) == INTVAL (xplus1)))
1579 && !TARGET_MIPS16)
1580 return 1;
1581 }
1582 }
1583
1584 if (TARGET_DEBUG_B_MODE)
1585 GO_PRINTF ("Not a legitimate address\n");
1586
1587 /* The address was not legitimate. */
1588 return 0;
1589 }
1590
1591
1592 /* We need a lot of little routines to check constant values on the
1593 mips16. These are used to figure out how long the instruction will
1594 be. It would be much better to do this using constraints, but
1595 there aren't nearly enough letters available. */
1596
1597 static int
m16_check_op(op,low,high,mask)1598 m16_check_op (op, low, high, mask)
1599 rtx op;
1600 int low;
1601 int high;
1602 int mask;
1603 {
1604 return (GET_CODE (op) == CONST_INT
1605 && INTVAL (op) >= low
1606 && INTVAL (op) <= high
1607 && (INTVAL (op) & mask) == 0);
1608 }
1609
1610 int
m16_uimm3_b(op,mode)1611 m16_uimm3_b (op, mode)
1612 rtx op;
1613 enum machine_mode mode ATTRIBUTE_UNUSED;
1614 {
1615 return m16_check_op (op, 0x1, 0x8, 0);
1616 }
1617
1618 int
m16_simm4_1(op,mode)1619 m16_simm4_1 (op, mode)
1620 rtx op;
1621 enum machine_mode mode ATTRIBUTE_UNUSED;
1622 {
1623 return m16_check_op (op, - 0x8, 0x7, 0);
1624 }
1625
1626 int
m16_nsimm4_1(op,mode)1627 m16_nsimm4_1 (op, mode)
1628 rtx op;
1629 enum machine_mode mode ATTRIBUTE_UNUSED;
1630 {
1631 return m16_check_op (op, - 0x7, 0x8, 0);
1632 }
1633
1634 int
m16_simm5_1(op,mode)1635 m16_simm5_1 (op, mode)
1636 rtx op;
1637 enum machine_mode mode ATTRIBUTE_UNUSED;
1638 {
1639 return m16_check_op (op, - 0x10, 0xf, 0);
1640 }
1641
1642 int
m16_nsimm5_1(op,mode)1643 m16_nsimm5_1 (op, mode)
1644 rtx op;
1645 enum machine_mode mode ATTRIBUTE_UNUSED;
1646 {
1647 return m16_check_op (op, - 0xf, 0x10, 0);
1648 }
1649
1650 int
m16_uimm5_4(op,mode)1651 m16_uimm5_4 (op, mode)
1652 rtx op;
1653 enum machine_mode mode ATTRIBUTE_UNUSED;
1654 {
1655 return m16_check_op (op, (- 0x10) << 2, 0xf << 2, 3);
1656 }
1657
1658 int
m16_nuimm5_4(op,mode)1659 m16_nuimm5_4 (op, mode)
1660 rtx op;
1661 enum machine_mode mode ATTRIBUTE_UNUSED;
1662 {
1663 return m16_check_op (op, (- 0xf) << 2, 0x10 << 2, 3);
1664 }
1665
1666 int
m16_simm8_1(op,mode)1667 m16_simm8_1 (op, mode)
1668 rtx op;
1669 enum machine_mode mode ATTRIBUTE_UNUSED;
1670 {
1671 return m16_check_op (op, - 0x80, 0x7f, 0);
1672 }
1673
1674 int
m16_nsimm8_1(op,mode)1675 m16_nsimm8_1 (op, mode)
1676 rtx op;
1677 enum machine_mode mode ATTRIBUTE_UNUSED;
1678 {
1679 return m16_check_op (op, - 0x7f, 0x80, 0);
1680 }
1681
1682 int
m16_uimm8_1(op,mode)1683 m16_uimm8_1 (op, mode)
1684 rtx op;
1685 enum machine_mode mode ATTRIBUTE_UNUSED;
1686 {
1687 return m16_check_op (op, 0x0, 0xff, 0);
1688 }
1689
1690 int
m16_nuimm8_1(op,mode)1691 m16_nuimm8_1 (op, mode)
1692 rtx op;
1693 enum machine_mode mode ATTRIBUTE_UNUSED;
1694 {
1695 return m16_check_op (op, - 0xff, 0x0, 0);
1696 }
1697
1698 int
m16_uimm8_m1_1(op,mode)1699 m16_uimm8_m1_1 (op, mode)
1700 rtx op;
1701 enum machine_mode mode ATTRIBUTE_UNUSED;
1702 {
1703 return m16_check_op (op, - 0x1, 0xfe, 0);
1704 }
1705
1706 int
m16_uimm8_4(op,mode)1707 m16_uimm8_4 (op, mode)
1708 rtx op;
1709 enum machine_mode mode ATTRIBUTE_UNUSED;
1710 {
1711 return m16_check_op (op, 0x0, 0xff << 2, 3);
1712 }
1713
1714 int
m16_nuimm8_4(op,mode)1715 m16_nuimm8_4 (op, mode)
1716 rtx op;
1717 enum machine_mode mode ATTRIBUTE_UNUSED;
1718 {
1719 return m16_check_op (op, (- 0xff) << 2, 0x0, 3);
1720 }
1721
1722 int
m16_simm8_8(op,mode)1723 m16_simm8_8 (op, mode)
1724 rtx op;
1725 enum machine_mode mode ATTRIBUTE_UNUSED;
1726 {
1727 return m16_check_op (op, (- 0x80) << 3, 0x7f << 3, 7);
1728 }
1729
1730 int
m16_nsimm8_8(op,mode)1731 m16_nsimm8_8 (op, mode)
1732 rtx op;
1733 enum machine_mode mode ATTRIBUTE_UNUSED;
1734 {
1735 return m16_check_op (op, (- 0x7f) << 3, 0x80 << 3, 7);
1736 }
1737
1738 /* References to the string table on the mips16 only use a small
1739 offset if the function is small. See the comment in the SYMBOL_REF
1740 case in simple_memory_operand. We can't check for LABEL_REF here,
1741 because the offset is always large if the label is before the
1742 referencing instruction. */
1743
1744 int
m16_usym8_4(op,mode)1745 m16_usym8_4 (op, mode)
1746 rtx op;
1747 enum machine_mode mode ATTRIBUTE_UNUSED;
1748 {
1749 if (GET_CODE (op) == SYMBOL_REF
1750 && SYMBOL_REF_FLAG (op)
1751 && cfun->machine->insns_len > 0
1752 && XSTR (op, 0)[0] == '*'
1753 && strncmp (XSTR (op, 0) + 1, LOCAL_LABEL_PREFIX,
1754 sizeof LOCAL_LABEL_PREFIX - 1) == 0
1755 && (cfun->machine->insns_len + get_pool_size () + mips_string_length
1756 < 4 * 0x100))
1757 {
1758 struct string_constant *l;
1759
1760 /* Make sure this symbol is on thelist of string constants to be
1761 output for this function. It is possible that it has already
1762 been output, in which case this requires a large offset. */
1763 for (l = string_constants; l != NULL; l = l->next)
1764 if (strcmp (l->label, XSTR (op, 0)) == 0)
1765 return 1;
1766 }
1767
1768 return 0;
1769 }
1770
1771 int
m16_usym5_4(op,mode)1772 m16_usym5_4 (op, mode)
1773 rtx op;
1774 enum machine_mode mode ATTRIBUTE_UNUSED;
1775 {
1776 if (GET_CODE (op) == SYMBOL_REF
1777 && SYMBOL_REF_FLAG (op)
1778 && cfun->machine->insns_len > 0
1779 && XSTR (op, 0)[0] == '*'
1780 && strncmp (XSTR (op, 0) + 1, LOCAL_LABEL_PREFIX,
1781 sizeof LOCAL_LABEL_PREFIX - 1) == 0
1782 && (cfun->machine->insns_len + get_pool_size () + mips_string_length
1783 < 4 * 0x20))
1784 {
1785 struct string_constant *l;
1786
1787 /* Make sure this symbol is on thelist of string constants to be
1788 output for this function. It is possible that it has already
1789 been output, in which case this requires a large offset. */
1790 for (l = string_constants; l != NULL; l = l->next)
1791 if (strcmp (l->label, XSTR (op, 0)) == 0)
1792 return 1;
1793 }
1794
1795 return 0;
1796 }
1797
1798 /* Returns an operand string for the given instruction's delay slot,
1799 after updating filled delay slot statistics.
1800
1801 We assume that operands[0] is the target register that is set.
1802
1803 In order to check the next insn, most of this functionality is moved
1804 to FINAL_PRESCAN_INSN, and we just set the global variables that
1805 it needs. */
1806
1807 /* ??? This function no longer does anything useful, because final_prescan_insn
1808 now will never emit a nop. */
1809
1810 const char *
mips_fill_delay_slot(ret,type,operands,cur_insn)1811 mips_fill_delay_slot (ret, type, operands, cur_insn)
1812 const char *ret; /* normal string to return */
1813 enum delay_type type; /* type of delay */
1814 rtx operands[]; /* operands to use */
1815 rtx cur_insn; /* current insn */
1816 {
1817 register rtx set_reg;
1818 register enum machine_mode mode;
1819 register rtx next_insn = cur_insn ? NEXT_INSN (cur_insn) : NULL_RTX;
1820 register int num_nops;
1821
1822 if (type == DELAY_LOAD || type == DELAY_FCMP)
1823 num_nops = 1;
1824
1825 else if (type == DELAY_HILO)
1826 num_nops = 2;
1827
1828 else
1829 num_nops = 0;
1830
1831 /* Make sure that we don't put nop's after labels. */
1832 next_insn = NEXT_INSN (cur_insn);
1833 while (next_insn != 0 && GET_CODE (next_insn) == NOTE)
1834 next_insn = NEXT_INSN (next_insn);
1835
1836 dslots_load_total += num_nops;
1837 if (TARGET_DEBUG_F_MODE
1838 || !optimize
1839 || type == DELAY_NONE
1840 || operands == 0
1841 || cur_insn == 0
1842 || next_insn == 0
1843 || GET_CODE (next_insn) == CODE_LABEL
1844 || (set_reg = operands[0]) == 0)
1845 {
1846 dslots_number_nops = 0;
1847 mips_load_reg = 0;
1848 mips_load_reg2 = 0;
1849 mips_load_reg3 = 0;
1850 mips_load_reg4 = 0;
1851 return ret;
1852 }
1853
1854 set_reg = operands[0];
1855 if (set_reg == 0)
1856 return ret;
1857
1858 while (GET_CODE (set_reg) == SUBREG)
1859 set_reg = SUBREG_REG (set_reg);
1860
1861 mode = GET_MODE (set_reg);
1862 dslots_number_nops = num_nops;
1863 mips_load_reg = set_reg;
1864 if (GET_MODE_SIZE (mode)
1865 > (unsigned) (FP_REG_P (REGNO (set_reg)) ? UNITS_PER_FPREG : UNITS_PER_WORD))
1866 mips_load_reg2 = gen_rtx_REG (SImode, REGNO (set_reg) + 1);
1867 else
1868 mips_load_reg2 = 0;
1869
1870 if (type == DELAY_HILO)
1871 {
1872 mips_load_reg3 = gen_rtx_REG (SImode, MD_REG_FIRST);
1873 mips_load_reg4 = gen_rtx_REG (SImode, MD_REG_FIRST+1);
1874 }
1875 else
1876 {
1877 mips_load_reg3 = 0;
1878 mips_load_reg4 = 0;
1879 }
1880
1881 return ret;
1882 }
1883
1884
1885 /* Determine whether a memory reference takes one (based off of the GP
1886 pointer), two (normal), or three (label + reg) instructions, and bump the
1887 appropriate counter for -mstats. */
1888
1889 void
mips_count_memory_refs(op,num)1890 mips_count_memory_refs (op, num)
1891 rtx op;
1892 int num;
1893 {
1894 int additional = 0;
1895 int n_words = 0;
1896 rtx addr, plus0, plus1;
1897 enum rtx_code code0, code1;
1898 int looping;
1899
1900 if (TARGET_DEBUG_B_MODE)
1901 {
1902 fprintf (stderr, "\n========== mips_count_memory_refs:\n");
1903 debug_rtx (op);
1904 }
1905
1906 /* Skip MEM if passed, otherwise handle movsi of address. */
1907 addr = (GET_CODE (op) != MEM) ? op : XEXP (op, 0);
1908
1909 /* Loop, going through the address RTL. */
1910 do
1911 {
1912 looping = FALSE;
1913 switch (GET_CODE (addr))
1914 {
1915 case REG:
1916 case CONST_INT:
1917 case LO_SUM:
1918 break;
1919
1920 case PLUS:
1921 plus0 = XEXP (addr, 0);
1922 plus1 = XEXP (addr, 1);
1923 code0 = GET_CODE (plus0);
1924 code1 = GET_CODE (plus1);
1925
1926 if (code0 == REG)
1927 {
1928 additional++;
1929 addr = plus1;
1930 looping = 1;
1931 continue;
1932 }
1933
1934 if (code0 == CONST_INT)
1935 {
1936 addr = plus1;
1937 looping = 1;
1938 continue;
1939 }
1940
1941 if (code1 == REG)
1942 {
1943 additional++;
1944 addr = plus0;
1945 looping = 1;
1946 continue;
1947 }
1948
1949 if (code1 == CONST_INT)
1950 {
1951 addr = plus0;
1952 looping = 1;
1953 continue;
1954 }
1955
1956 if (code0 == SYMBOL_REF || code0 == LABEL_REF || code0 == CONST)
1957 {
1958 addr = plus0;
1959 looping = 1;
1960 continue;
1961 }
1962
1963 if (code1 == SYMBOL_REF || code1 == LABEL_REF || code1 == CONST)
1964 {
1965 addr = plus1;
1966 looping = 1;
1967 continue;
1968 }
1969
1970 break;
1971
1972 case LABEL_REF:
1973 n_words = 2; /* always 2 words */
1974 break;
1975
1976 case CONST:
1977 addr = XEXP (addr, 0);
1978 looping = 1;
1979 continue;
1980
1981 case SYMBOL_REF:
1982 n_words = SYMBOL_REF_FLAG (addr) ? 1 : 2;
1983 break;
1984
1985 default:
1986 break;
1987 }
1988 }
1989 while (looping);
1990
1991 if (n_words == 0)
1992 return;
1993
1994 n_words += additional;
1995 if (n_words > 3)
1996 n_words = 3;
1997
1998 num_refs[n_words-1] += num;
1999 }
2000
2001
2002 /* Return a pseudo that points to the address of the current function.
2003 The first time it is called for a function, an initializer for the
2004 pseudo is emitted in the beginning of the function. */
2005
2006 rtx
embedded_pic_fnaddr_reg()2007 embedded_pic_fnaddr_reg ()
2008 {
2009 if (cfun->machine->embedded_pic_fnaddr_rtx == NULL)
2010 {
2011 rtx seq;
2012
2013 cfun->machine->embedded_pic_fnaddr_rtx = gen_reg_rtx (Pmode);
2014
2015 /* Output code at function start to initialize the pseudo-reg. */
2016 /* ??? We used to do this in FINALIZE_PIC, but that does not work for
2017 inline functions, because it is called after RTL for the function
2018 has been copied. The pseudo-reg in embedded_pic_fnaddr_rtx however
2019 does not get copied, and ends up not matching the rest of the RTL.
2020 This solution works, but means that we get unnecessary code to
2021 initialize this value every time a function is inlined into another
2022 function. */
2023 start_sequence ();
2024 emit_insn (gen_get_fnaddr (cfun->machine->embedded_pic_fnaddr_rtx,
2025 XEXP (DECL_RTL (current_function_decl), 0)));
2026 seq = get_insns ();
2027 end_sequence ();
2028 push_topmost_sequence ();
2029 emit_insn_after (seq, get_insns ());
2030 pop_topmost_sequence ();
2031 }
2032
2033 return cfun->machine->embedded_pic_fnaddr_rtx;
2034 }
2035
2036 /* Return RTL for the offset from the current function to the argument.
2037 X is the symbol whose offset from the current function we want. */
2038
2039 rtx
embedded_pic_offset(x)2040 embedded_pic_offset (x)
2041 rtx x;
2042 {
2043 /* Make sure it is emitted. */
2044 embedded_pic_fnaddr_reg ();
2045
2046 return
2047 gen_rtx_CONST (Pmode,
2048 gen_rtx_MINUS (Pmode, x,
2049 XEXP (DECL_RTL (current_function_decl), 0)));
2050 }
2051
2052 /* Return the appropriate instructions to move one operand to another. */
2053
2054 const char *
mips_move_1word(operands,insn,unsignedp)2055 mips_move_1word (operands, insn, unsignedp)
2056 rtx operands[];
2057 rtx insn;
2058 int unsignedp;
2059 {
2060 const char *ret = 0;
2061 rtx op0 = operands[0];
2062 rtx op1 = operands[1];
2063 enum rtx_code code0 = GET_CODE (op0);
2064 enum rtx_code code1 = GET_CODE (op1);
2065 enum machine_mode mode = GET_MODE (op0);
2066 int subreg_offset0 = 0;
2067 int subreg_offset1 = 0;
2068 enum delay_type delay = DELAY_NONE;
2069
2070 while (code0 == SUBREG)
2071 {
2072 subreg_offset0 += subreg_regno_offset (REGNO (SUBREG_REG (op0)),
2073 GET_MODE (SUBREG_REG (op0)),
2074 SUBREG_BYTE (op0),
2075 GET_MODE (op0));
2076 op0 = SUBREG_REG (op0);
2077 code0 = GET_CODE (op0);
2078 }
2079
2080 while (code1 == SUBREG)
2081 {
2082 subreg_offset1 += subreg_regno_offset (REGNO (SUBREG_REG (op1)),
2083 GET_MODE (SUBREG_REG (op1)),
2084 SUBREG_BYTE (op1),
2085 GET_MODE (op1));
2086 op1 = SUBREG_REG (op1);
2087 code1 = GET_CODE (op1);
2088 }
2089
2090 /* For our purposes, a condition code mode is the same as SImode. */
2091 if (mode == CCmode)
2092 mode = SImode;
2093
2094 if (code0 == REG)
2095 {
2096 int regno0 = REGNO (op0) + subreg_offset0;
2097
2098 if (code1 == REG)
2099 {
2100 int regno1 = REGNO (op1) + subreg_offset1;
2101
2102 /* Just in case, don't do anything for assigning a register
2103 to itself, unless we are filling a delay slot. */
2104 if (regno0 == regno1 && set_nomacro == 0)
2105 ret = "";
2106
2107 else if (GP_REG_P (regno0))
2108 {
2109 if (GP_REG_P (regno1))
2110 ret = "move\t%0,%1";
2111
2112 else if (MD_REG_P (regno1))
2113 {
2114 delay = DELAY_HILO;
2115 if (regno1 != HILO_REGNUM)
2116 ret = "mf%1\t%0";
2117 else
2118 ret = "mflo\t%0";
2119 }
2120
2121 else if (ST_REG_P (regno1) && ISA_HAS_8CC)
2122 ret = "li\t%0,1\n\tmovf\t%0,%.,%1";
2123
2124 else
2125 {
2126 delay = DELAY_LOAD;
2127 if (FP_REG_P (regno1))
2128 ret = "mfc1\t%0,%1";
2129 else if (ALL_COP_REG_P (regno1))
2130 {
2131 static char retval[] = "mfc_\t%0,%1";
2132
2133 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (regno1);
2134 ret = retval;
2135 }
2136 else if (regno1 == FPSW_REGNUM && ! ISA_HAS_8CC)
2137 ret = "cfc1\t%0,$31";
2138 }
2139 }
2140
2141 else if (FP_REG_P (regno0))
2142 {
2143 if (GP_REG_P (regno1))
2144 {
2145 delay = DELAY_LOAD;
2146 ret = "mtc1\t%1,%0";
2147 }
2148
2149 if (FP_REG_P (regno1))
2150 ret = "mov.s\t%0,%1";
2151 }
2152
2153 else if (MD_REG_P (regno0))
2154 {
2155 if (GP_REG_P (regno1))
2156 {
2157 delay = DELAY_HILO;
2158 if (regno0 != HILO_REGNUM && ! TARGET_MIPS16)
2159 ret = "mt%0\t%1";
2160 }
2161 }
2162
2163 else if (regno0 == FPSW_REGNUM && ! ISA_HAS_8CC)
2164 {
2165 if (GP_REG_P (regno1))
2166 {
2167 delay = DELAY_LOAD;
2168 ret = "ctc1\t%0,$31";
2169 }
2170 }
2171 else if (ALL_COP_REG_P (regno0))
2172 {
2173 if (GP_REG_P (regno1))
2174 {
2175 static char retval[] = "mtc_\t%1,%0";
2176 char cop = COPNUM_AS_CHAR_FROM_REGNUM (regno0);
2177
2178 if (cop == '0')
2179 abort_with_insn (insn,
2180 "mtc0 not supported; it disturbs virtual address translation");
2181 delay = DELAY_LOAD;
2182 retval[3] = cop;
2183 ret = retval;
2184 }
2185 }
2186 }
2187
2188 else if (code1 == MEM)
2189 {
2190 delay = DELAY_LOAD;
2191
2192 if (TARGET_STATS)
2193 mips_count_memory_refs (op1, 1);
2194
2195 if (GP_REG_P (regno0))
2196 {
2197 /* For loads, use the mode of the memory item, instead of the
2198 target, so zero/sign extend can use this code as well. */
2199 switch (GET_MODE (op1))
2200 {
2201 default:
2202 break;
2203 case SFmode:
2204 ret = "lw\t%0,%1";
2205 break;
2206 case SImode:
2207 case CCmode:
2208 ret = ((unsignedp && TARGET_64BIT)
2209 ? "lwu\t%0,%1"
2210 : "lw\t%0,%1");
2211 break;
2212 case HImode:
2213 ret = (unsignedp) ? "lhu\t%0,%1" : "lh\t%0,%1";
2214 break;
2215 case QImode:
2216 ret = (unsignedp) ? "lbu\t%0,%1" : "lb\t%0,%1";
2217 break;
2218 }
2219 }
2220
2221 else if (FP_REG_P (regno0) && (mode == SImode || mode == SFmode))
2222 ret = "l.s\t%0,%1";
2223
2224 else if (ALL_COP_REG_P (regno0))
2225 {
2226 static char retval[] = "lwc_\t%0,%1";
2227 char cop = COPNUM_AS_CHAR_FROM_REGNUM (regno0);
2228
2229 if (cop == '0')
2230 abort_with_insn (insn,
2231 "loads from memory to COP0 are illegal");
2232 delay = DELAY_LOAD;
2233 retval[3] = cop;
2234 ret = retval;
2235 }
2236
2237 if (ret != (char *)0 && MEM_VOLATILE_P (op1))
2238 {
2239 size_t i = strlen (ret);
2240 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
2241 abort ();
2242
2243 sprintf (volatile_buffer, "%%{%s%%}", ret);
2244 ret = volatile_buffer;
2245 }
2246 }
2247
2248 else if (code1 == CONST_INT
2249 || (code1 == CONST_DOUBLE
2250 && GET_MODE (op1) == VOIDmode))
2251 {
2252 if (code1 == CONST_DOUBLE)
2253 {
2254 /* This can happen when storing constants into long long
2255 bitfields. Just store the least significant word of
2256 the value. */
2257 operands[1] = op1 = GEN_INT (CONST_DOUBLE_LOW (op1));
2258 }
2259
2260 if (INTVAL (op1) == 0 && ! TARGET_MIPS16)
2261 {
2262 if (GP_REG_P (regno0))
2263 ret = "move\t%0,%z1";
2264
2265 else if (FP_REG_P (regno0))
2266 {
2267 delay = DELAY_LOAD;
2268 ret = "mtc1\t%z1,%0";
2269 }
2270
2271 else if (MD_REG_P (regno0))
2272 {
2273 delay = DELAY_HILO;
2274 ret = "mt%0\t%.";
2275 }
2276 }
2277
2278 else if (GP_REG_P (regno0))
2279 {
2280 /* Don't use X format, because that will give out of
2281 range numbers for 64 bit host and 32 bit target. */
2282 if (! TARGET_MIPS16)
2283 ret = "li\t%0,%1\t\t\t# %X1";
2284 else
2285 {
2286 if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff)
2287 ret = "li\t%0,%1";
2288 else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff)
2289 ret = "li\t%0,%n1\n\tneg\t%0";
2290 }
2291 }
2292 }
2293
2294 else if (code1 == CONST_DOUBLE && mode == SFmode)
2295 {
2296 if (op1 == CONST0_RTX (SFmode))
2297 {
2298 if (GP_REG_P (regno0))
2299 ret = "move\t%0,%.";
2300
2301 else if (FP_REG_P (regno0))
2302 {
2303 delay = DELAY_LOAD;
2304 ret = "mtc1\t%.,%0";
2305 }
2306 }
2307
2308 else
2309 {
2310 delay = DELAY_LOAD;
2311 ret = "li.s\t%0,%1";
2312 }
2313 }
2314
2315 else if (code1 == LABEL_REF)
2316 {
2317 if (TARGET_STATS)
2318 mips_count_memory_refs (op1, 1);
2319
2320 ret = "la\t%0,%a1";
2321 }
2322
2323 else if (code1 == SYMBOL_REF || code1 == CONST)
2324 {
2325 if (TARGET_MIPS16
2326 && code1 == CONST
2327 && GET_CODE (XEXP (op1, 0)) == REG
2328 && REGNO (XEXP (op1, 0)) == GP_REG_FIRST + 28)
2329 {
2330 /* This case arises on the mips16; see
2331 mips16_gp_pseudo_reg. */
2332 ret = "move\t%0,%+";
2333 }
2334 else if (TARGET_MIPS16
2335 && code1 == SYMBOL_REF
2336 && SYMBOL_REF_FLAG (op1)
2337 && (XSTR (op1, 0)[0] != '*'
2338 || strncmp (XSTR (op1, 0) + 1,
2339 LOCAL_LABEL_PREFIX,
2340 sizeof LOCAL_LABEL_PREFIX - 1) != 0))
2341 {
2342 /* This can occur when reloading the address of a GP
2343 relative symbol on the mips16. */
2344 ret = "move\t%0,%+\n\taddu\t%0,%%gprel(%a1)";
2345 }
2346 else
2347 {
2348 if (TARGET_STATS)
2349 mips_count_memory_refs (op1, 1);
2350
2351 ret = "la\t%0,%a1";
2352 }
2353 }
2354
2355 else if (code1 == PLUS)
2356 {
2357 rtx add_op0 = XEXP (op1, 0);
2358 rtx add_op1 = XEXP (op1, 1);
2359
2360 if (GET_CODE (XEXP (op1, 1)) == REG
2361 && GET_CODE (XEXP (op1, 0)) == CONST_INT)
2362 add_op0 = XEXP (op1, 1), add_op1 = XEXP (op1, 0);
2363
2364 operands[2] = add_op0;
2365 operands[3] = add_op1;
2366 ret = "add%:\t%0,%2,%3";
2367 }
2368
2369 else if (code1 == HIGH)
2370 {
2371 operands[1] = XEXP (op1, 0);
2372 ret = "lui\t%0,%%hi(%1)";
2373 }
2374 }
2375
2376 else if (code0 == MEM)
2377 {
2378 if (TARGET_STATS)
2379 mips_count_memory_refs (op0, 1);
2380
2381 if (code1 == REG)
2382 {
2383 int regno1 = REGNO (op1) + subreg_offset1;
2384
2385 if (GP_REG_P (regno1))
2386 {
2387 switch (mode)
2388 {
2389 case SFmode: ret = "sw\t%1,%0"; break;
2390 case SImode: ret = "sw\t%1,%0"; break;
2391 case HImode: ret = "sh\t%1,%0"; break;
2392 case QImode: ret = "sb\t%1,%0"; break;
2393 default: break;
2394 }
2395 }
2396
2397 else if (FP_REG_P (regno1) && (mode == SImode || mode == SFmode))
2398 ret = "s.s\t%1,%0";
2399 else if (ALL_COP_REG_P (regno1))
2400 {
2401 static char retval[] = "swc_\t%1,%0";
2402
2403 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (regno1);
2404 ret = retval;
2405 }
2406 }
2407
2408 else if (code1 == CONST_INT && INTVAL (op1) == 0)
2409 {
2410 switch (mode)
2411 {
2412 case SFmode: ret = "sw\t%z1,%0"; break;
2413 case SImode: ret = "sw\t%z1,%0"; break;
2414 case HImode: ret = "sh\t%z1,%0"; break;
2415 case QImode: ret = "sb\t%z1,%0"; break;
2416 default: break;
2417 }
2418 }
2419
2420 else if (code1 == CONST_DOUBLE && op1 == CONST0_RTX (mode))
2421 {
2422 switch (mode)
2423 {
2424 case SFmode: ret = "sw\t%.,%0"; break;
2425 case SImode: ret = "sw\t%.,%0"; break;
2426 case HImode: ret = "sh\t%.,%0"; break;
2427 case QImode: ret = "sb\t%.,%0"; break;
2428 default: break;
2429 }
2430 }
2431
2432 if (ret != 0 && MEM_VOLATILE_P (op0))
2433 {
2434 size_t i = strlen (ret);
2435
2436 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
2437 abort ();
2438
2439 sprintf (volatile_buffer, "%%{%s%%}", ret);
2440 ret = volatile_buffer;
2441 }
2442 }
2443
2444 if (ret == 0)
2445 {
2446 abort_with_insn (insn, "bad move");
2447 return 0;
2448 }
2449
2450 if (delay != DELAY_NONE)
2451 return mips_fill_delay_slot (ret, delay, operands, insn);
2452
2453 return ret;
2454 }
2455
2456 /* Return instructions to restore the global pointer from the stack,
2457 assuming TARGET_ABICALLS. Used by exception_receiver to set up
2458 the GP for exception handlers.
2459
2460 OPERANDS is an array of operands whose contents are undefined
2461 on entry. INSN is the exception_handler instruction. */
2462
2463 const char *
mips_restore_gp(operands,insn)2464 mips_restore_gp (operands, insn)
2465 rtx *operands, insn;
2466 {
2467 rtx loc;
2468
2469 operands[0] = pic_offset_table_rtx;
2470 if (frame_pointer_needed)
2471 loc = hard_frame_pointer_rtx;
2472 else
2473 loc = stack_pointer_rtx;
2474 loc = plus_constant (loc, cfun->machine->frame.args_size);
2475 operands[1] = gen_rtx_MEM (Pmode, loc);
2476
2477 return mips_move_1word (operands, insn, 0);
2478 }
2479
2480 /* Return an instruction to sign-extend SImode value SRC and store it
2481 in DImode value DEST. INSN is the original extendsidi2-type insn. */
2482
2483 const char *
mips_sign_extend(insn,dest,src)2484 mips_sign_extend (insn, dest, src)
2485 rtx insn, dest, src;
2486 {
2487 rtx operands[MAX_RECOG_OPERANDS];
2488
2489 if ((register_operand (src, SImode) && FP_REG_P (true_regnum (src)))
2490 || memory_operand (src, SImode))
2491 {
2492 /* If the source is a floating-point register, we need to use a
2493 32-bit move, since the float register is not kept sign-extended.
2494 If the source is in memory, we need a 32-bit load. */
2495 operands[0] = gen_lowpart_SUBREG (SImode, dest);
2496 operands[1] = src;
2497 return mips_move_1word (operands, insn, false);
2498 }
2499 else
2500 {
2501 operands[0] = dest;
2502 operands[1] = src;
2503 return mips_move_2words (operands, insn);
2504 }
2505 }
2506
2507 /* Return the appropriate instructions to move 2 words */
2508
2509 const char *
mips_move_2words(operands,insn)2510 mips_move_2words (operands, insn)
2511 rtx operands[];
2512 rtx insn;
2513 {
2514 const char *ret = 0;
2515 rtx op0 = operands[0];
2516 rtx op1 = operands[1];
2517 enum rtx_code code0 = GET_CODE (operands[0]);
2518 enum rtx_code code1 = GET_CODE (operands[1]);
2519 int subreg_offset0 = 0;
2520 int subreg_offset1 = 0;
2521 enum delay_type delay = DELAY_NONE;
2522
2523 if (code1 == SIGN_EXTEND)
2524 return mips_sign_extend (insn, op0, XEXP (op1, 0));
2525
2526 while (code0 == SUBREG)
2527 {
2528 subreg_offset0 += subreg_regno_offset (REGNO (SUBREG_REG (op0)),
2529 GET_MODE (SUBREG_REG (op0)),
2530 SUBREG_BYTE (op0),
2531 GET_MODE (op0));
2532 op0 = SUBREG_REG (op0);
2533 code0 = GET_CODE (op0);
2534 }
2535
2536 while (code1 == SUBREG)
2537 {
2538 subreg_offset1 += subreg_regno_offset (REGNO (SUBREG_REG (op1)),
2539 GET_MODE (SUBREG_REG (op1)),
2540 SUBREG_BYTE (op1),
2541 GET_MODE (op1));
2542 op1 = SUBREG_REG (op1);
2543 code1 = GET_CODE (op1);
2544 }
2545
2546 if (code0 == REG)
2547 {
2548 int regno0 = REGNO (op0) + subreg_offset0;
2549
2550 if (code1 == REG)
2551 {
2552 int regno1 = REGNO (op1) + subreg_offset1;
2553
2554 /* Just in case, don't do anything for assigning a register
2555 to itself, unless we are filling a delay slot. */
2556 if (regno0 == regno1 && set_nomacro == 0)
2557 ret = "";
2558
2559 else if (FP_REG_P (regno0))
2560 {
2561 if (FP_REG_P (regno1))
2562 ret = "mov.d\t%0,%1";
2563
2564 else
2565 {
2566 delay = DELAY_LOAD;
2567 if (TARGET_FLOAT64)
2568 {
2569 if (!TARGET_64BIT)
2570 abort_with_insn (insn, "bad move");
2571
2572 #ifdef TARGET_FP_CALL_32
2573 if (FP_CALL_GP_REG_P (regno1))
2574 ret = "dsll\t%1,32\n\tor\t%1,%D1\n\tdmtc1\t%1,%0";
2575 else
2576 #endif
2577 ret = "dmtc1\t%1,%0";
2578 }
2579 else
2580 ret = "mtc1\t%L1,%0\n\tmtc1\t%M1,%D0";
2581 }
2582 }
2583
2584 else if (FP_REG_P (regno1))
2585 {
2586 delay = DELAY_LOAD;
2587 if (TARGET_FLOAT64)
2588 {
2589 if (!TARGET_64BIT)
2590 abort_with_insn (insn, "bad move");
2591
2592 #ifdef TARGET_FP_CALL_32
2593 if (FP_CALL_GP_REG_P (regno0))
2594 ret = "dmfc1\t%0,%1\n\tmfc1\t%D0,%1\n\tdsrl\t%0,32";
2595 else
2596 #endif
2597 ret = "dmfc1\t%0,%1";
2598 }
2599 else
2600 ret = "mfc1\t%L0,%1\n\tmfc1\t%M0,%D1";
2601 }
2602
2603 else if (MD_REG_P (regno0) && GP_REG_P (regno1) && !TARGET_MIPS16)
2604 {
2605 delay = DELAY_HILO;
2606 if (TARGET_64BIT)
2607 {
2608 if (regno0 != HILO_REGNUM)
2609 ret = "mt%0\t%1";
2610 else if (regno1 == 0)
2611 ret = "mtlo\t%.\n\tmthi\t%.";
2612 }
2613 else
2614 ret = "mthi\t%M1\n\tmtlo\t%L1";
2615 }
2616
2617 else if (GP_REG_P (regno0) && MD_REG_P (regno1))
2618 {
2619 delay = DELAY_HILO;
2620 if (TARGET_64BIT)
2621 {
2622 if (regno1 != HILO_REGNUM)
2623 ret = "mf%1\t%0";
2624 }
2625 else
2626 ret = "mfhi\t%M0\n\tmflo\t%L0";
2627 }
2628 else if (GP_REG_P (regno0) && ALL_COP_REG_P (regno1)
2629 && TARGET_64BIT)
2630 {
2631 static char retval[] = "dmfc_\t%0,%1";
2632
2633 delay = DELAY_LOAD;
2634 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (regno1);
2635 ret = retval;
2636 }
2637 else if (ALL_COP_REG_P (regno0) && GP_REG_P (regno1)
2638 && TARGET_64BIT)
2639 {
2640 static char retval[] = "dmtc_\t%1,%0";
2641 char cop = COPNUM_AS_CHAR_FROM_REGNUM (regno0);
2642
2643 if (cop == '0')
2644 abort_with_insn (insn,
2645 "dmtc0 not supported; it disturbs virtual address translation");
2646 delay = DELAY_LOAD;
2647 retval[4] = cop;
2648 ret = retval;
2649 }
2650 else if (TARGET_64BIT)
2651 ret = "move\t%0,%1";
2652
2653 else if (regno0 != (regno1+1))
2654 ret = "move\t%0,%1\n\tmove\t%D0,%D1";
2655
2656 else
2657 ret = "move\t%D0,%D1\n\tmove\t%0,%1";
2658 }
2659
2660 else if (code1 == CONST_DOUBLE)
2661 {
2662 /* Move zero from $0 unless !TARGET_64BIT and recipient
2663 is 64-bit fp reg, in which case generate a constant. */
2664 if (op1 != CONST0_RTX (GET_MODE (op1))
2665 || (TARGET_FLOAT64 && !TARGET_64BIT && FP_REG_P (regno0)))
2666 {
2667 if (GET_MODE (op1) == DFmode)
2668 {
2669 delay = DELAY_LOAD;
2670
2671 #ifdef TARGET_FP_CALL_32
2672 if (FP_CALL_GP_REG_P (regno0))
2673 {
2674 if (TARGET_FLOAT64 && !TARGET_64BIT)
2675 {
2676 split_double (op1, operands + 2, operands + 3);
2677 ret = "li\t%0,%2\n\tli\t%D0,%3";
2678 }
2679 else
2680 ret = "li.d\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32";
2681 }
2682 else
2683 #endif
2684 /* GNU as emits 64-bit code for li.d if the ISA is 3
2685 or higher. For !TARGET_64BIT && gp registers we
2686 need to avoid this by using two li instructions
2687 instead. */
2688 if (ISA_HAS_64BIT_REGS
2689 && ! TARGET_64BIT
2690 && ! FP_REG_P (regno0))
2691 {
2692 split_double (op1, operands + 2, operands + 3);
2693 ret = "li\t%0,%2\n\tli\t%D0,%3";
2694 }
2695 else
2696 ret = "li.d\t%0,%1";
2697 }
2698
2699 else if (TARGET_64BIT)
2700 {
2701 if (! TARGET_MIPS16)
2702 ret = "dli\t%0,%1";
2703 }
2704
2705 else
2706 {
2707 split_double (op1, operands + 2, operands + 3);
2708 ret = "li\t%0,%2\n\tli\t%D0,%3";
2709 }
2710 }
2711
2712 else
2713 {
2714 if (GP_REG_P (regno0))
2715 ret = (TARGET_64BIT
2716 #ifdef TARGET_FP_CALL_32
2717 && ! FP_CALL_GP_REG_P (regno0)
2718 #endif
2719 ? "move\t%0,%."
2720 : "move\t%0,%.\n\tmove\t%D0,%.");
2721
2722 else if (FP_REG_P (regno0))
2723 {
2724 delay = DELAY_LOAD;
2725 ret = (TARGET_64BIT
2726 ? "dmtc1\t%.,%0"
2727 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0");
2728 }
2729 }
2730 }
2731
2732 else if (code1 == CONST_INT && INTVAL (op1) == 0 && ! TARGET_MIPS16)
2733 {
2734 if (GP_REG_P (regno0))
2735 ret = (TARGET_64BIT
2736 ? "move\t%0,%."
2737 : "move\t%0,%.\n\tmove\t%D0,%.");
2738
2739 else if (FP_REG_P (regno0))
2740 {
2741 delay = DELAY_LOAD;
2742 ret = (TARGET_64BIT
2743 ? "dmtc1\t%.,%0"
2744 : (TARGET_FLOAT64
2745 ? "li.d\t%0,%1"
2746 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0"));
2747 }
2748 else if (MD_REG_P (regno0))
2749 {
2750 delay = DELAY_HILO;
2751 ret = (regno0 == HILO_REGNUM
2752 ? "mtlo\t%.\n\tmthi\t%."
2753 : "mt%0\t%.\n");
2754 }
2755 }
2756
2757 else if (code1 == CONST_INT && GET_MODE (op0) == DImode
2758 && GP_REG_P (regno0))
2759 {
2760 if (TARGET_64BIT)
2761 {
2762 if (TARGET_MIPS16)
2763 {
2764 if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff)
2765 ret = "li\t%0,%1";
2766 else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff)
2767 ret = "li\t%0,%n1\n\tneg\t%0";
2768 }
2769 else if (GET_CODE (operands[1]) == SIGN_EXTEND)
2770 ret = "li\t%0,%1\t\t# %X1";
2771 else if (HOST_BITS_PER_WIDE_INT < 64)
2772 /* We can't use 'X' for negative numbers, because then we won't
2773 get the right value for the upper 32 bits. */
2774 ret = (INTVAL (op1) < 0
2775 ? "dli\t%0,%1\t\t\t# %X1"
2776 : "dli\t%0,%X1\t\t# %1");
2777 else
2778 /* We must use 'X', because otherwise LONG_MIN will print as
2779 a number that the assembler won't accept. */
2780 ret = "dli\t%0,%X1\t\t# %1";
2781 }
2782 else if (HOST_BITS_PER_WIDE_INT < 64)
2783 {
2784 operands[2] = GEN_INT (INTVAL (operands[1]) >= 0 ? 0 : -1);
2785 if (TARGET_MIPS16)
2786 {
2787 if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff)
2788 ret = "li\t%M0,%2\n\tli\t%L0,%1";
2789 else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff)
2790 {
2791 operands[2] = GEN_INT (1);
2792 ret = "li\t%M0,%2\n\tneg\t%M0\n\tli\t%L0,%n1\n\tneg\t%L0";
2793 }
2794 }
2795 else
2796 ret = "li\t%M0,%2\n\tli\t%L0,%1";
2797 }
2798 else
2799 {
2800 /* We use multiple shifts here, to avoid warnings about out
2801 of range shifts on 32 bit hosts. */
2802 operands[2] = GEN_INT (INTVAL (operands[1]) >> 16 >> 16);
2803 operands[1]
2804 = GEN_INT (INTVAL (operands[1]) << 16 << 16 >> 16 >> 16);
2805 if (TARGET_MIPS16)
2806 {
2807 if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff)
2808 ret = "li\t%M0,%2\n\tli\t%L0,%1";
2809 else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff)
2810 {
2811 operands[2] = GEN_INT (1);
2812 ret = "li\t%M0,%2\n\tneg\t%M0\n\tli\t%L0,%n1\n\tneg\t%L0";
2813 }
2814 }
2815 else
2816 ret = "li\t%M0,%2\n\tli\t%L0,%1";
2817 }
2818 }
2819
2820 else if (code1 == MEM)
2821 {
2822 delay = DELAY_LOAD;
2823
2824 if (TARGET_STATS)
2825 mips_count_memory_refs (op1, 2);
2826
2827 if (FP_REG_P (regno0))
2828 ret = "l.d\t%0,%1";
2829
2830 else if (ALL_COP_REG_P (regno0) && TARGET_64BIT)
2831 {
2832 static char retval[] = "ldc_\t%0,%1";
2833 char cop = COPNUM_AS_CHAR_FROM_REGNUM (regno0);
2834
2835 if (cop == '0')
2836 abort_with_insn (insn,
2837 "loads from memory to COP0 are illegal");
2838 delay = DELAY_LOAD;
2839 retval[3] = cop;
2840 ret = retval;
2841 }
2842
2843 else if (TARGET_64BIT)
2844 {
2845
2846 #ifdef TARGET_FP_CALL_32
2847 if (FP_CALL_GP_REG_P (regno0))
2848 ret = (double_memory_operand (op1, GET_MODE (op1))
2849 ? "lwu\t%0,%1\n\tlwu\t%D0,4+%1"
2850 : "ld\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32");
2851 else
2852 #endif
2853 ret = "ld\t%0,%1";
2854 }
2855
2856 else if (double_memory_operand (op1, GET_MODE (op1)))
2857 ret = (reg_mentioned_p (op0, op1)
2858 ? "lw\t%D0,%D1\n\tlw\t%0,%1"
2859 : "lw\t%0,%1\n\tlw\t%D0,%D1");
2860
2861 if (ret != 0 && MEM_VOLATILE_P (op1))
2862 {
2863 size_t i = strlen (ret);
2864
2865 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
2866 abort ();
2867
2868 sprintf (volatile_buffer, "%%{%s%%}", ret);
2869 ret = volatile_buffer;
2870 }
2871 }
2872
2873 else if (code1 == LABEL_REF)
2874 {
2875 if (TARGET_STATS)
2876 mips_count_memory_refs (op1, 2);
2877
2878 if (GET_CODE (operands[1]) == SIGN_EXTEND)
2879 /* We deliberately remove the 'a' from '%1', so that we don't
2880 have to add SIGN_EXTEND support to print_operand_address.
2881 print_operand will just call print_operand_address in this
2882 case, so there is no problem. */
2883 ret = "la\t%0,%1";
2884 else
2885 ret = "dla\t%0,%a1";
2886 }
2887 else if (code1 == SYMBOL_REF || code1 == CONST)
2888 {
2889 if (TARGET_MIPS16
2890 && code1 == CONST
2891 && GET_CODE (XEXP (op1, 0)) == REG
2892 && REGNO (XEXP (op1, 0)) == GP_REG_FIRST + 28)
2893 {
2894 /* This case arises on the mips16; see
2895 mips16_gp_pseudo_reg. */
2896 ret = "move\t%0,%+";
2897 }
2898 else if (TARGET_MIPS16
2899 && code1 == SYMBOL_REF
2900 && SYMBOL_REF_FLAG (op1)
2901 && (XSTR (op1, 0)[0] != '*'
2902 || strncmp (XSTR (op1, 0) + 1,
2903 LOCAL_LABEL_PREFIX,
2904 sizeof LOCAL_LABEL_PREFIX - 1) != 0))
2905 {
2906 /* This can occur when reloading the address of a GP
2907 relative symbol on the mips16. */
2908 ret = "move\t%0,%+\n\taddu\t%0,%%gprel(%a1)";
2909 }
2910 else
2911 {
2912 if (TARGET_STATS)
2913 mips_count_memory_refs (op1, 2);
2914
2915 if (GET_CODE (operands[1]) == SIGN_EXTEND)
2916 /* We deliberately remove the 'a' from '%1', so that we don't
2917 have to add SIGN_EXTEND support to print_operand_address.
2918 print_operand will just call print_operand_address in this
2919 case, so there is no problem. */
2920 ret = "la\t%0,%1";
2921 else
2922 ret = "dla\t%0,%a1";
2923 }
2924 }
2925 }
2926
2927 else if (code0 == MEM)
2928 {
2929 if (code1 == REG)
2930 {
2931 int regno1 = REGNO (op1) + subreg_offset1;
2932
2933 if (FP_REG_P (regno1))
2934 ret = "s.d\t%1,%0";
2935
2936 else if (ALL_COP_REG_P (regno1) && TARGET_64BIT)
2937 {
2938 static char retval[] = "sdc_\t%1,%0";
2939
2940 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (regno1);
2941 ret = retval;
2942 }
2943 else if (TARGET_64BIT)
2944 {
2945
2946 #ifdef TARGET_FP_CALL_32
2947 if (FP_CALL_GP_REG_P (regno1))
2948 ret = "dsll\t%1,32\n\tor\t%1,%D1\n\tsd\t%1,%0";
2949 else
2950 #endif
2951 ret = "sd\t%1,%0";
2952 }
2953
2954 else if (double_memory_operand (op0, GET_MODE (op0)))
2955 ret = "sw\t%1,%0\n\tsw\t%D1,%D0";
2956 }
2957
2958 else if (((code1 == CONST_INT && INTVAL (op1) == 0)
2959 || (code1 == CONST_DOUBLE
2960 && op1 == CONST0_RTX (GET_MODE (op1))))
2961 && (TARGET_64BIT
2962 || double_memory_operand (op0, GET_MODE (op0))))
2963 {
2964 if (TARGET_64BIT)
2965 ret = "sd\t%.,%0";
2966 else
2967 ret = "sw\t%.,%0\n\tsw\t%.,%D0";
2968 }
2969
2970 if (TARGET_STATS)
2971 mips_count_memory_refs (op0, 2);
2972
2973 if (ret != 0 && MEM_VOLATILE_P (op0))
2974 {
2975 size_t i = strlen (ret);
2976
2977 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
2978 abort ();
2979
2980 sprintf (volatile_buffer, "%%{%s%%}", ret);
2981 ret = volatile_buffer;
2982 }
2983 }
2984
2985 if (ret == 0)
2986 {
2987 abort_with_insn (insn, "bad move");
2988 return 0;
2989 }
2990
2991 if (delay != DELAY_NONE)
2992 return mips_fill_delay_slot (ret, delay, operands, insn);
2993
2994 return ret;
2995 }
2996
2997 /* Provide the costs of an addressing mode that contains ADDR.
2998 If ADDR is not a valid address, its cost is irrelevant. */
2999
3000 int
mips_address_cost(addr)3001 mips_address_cost (addr)
3002 rtx addr;
3003 {
3004 switch (GET_CODE (addr))
3005 {
3006 case LO_SUM:
3007 return 1;
3008
3009 case LABEL_REF:
3010 return 2;
3011
3012 case CONST:
3013 {
3014 rtx offset = const0_rtx;
3015 addr = eliminate_constant_term (XEXP (addr, 0), &offset);
3016 if (GET_CODE (addr) == LABEL_REF)
3017 return 2;
3018
3019 if (GET_CODE (addr) != SYMBOL_REF)
3020 return 4;
3021
3022 if (! SMALL_INT (offset))
3023 return 2;
3024 }
3025
3026 /* ... fall through ... */
3027
3028 case SYMBOL_REF:
3029 return SYMBOL_REF_FLAG (addr) ? 1 : 2;
3030
3031 case PLUS:
3032 {
3033 register rtx plus0 = XEXP (addr, 0);
3034 register rtx plus1 = XEXP (addr, 1);
3035
3036 if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG)
3037 plus0 = XEXP (addr, 1), plus1 = XEXP (addr, 0);
3038
3039 if (GET_CODE (plus0) != REG)
3040 break;
3041
3042 switch (GET_CODE (plus1))
3043 {
3044 case CONST_INT:
3045 return SMALL_INT (plus1) ? 1 : 2;
3046
3047 case CONST:
3048 case SYMBOL_REF:
3049 case LABEL_REF:
3050 case HIGH:
3051 case LO_SUM:
3052 return mips_address_cost (plus1) + 1;
3053
3054 default:
3055 break;
3056 }
3057 }
3058
3059 default:
3060 break;
3061 }
3062
3063 return 4;
3064 }
3065
3066 /* Return nonzero if X is an address which needs a temporary register when
3067 reloaded while generating PIC code. */
3068
3069 int
pic_address_needs_scratch(x)3070 pic_address_needs_scratch (x)
3071 rtx x;
3072 {
3073 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3074 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
3075 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
3076 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3077 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
3078 return 1;
3079
3080 return 0;
3081 }
3082
3083 /* Make normal rtx_code into something we can index from an array */
3084
3085 static enum internal_test
map_test_to_internal_test(test_code)3086 map_test_to_internal_test (test_code)
3087 enum rtx_code test_code;
3088 {
3089 enum internal_test test = ITEST_MAX;
3090
3091 switch (test_code)
3092 {
3093 case EQ: test = ITEST_EQ; break;
3094 case NE: test = ITEST_NE; break;
3095 case GT: test = ITEST_GT; break;
3096 case GE: test = ITEST_GE; break;
3097 case LT: test = ITEST_LT; break;
3098 case LE: test = ITEST_LE; break;
3099 case GTU: test = ITEST_GTU; break;
3100 case GEU: test = ITEST_GEU; break;
3101 case LTU: test = ITEST_LTU; break;
3102 case LEU: test = ITEST_LEU; break;
3103 default: break;
3104 }
3105
3106 return test;
3107 }
3108
3109
3110 /* Generate the code to compare two integer values. The return value is:
3111 (reg:SI xx) The pseudo register the comparison is in
3112 0 No register, generate a simple branch.
3113
3114 ??? This is called with result nonzero by the Scond patterns in
3115 mips.md. These patterns are called with a target in the mode of
3116 the Scond instruction pattern. Since this must be a constant, we
3117 must use SImode. This means that if RESULT is nonzero, it will
3118 always be an SImode register, even if TARGET_64BIT is true. We
3119 cope with this by calling convert_move rather than emit_move_insn.
3120 This will sometimes lead to an unnecessary extension of the result;
3121 for example:
3122
3123 long long
3124 foo (long long i)
3125 {
3126 return i < 5;
3127 }
3128
3129 */
3130
3131 rtx
gen_int_relational(test_code,result,cmp0,cmp1,p_invert)3132 gen_int_relational (test_code, result, cmp0, cmp1, p_invert)
3133 enum rtx_code test_code; /* relational test (EQ, etc) */
3134 rtx result; /* result to store comp. or 0 if branch */
3135 rtx cmp0; /* first operand to compare */
3136 rtx cmp1; /* second operand to compare */
3137 int *p_invert; /* NULL or ptr to hold whether branch needs */
3138 /* to reverse its test */
3139 {
3140 struct cmp_info
3141 {
3142 enum rtx_code test_code; /* code to use in instruction (LT vs. LTU) */
3143 int const_low; /* low bound of constant we can accept */
3144 int const_high; /* high bound of constant we can accept */
3145 int const_add; /* constant to add (convert LE -> LT) */
3146 int reverse_regs; /* reverse registers in test */
3147 int invert_const; /* != 0 if invert value if cmp1 is constant */
3148 int invert_reg; /* != 0 if invert value if cmp1 is register */
3149 int unsignedp; /* != 0 for unsigned comparisons. */
3150 };
3151
3152 static const struct cmp_info info[ (int)ITEST_MAX ] = {
3153
3154 { XOR, 0, 65535, 0, 0, 0, 0, 0 }, /* EQ */
3155 { XOR, 0, 65535, 0, 0, 1, 1, 0 }, /* NE */
3156 { LT, -32769, 32766, 1, 1, 1, 0, 0 }, /* GT */
3157 { LT, -32768, 32767, 0, 0, 1, 1, 0 }, /* GE */
3158 { LT, -32768, 32767, 0, 0, 0, 0, 0 }, /* LT */
3159 { LT, -32769, 32766, 1, 1, 0, 1, 0 }, /* LE */
3160 { LTU, -32769, 32766, 1, 1, 1, 0, 1 }, /* GTU */
3161 { LTU, -32768, 32767, 0, 0, 1, 1, 1 }, /* GEU */
3162 { LTU, -32768, 32767, 0, 0, 0, 0, 1 }, /* LTU */
3163 { LTU, -32769, 32766, 1, 1, 0, 1, 1 }, /* LEU */
3164 };
3165
3166 enum internal_test test;
3167 enum machine_mode mode;
3168 const struct cmp_info *p_info;
3169 int branch_p;
3170 int eqne_p;
3171 int invert;
3172 rtx reg;
3173 rtx reg2;
3174
3175 test = map_test_to_internal_test (test_code);
3176 if (test == ITEST_MAX)
3177 abort ();
3178
3179 p_info = &info[(int) test];
3180 eqne_p = (p_info->test_code == XOR);
3181
3182 mode = GET_MODE (cmp0);
3183 if (mode == VOIDmode)
3184 mode = GET_MODE (cmp1);
3185
3186 /* Eliminate simple branches */
3187 branch_p = (result == 0);
3188 if (branch_p)
3189 {
3190 if (GET_CODE (cmp0) == REG || GET_CODE (cmp0) == SUBREG)
3191 {
3192 /* Comparisons against zero are simple branches */
3193 if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0
3194 && (! TARGET_MIPS16 || eqne_p))
3195 return 0;
3196
3197 /* Test for beq/bne. */
3198 if (eqne_p && ! TARGET_MIPS16)
3199 return 0;
3200 }
3201
3202 /* allocate a pseudo to calculate the value in. */
3203 result = gen_reg_rtx (mode);
3204 }
3205
3206 /* Make sure we can handle any constants given to us. */
3207 if (GET_CODE (cmp0) == CONST_INT)
3208 cmp0 = force_reg (mode, cmp0);
3209
3210 if (GET_CODE (cmp1) == CONST_INT)
3211 {
3212 HOST_WIDE_INT value = INTVAL (cmp1);
3213
3214 if (value < p_info->const_low
3215 || value > p_info->const_high
3216 /* ??? Why? And why wasn't the similar code below modified too? */
3217 || (TARGET_64BIT
3218 && HOST_BITS_PER_WIDE_INT < 64
3219 && p_info->const_add != 0
3220 && ((p_info->unsignedp
3221 ? ((unsigned HOST_WIDE_INT) (value + p_info->const_add)
3222 > (unsigned HOST_WIDE_INT) INTVAL (cmp1))
3223 : (value + p_info->const_add) > INTVAL (cmp1))
3224 != (p_info->const_add > 0))))
3225 cmp1 = force_reg (mode, cmp1);
3226 }
3227
3228 /* See if we need to invert the result. */
3229 invert = (GET_CODE (cmp1) == CONST_INT
3230 ? p_info->invert_const : p_info->invert_reg);
3231
3232 if (p_invert != (int *)0)
3233 {
3234 *p_invert = invert;
3235 invert = 0;
3236 }
3237
3238 /* Comparison to constants, may involve adding 1 to change a LT into LE.
3239 Comparison between two registers, may involve switching operands. */
3240 if (GET_CODE (cmp1) == CONST_INT)
3241 {
3242 if (p_info->const_add != 0)
3243 {
3244 HOST_WIDE_INT new = INTVAL (cmp1) + p_info->const_add;
3245
3246 /* If modification of cmp1 caused overflow,
3247 we would get the wrong answer if we follow the usual path;
3248 thus, x > 0xffffffffU would turn into x > 0U. */
3249 if ((p_info->unsignedp
3250 ? (unsigned HOST_WIDE_INT) new >
3251 (unsigned HOST_WIDE_INT) INTVAL (cmp1)
3252 : new > INTVAL (cmp1))
3253 != (p_info->const_add > 0))
3254 {
3255 /* This test is always true, but if INVERT is true then
3256 the result of the test needs to be inverted so 0 should
3257 be returned instead. */
3258 emit_move_insn (result, invert ? const0_rtx : const_true_rtx);
3259 return result;
3260 }
3261 else
3262 cmp1 = GEN_INT (new);
3263 }
3264 }
3265
3266 else if (p_info->reverse_regs)
3267 {
3268 rtx temp = cmp0;
3269 cmp0 = cmp1;
3270 cmp1 = temp;
3271 }
3272
3273 if (test == ITEST_NE && GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0)
3274 reg = cmp0;
3275 else
3276 {
3277 reg = (invert || eqne_p) ? gen_reg_rtx (mode) : result;
3278 convert_move (reg, gen_rtx (p_info->test_code, mode, cmp0, cmp1), 0);
3279 }
3280
3281 if (test == ITEST_NE)
3282 {
3283 if (! TARGET_MIPS16)
3284 {
3285 convert_move (result, gen_rtx (GTU, mode, reg, const0_rtx), 0);
3286 if (p_invert != NULL)
3287 *p_invert = 0;
3288 invert = 0;
3289 }
3290 else
3291 {
3292 reg2 = invert ? gen_reg_rtx (mode) : result;
3293 convert_move (reg2, gen_rtx (LTU, mode, reg, const1_rtx), 0);
3294 reg = reg2;
3295 }
3296 }
3297
3298 else if (test == ITEST_EQ)
3299 {
3300 reg2 = invert ? gen_reg_rtx (mode) : result;
3301 convert_move (reg2, gen_rtx_LTU (mode, reg, const1_rtx), 0);
3302 reg = reg2;
3303 }
3304
3305 if (invert)
3306 {
3307 rtx one;
3308
3309 if (! TARGET_MIPS16)
3310 one = const1_rtx;
3311 else
3312 {
3313 /* The value is in $24. Copy it to another register, so
3314 that reload doesn't think it needs to store the $24 and
3315 the input to the XOR in the same location. */
3316 reg2 = gen_reg_rtx (mode);
3317 emit_move_insn (reg2, reg);
3318 reg = reg2;
3319 one = force_reg (mode, const1_rtx);
3320 }
3321 convert_move (result, gen_rtx (XOR, mode, reg, one), 0);
3322 }
3323
3324 return result;
3325 }
3326
3327 /* Work out how to check a floating-point condition. We need a
3328 separate comparison instruction (C.cond.fmt), followed by a
3329 branch or conditional move. Given that IN_CODE is the
3330 required condition, set *CMP_CODE to the C.cond.fmt code
3331 and *action_code to the branch or move code. */
3332
3333 static void
get_float_compare_codes(in_code,cmp_code,action_code)3334 get_float_compare_codes (in_code, cmp_code, action_code)
3335 enum rtx_code in_code, *cmp_code, *action_code;
3336 {
3337 switch (in_code)
3338 {
3339 case NE:
3340 case UNGE:
3341 case UNGT:
3342 case LTGT:
3343 case ORDERED:
3344 *cmp_code = reverse_condition_maybe_unordered (in_code);
3345 *action_code = EQ;
3346 break;
3347
3348 default:
3349 *cmp_code = in_code;
3350 *action_code = NE;
3351 break;
3352 }
3353 }
3354
3355 /* Emit the common code for doing conditional branches.
3356 operand[0] is the label to jump to.
3357 The comparison operands are saved away by cmp{si,di,sf,df}. */
3358
3359 void
gen_conditional_branch(operands,test_code)3360 gen_conditional_branch (operands, test_code)
3361 rtx operands[];
3362 enum rtx_code test_code;
3363 {
3364 enum cmp_type type = branch_type;
3365 rtx cmp0 = branch_cmp[0];
3366 rtx cmp1 = branch_cmp[1];
3367 enum machine_mode mode;
3368 enum rtx_code cmp_code;
3369 rtx reg;
3370 int invert;
3371 rtx label1, label2;
3372
3373 switch (type)
3374 {
3375 case CMP_SI:
3376 case CMP_DI:
3377 mode = type == CMP_SI ? SImode : DImode;
3378 invert = 0;
3379 reg = gen_int_relational (test_code, NULL_RTX, cmp0, cmp1, &invert);
3380
3381 if (reg)
3382 {
3383 cmp0 = reg;
3384 cmp1 = const0_rtx;
3385 test_code = NE;
3386 }
3387 else if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) != 0)
3388 /* We don't want to build a comparison against a nonzero
3389 constant. */
3390 cmp1 = force_reg (mode, cmp1);
3391
3392 break;
3393
3394 case CMP_SF:
3395 case CMP_DF:
3396 if (! ISA_HAS_8CC)
3397 reg = gen_rtx_REG (CCmode, FPSW_REGNUM);
3398 else
3399 reg = gen_reg_rtx (CCmode);
3400
3401 get_float_compare_codes (test_code, &cmp_code, &test_code);
3402 emit_insn (gen_rtx_SET (VOIDmode, reg,
3403 gen_rtx (cmp_code, CCmode, cmp0, cmp1)));
3404
3405 mode = CCmode;
3406 cmp0 = reg;
3407 cmp1 = const0_rtx;
3408 invert = 0;
3409 break;
3410
3411 default:
3412 abort_with_insn (gen_rtx (test_code, VOIDmode, cmp0, cmp1), "bad test");
3413 }
3414
3415 /* Generate the branch. */
3416
3417 label1 = gen_rtx_LABEL_REF (VOIDmode, operands[0]);
3418 label2 = pc_rtx;
3419
3420 if (invert)
3421 {
3422 label2 = label1;
3423 label1 = pc_rtx;
3424 }
3425
3426 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3427 gen_rtx_IF_THEN_ELSE (VOIDmode,
3428 gen_rtx (test_code, mode,
3429 cmp0, cmp1),
3430 label1, label2)));
3431 }
3432
3433 /* Emit the common code for conditional moves. OPERANDS is the array
3434 of operands passed to the conditional move defined_expand. */
3435
3436 void
gen_conditional_move(operands)3437 gen_conditional_move (operands)
3438 rtx *operands;
3439 {
3440 rtx op0 = branch_cmp[0];
3441 rtx op1 = branch_cmp[1];
3442 enum machine_mode mode = GET_MODE (branch_cmp[0]);
3443 enum rtx_code cmp_code = GET_CODE (operands[1]);
3444 enum rtx_code move_code = NE;
3445 enum machine_mode op_mode = GET_MODE (operands[0]);
3446 enum machine_mode cmp_mode;
3447 rtx cmp_reg;
3448
3449 if (GET_MODE_CLASS (mode) != MODE_FLOAT)
3450 {
3451 switch (cmp_code)
3452 {
3453 case EQ:
3454 cmp_code = XOR;
3455 move_code = EQ;
3456 break;
3457 case NE:
3458 cmp_code = XOR;
3459 break;
3460 case LT:
3461 break;
3462 case GE:
3463 cmp_code = LT;
3464 move_code = EQ;
3465 break;
3466 case GT:
3467 cmp_code = LT;
3468 op0 = force_reg (mode, branch_cmp[1]);
3469 op1 = branch_cmp[0];
3470 break;
3471 case LE:
3472 cmp_code = LT;
3473 op0 = force_reg (mode, branch_cmp[1]);
3474 op1 = branch_cmp[0];
3475 move_code = EQ;
3476 break;
3477 case LTU:
3478 break;
3479 case GEU:
3480 cmp_code = LTU;
3481 move_code = EQ;
3482 break;
3483 case GTU:
3484 cmp_code = LTU;
3485 op0 = force_reg (mode, branch_cmp[1]);
3486 op1 = branch_cmp[0];
3487 break;
3488 case LEU:
3489 cmp_code = LTU;
3490 op0 = force_reg (mode, branch_cmp[1]);
3491 op1 = branch_cmp[0];
3492 move_code = EQ;
3493 break;
3494 default:
3495 abort ();
3496 }
3497 }
3498 else
3499 get_float_compare_codes (cmp_code, &cmp_code, &move_code);
3500
3501 if (mode == SImode || mode == DImode)
3502 cmp_mode = mode;
3503 else if (mode == SFmode || mode == DFmode)
3504 cmp_mode = CCmode;
3505 else
3506 abort ();
3507
3508 cmp_reg = gen_reg_rtx (cmp_mode);
3509 emit_insn (gen_rtx_SET (cmp_mode, cmp_reg,
3510 gen_rtx (cmp_code, cmp_mode, op0, op1)));
3511
3512 emit_insn (gen_rtx_SET (op_mode, operands[0],
3513 gen_rtx_IF_THEN_ELSE (op_mode,
3514 gen_rtx (move_code, VOIDmode,
3515 cmp_reg,
3516 CONST0_RTX (SImode)),
3517 operands[2], operands[3])));
3518 }
3519
3520 /* Emit the common code for conditional moves. OPERANDS is the array
3521 of operands passed to the conditional move defined_expand. */
3522
3523 void
mips_gen_conditional_trap(operands)3524 mips_gen_conditional_trap (operands)
3525 rtx operands[];
3526 {
3527 rtx op0, op1;
3528 enum rtx_code cmp_code = GET_CODE (operands[0]);
3529 enum machine_mode mode = GET_MODE (branch_cmp[0]);
3530
3531 /* MIPS conditional trap machine instructions don't have GT or LE
3532 flavors, so we must invert the comparison and convert to LT and
3533 GE, respectively. */
3534 switch (cmp_code)
3535 {
3536 case GT: cmp_code = LT; break;
3537 case LE: cmp_code = GE; break;
3538 case GTU: cmp_code = LTU; break;
3539 case LEU: cmp_code = GEU; break;
3540 default: break;
3541 }
3542 if (cmp_code == GET_CODE (operands[0]))
3543 {
3544 op0 = force_reg (mode, branch_cmp[0]);
3545 op1 = branch_cmp[1];
3546 }
3547 else
3548 {
3549 op0 = force_reg (mode, branch_cmp[1]);
3550 op1 = branch_cmp[0];
3551 }
3552 if (GET_CODE (op1) == CONST_INT && ! SMALL_INT (op1))
3553 op1 = force_reg (mode, op1);
3554
3555 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
3556 gen_rtx (cmp_code, GET_MODE (operands[0]), op0, op1),
3557 operands[1]));
3558 }
3559
3560 /* Return true if operand OP is a condition code register.
3561 Only for use during or after reload. */
3562
3563 int
fcc_register_operand(op,mode)3564 fcc_register_operand (op, mode)
3565 rtx op;
3566 enum machine_mode mode;
3567 {
3568 return ((mode == VOIDmode || mode == GET_MODE (op))
3569 && (reload_in_progress || reload_completed)
3570 && (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
3571 && ST_REG_P (true_regnum (op)));
3572 }
3573
3574 /* Emit code to move general operand SRC into condition-code
3575 register DEST. SCRATCH is a scratch TFmode float register.
3576 The sequence is:
3577
3578 FP1 = SRC
3579 FP2 = 0.0f
3580 DEST = FP2 < FP1
3581
3582 where FP1 and FP2 are single-precision float registers
3583 taken from SCRATCH. */
3584
3585 void
mips_emit_fcc_reload(dest,src,scratch)3586 mips_emit_fcc_reload (dest, src, scratch)
3587 rtx dest, src, scratch;
3588 {
3589 rtx fp1, fp2;
3590
3591 /* Change the source to SFmode. */
3592 if (GET_CODE (src) == MEM)
3593 src = adjust_address (src, SFmode, 0);
3594 else if (GET_CODE (src) == REG || GET_CODE (src) == SUBREG)
3595 src = gen_rtx_REG (SFmode, true_regnum (src));
3596
3597 fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
3598 fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + FP_INC);
3599
3600 emit_move_insn (copy_rtx (fp1), src);
3601 emit_move_insn (copy_rtx (fp2), CONST0_RTX (SFmode));
3602 emit_insn (gen_slt_sf (dest, fp2, fp1));
3603 }
3604
3605 /* Emit code to change the current function's return address to
3606 ADDRESS. SCRATCH is available as a scratch register, if needed.
3607 ADDRESS and SCRATCH are both word-mode GPRs. */
3608
3609 void
mips_set_return_address(address,scratch)3610 mips_set_return_address (address, scratch)
3611 rtx address, scratch;
3612 {
3613 HOST_WIDE_INT gp_offset;
3614
3615 compute_frame_size (get_frame_size ());
3616 if (((cfun->machine->frame.mask >> 31) & 1) == 0)
3617 abort ();
3618 gp_offset = cfun->machine->frame.gp_sp_offset;
3619
3620 /* Reduce SP + GP_OFSET to a legitimate address and put it in SCRATCH. */
3621 if (gp_offset < 32768)
3622 scratch = plus_constant (stack_pointer_rtx, gp_offset);
3623 else
3624 {
3625 emit_move_insn (scratch, GEN_INT (gp_offset));
3626 if (Pmode == DImode)
3627 emit_insn (gen_adddi3 (scratch, scratch, stack_pointer_rtx));
3628 else
3629 emit_insn (gen_addsi3 (scratch, scratch, stack_pointer_rtx));
3630 }
3631
3632 emit_move_insn (gen_rtx_MEM (GET_MODE (address), scratch), address);
3633 }
3634
3635 /* Write a loop to move a constant number of bytes.
3636 Generate load/stores as follows:
3637
3638 do {
3639 temp1 = src[0];
3640 temp2 = src[1];
3641 ...
3642 temp<last> = src[MAX_MOVE_REGS-1];
3643 dest[0] = temp1;
3644 dest[1] = temp2;
3645 ...
3646 dest[MAX_MOVE_REGS-1] = temp<last>;
3647 src += MAX_MOVE_REGS;
3648 dest += MAX_MOVE_REGS;
3649 } while (src != final);
3650
3651 This way, no NOP's are needed, and only MAX_MOVE_REGS+3 temp
3652 registers are needed.
3653
3654 Aligned moves move MAX_MOVE_REGS*4 bytes every (2*MAX_MOVE_REGS)+3
3655 cycles, unaligned moves move MAX_MOVE_REGS*4 bytes every
3656 (4*MAX_MOVE_REGS)+3 cycles, assuming no cache misses. */
3657
3658 #define MAX_MOVE_REGS 4
3659 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
3660
3661 static void
block_move_loop(dest_reg,src_reg,bytes,align,orig_dest,orig_src)3662 block_move_loop (dest_reg, src_reg, bytes, align, orig_dest, orig_src)
3663 rtx dest_reg; /* register holding destination address */
3664 rtx src_reg; /* register holding source address */
3665 unsigned int bytes; /* # bytes to move */
3666 int align; /* alignment */
3667 rtx orig_dest; /* original dest */
3668 rtx orig_src; /* original source for making a reg note */
3669 {
3670 rtx dest_mem = replace_equiv_address (orig_dest, dest_reg);
3671 rtx src_mem = replace_equiv_address (orig_src, src_reg);
3672 rtx align_rtx = GEN_INT (align);
3673 rtx label;
3674 rtx final_src;
3675 rtx bytes_rtx;
3676 int leftover;
3677
3678 if (bytes < (unsigned)2 * MAX_MOVE_BYTES)
3679 abort ();
3680
3681 leftover = bytes % MAX_MOVE_BYTES;
3682 bytes -= leftover;
3683
3684 label = gen_label_rtx ();
3685 final_src = gen_reg_rtx (Pmode);
3686 bytes_rtx = GEN_INT (bytes);
3687
3688 if (bytes > 0x7fff)
3689 {
3690 if (Pmode == DImode)
3691 {
3692 emit_insn (gen_movdi (final_src, bytes_rtx));
3693 emit_insn (gen_adddi3 (final_src, final_src, src_reg));
3694 }
3695 else
3696 {
3697 emit_insn (gen_movsi (final_src, bytes_rtx));
3698 emit_insn (gen_addsi3 (final_src, final_src, src_reg));
3699 }
3700 }
3701 else
3702 {
3703 if (Pmode == DImode)
3704 emit_insn (gen_adddi3 (final_src, src_reg, bytes_rtx));
3705 else
3706 emit_insn (gen_addsi3 (final_src, src_reg, bytes_rtx));
3707 }
3708
3709 emit_label (label);
3710
3711 bytes_rtx = GEN_INT (MAX_MOVE_BYTES);
3712 emit_insn (gen_movstrsi_internal (dest_mem, src_mem, bytes_rtx, align_rtx));
3713
3714 if (Pmode == DImode)
3715 {
3716 emit_insn (gen_adddi3 (src_reg, src_reg, bytes_rtx));
3717 emit_insn (gen_adddi3 (dest_reg, dest_reg, bytes_rtx));
3718 emit_insn (gen_cmpdi (src_reg, final_src));
3719 }
3720 else
3721 {
3722 emit_insn (gen_addsi3 (src_reg, src_reg, bytes_rtx));
3723 emit_insn (gen_addsi3 (dest_reg, dest_reg, bytes_rtx));
3724 emit_insn (gen_cmpsi (src_reg, final_src));
3725 }
3726
3727 emit_jump_insn (gen_bne (label));
3728
3729 if (leftover)
3730 emit_insn (gen_movstrsi_internal (dest_mem, src_mem, GEN_INT (leftover),
3731 align_rtx));
3732 }
3733
3734 /* Use a library function to move some bytes. */
3735
3736 static void
block_move_call(dest_reg,src_reg,bytes_rtx)3737 block_move_call (dest_reg, src_reg, bytes_rtx)
3738 rtx dest_reg;
3739 rtx src_reg;
3740 rtx bytes_rtx;
3741 {
3742 /* We want to pass the size as Pmode, which will normally be SImode
3743 but will be DImode if we are using 64 bit longs and pointers. */
3744 if (GET_MODE (bytes_rtx) != VOIDmode
3745 && GET_MODE (bytes_rtx) != (unsigned) Pmode)
3746 bytes_rtx = convert_to_mode (Pmode, bytes_rtx, 1);
3747
3748 #ifdef TARGET_MEM_FUNCTIONS
3749 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "memcpy"), 0,
3750 VOIDmode, 3, dest_reg, Pmode, src_reg, Pmode,
3751 convert_to_mode (TYPE_MODE (sizetype), bytes_rtx,
3752 TREE_UNSIGNED (sizetype)),
3753 TYPE_MODE (sizetype));
3754 #else
3755 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "bcopy"), 0,
3756 VOIDmode, 3, src_reg, Pmode, dest_reg, Pmode,
3757 convert_to_mode (TYPE_MODE (integer_type_node), bytes_rtx,
3758 TREE_UNSIGNED (integer_type_node)),
3759 TYPE_MODE (integer_type_node));
3760 #endif
3761 }
3762
3763 /* Expand string/block move operations.
3764
3765 operands[0] is the pointer to the destination.
3766 operands[1] is the pointer to the source.
3767 operands[2] is the number of bytes to move.
3768 operands[3] is the alignment. */
3769
3770 void
expand_block_move(operands)3771 expand_block_move (operands)
3772 rtx operands[];
3773 {
3774 rtx bytes_rtx = operands[2];
3775 rtx align_rtx = operands[3];
3776 int constp = GET_CODE (bytes_rtx) == CONST_INT;
3777 unsigned HOST_WIDE_INT bytes = constp ? INTVAL (bytes_rtx) : 0;
3778 unsigned int align = INTVAL (align_rtx);
3779 rtx orig_src = operands[1];
3780 rtx orig_dest = operands[0];
3781 rtx src_reg;
3782 rtx dest_reg;
3783
3784 if (constp && bytes == 0)
3785 return;
3786
3787 if (align > (unsigned) UNITS_PER_WORD)
3788 align = UNITS_PER_WORD;
3789
3790 /* Move the address into scratch registers. */
3791 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
3792 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
3793
3794 if (TARGET_MEMCPY)
3795 block_move_call (dest_reg, src_reg, bytes_rtx);
3796
3797 else if (constp && bytes <= (unsigned)2 * MAX_MOVE_BYTES
3798 && align == (unsigned) UNITS_PER_WORD)
3799 move_by_pieces (orig_dest, orig_src, bytes, align * BITS_PER_WORD);
3800
3801 else if (constp && bytes <= (unsigned)2 * MAX_MOVE_BYTES)
3802 emit_insn (gen_movstrsi_internal (replace_equiv_address (orig_dest,
3803 dest_reg),
3804 replace_equiv_address (orig_src,
3805 src_reg),
3806 bytes_rtx, align_rtx));
3807
3808 else if (constp && align >= (unsigned) UNITS_PER_WORD && optimize)
3809 block_move_loop (dest_reg, src_reg, bytes, align, orig_dest, orig_src);
3810
3811 else if (constp && optimize)
3812 {
3813 /* If the alignment is not word aligned, generate a test at
3814 runtime, to see whether things wound up aligned, and we
3815 can use the faster lw/sw instead ulw/usw. */
3816
3817 rtx temp = gen_reg_rtx (Pmode);
3818 rtx aligned_label = gen_label_rtx ();
3819 rtx join_label = gen_label_rtx ();
3820 int leftover = bytes % MAX_MOVE_BYTES;
3821
3822 bytes -= leftover;
3823
3824 if (Pmode == DImode)
3825 {
3826 emit_insn (gen_iordi3 (temp, src_reg, dest_reg));
3827 emit_insn (gen_anddi3 (temp, temp, GEN_INT (UNITS_PER_WORD - 1)));
3828 emit_insn (gen_cmpdi (temp, const0_rtx));
3829 }
3830 else
3831 {
3832 emit_insn (gen_iorsi3 (temp, src_reg, dest_reg));
3833 emit_insn (gen_andsi3 (temp, temp, GEN_INT (UNITS_PER_WORD - 1)));
3834 emit_insn (gen_cmpsi (temp, const0_rtx));
3835 }
3836
3837 emit_jump_insn (gen_beq (aligned_label));
3838
3839 /* Unaligned loop. */
3840 block_move_loop (dest_reg, src_reg, bytes, 1, orig_dest, orig_src);
3841 emit_jump_insn (gen_jump (join_label));
3842 emit_barrier ();
3843
3844 /* Aligned loop. */
3845 emit_label (aligned_label);
3846 block_move_loop (dest_reg, src_reg, bytes, UNITS_PER_WORD, orig_dest,
3847 orig_src);
3848 emit_label (join_label);
3849
3850 /* Bytes at the end of the loop. */
3851 if (leftover)
3852 emit_insn (gen_movstrsi_internal (replace_equiv_address (orig_dest,
3853 dest_reg),
3854 replace_equiv_address (orig_src,
3855 src_reg),
3856 GEN_INT (leftover),
3857 GEN_INT (align)));
3858 }
3859
3860 else
3861 block_move_call (dest_reg, src_reg, bytes_rtx);
3862 }
3863
3864 /* Emit load/stores for a small constant block_move.
3865
3866 operands[0] is the memory address of the destination.
3867 operands[1] is the memory address of the source.
3868 operands[2] is the number of bytes to move.
3869 operands[3] is the alignment.
3870 operands[4] is a temp register.
3871 operands[5] is a temp register.
3872 ...
3873 operands[3+num_regs] is the last temp register.
3874
3875 The block move type can be one of the following:
3876 BLOCK_MOVE_NORMAL Do all of the block move.
3877 BLOCK_MOVE_NOT_LAST Do all but the last store.
3878 BLOCK_MOVE_LAST Do just the last store. */
3879
3880 const char *
output_block_move(insn,operands,num_regs,move_type)3881 output_block_move (insn, operands, num_regs, move_type)
3882 rtx insn;
3883 rtx operands[];
3884 int num_regs;
3885 enum block_move_type move_type;
3886 {
3887 rtx dest_reg = XEXP (operands[0], 0);
3888 rtx src_reg = XEXP (operands[1], 0);
3889 HOST_WIDE_INT bytes = INTVAL (operands[2]);
3890 int align = INTVAL (operands[3]);
3891 int num = 0;
3892 int offset = 0;
3893 int use_lwl_lwr = 0;
3894 int last_operand = num_regs + 4;
3895 int safe_regs = 4;
3896 int i;
3897 rtx xoperands[10];
3898
3899 struct {
3900 const char *load; /* load insn without nop */
3901 const char *load_nop; /* load insn with trailing nop */
3902 const char *store; /* store insn */
3903 const char *final; /* if last_store used: NULL or swr */
3904 const char *last_store; /* last store instruction */
3905 int offset; /* current offset */
3906 enum machine_mode mode; /* mode to use on (MEM) */
3907 } load_store[4];
3908
3909 /* ??? Detect a bug in GCC, where it can give us a register
3910 the same as one of the addressing registers and reduce
3911 the number of registers available. */
3912 for (i = 4; i < last_operand && safe_regs < (int) ARRAY_SIZE (xoperands); i++)
3913 if (! reg_mentioned_p (operands[i], operands[0])
3914 && ! reg_mentioned_p (operands[i], operands[1]))
3915 xoperands[safe_regs++] = operands[i];
3916
3917 if (safe_regs < last_operand)
3918 {
3919 xoperands[0] = operands[0];
3920 xoperands[1] = operands[1];
3921 xoperands[2] = operands[2];
3922 xoperands[3] = operands[3];
3923 return output_block_move (insn, xoperands, safe_regs - 4, move_type);
3924 }
3925
3926 /* If we are given global or static addresses, and we would be
3927 emitting a few instructions, try to save time by using a
3928 temporary register for the pointer. */
3929 /* ??? The SGI Irix6 assembler fails when a SYMBOL_REF is used in
3930 an ldl/ldr instruction pair. We play it safe, and always move
3931 constant addresses into registers when generating N32/N64 code, just
3932 in case we might emit an unaligned load instruction. */
3933 if (num_regs > 2 && (bytes > 2 * align || move_type != BLOCK_MOVE_NORMAL
3934 || mips_abi == ABI_MEABI
3935 || mips_abi == ABI_N32
3936 || mips_abi == ABI_64))
3937 {
3938 if (CONSTANT_P (src_reg))
3939 {
3940 if (TARGET_STATS)
3941 mips_count_memory_refs (operands[1], 1);
3942
3943 src_reg = operands[3 + num_regs--];
3944 if (move_type != BLOCK_MOVE_LAST)
3945 {
3946 xoperands[1] = operands[1];
3947 xoperands[0] = src_reg;
3948 if (Pmode == DImode)
3949 output_asm_insn ("dla\t%0,%1", xoperands);
3950 else
3951 output_asm_insn ("la\t%0,%1", xoperands);
3952 }
3953 }
3954
3955 if (CONSTANT_P (dest_reg))
3956 {
3957 if (TARGET_STATS)
3958 mips_count_memory_refs (operands[0], 1);
3959
3960 dest_reg = operands[3 + num_regs--];
3961 if (move_type != BLOCK_MOVE_LAST)
3962 {
3963 xoperands[1] = operands[0];
3964 xoperands[0] = dest_reg;
3965 if (Pmode == DImode)
3966 output_asm_insn ("dla\t%0,%1", xoperands);
3967 else
3968 output_asm_insn ("la\t%0,%1", xoperands);
3969 }
3970 }
3971 }
3972
3973 /* ??? We really shouldn't get any LO_SUM addresses here, because they
3974 are not offsettable, however, offsettable_address_p says they are
3975 offsettable. I think this is a bug in offsettable_address_p.
3976 For expediency, we fix this by just loading the address into a register
3977 if we happen to get one. */
3978
3979 if (GET_CODE (src_reg) == LO_SUM)
3980 {
3981 src_reg = operands[3 + num_regs--];
3982 if (move_type != BLOCK_MOVE_LAST)
3983 {
3984 xoperands[2] = XEXP (XEXP (operands[1], 0), 1);
3985 xoperands[1] = XEXP (XEXP (operands[1], 0), 0);
3986 xoperands[0] = src_reg;
3987 if (Pmode == DImode)
3988 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands);
3989 else
3990 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands);
3991 }
3992 }
3993
3994 if (GET_CODE (dest_reg) == LO_SUM)
3995 {
3996 dest_reg = operands[3 + num_regs--];
3997 if (move_type != BLOCK_MOVE_LAST)
3998 {
3999 xoperands[2] = XEXP (XEXP (operands[0], 0), 1);
4000 xoperands[1] = XEXP (XEXP (operands[0], 0), 0);
4001 xoperands[0] = dest_reg;
4002 if (Pmode == DImode)
4003 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands);
4004 else
4005 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands);
4006 }
4007 }
4008
4009 if (num_regs > (int) ARRAY_SIZE (load_store))
4010 num_regs = ARRAY_SIZE (load_store);
4011
4012 else if (num_regs < 1)
4013 abort_with_insn (insn,
4014 "cannot do block move, not enough scratch registers");
4015
4016 while (bytes > 0)
4017 {
4018 load_store[num].offset = offset;
4019
4020 if (TARGET_64BIT && bytes >= 8 && align >= 8)
4021 {
4022 load_store[num].load = "ld\t%0,%1";
4023 load_store[num].load_nop = "ld\t%0,%1%#";
4024 load_store[num].store = "sd\t%0,%1";
4025 load_store[num].last_store = "sd\t%0,%1";
4026 load_store[num].final = 0;
4027 load_store[num].mode = DImode;
4028 offset += 8;
4029 bytes -= 8;
4030 }
4031
4032 /* ??? Fails because of a MIPS assembler bug? */
4033 else if (TARGET_64BIT && bytes >= 8
4034 && ! TARGET_SR71K
4035 && ! TARGET_MIPS16)
4036 {
4037 if (BYTES_BIG_ENDIAN)
4038 {
4039 load_store[num].load = "ldl\t%0,%1\n\tldr\t%0,%2";
4040 load_store[num].load_nop = "ldl\t%0,%1\n\tldr\t%0,%2%#";
4041 load_store[num].store = "sdl\t%0,%1\n\tsdr\t%0,%2";
4042 load_store[num].last_store = "sdr\t%0,%2";
4043 load_store[num].final = "sdl\t%0,%1";
4044 }
4045 else
4046 {
4047 load_store[num].load = "ldl\t%0,%2\n\tldr\t%0,%1";
4048 load_store[num].load_nop = "ldl\t%0,%2\n\tldr\t%0,%1%#";
4049 load_store[num].store = "sdl\t%0,%2\n\tsdr\t%0,%1";
4050 load_store[num].last_store = "sdr\t%0,%1";
4051 load_store[num].final = "sdl\t%0,%2";
4052 }
4053
4054 load_store[num].mode = DImode;
4055 offset += 8;
4056 bytes -= 8;
4057 use_lwl_lwr = 1;
4058 }
4059
4060 else if (bytes >= 4 && align >= 4)
4061 {
4062 load_store[num].load = "lw\t%0,%1";
4063 load_store[num].load_nop = "lw\t%0,%1%#";
4064 load_store[num].store = "sw\t%0,%1";
4065 load_store[num].last_store = "sw\t%0,%1";
4066 load_store[num].final = 0;
4067 load_store[num].mode = SImode;
4068 offset += 4;
4069 bytes -= 4;
4070 }
4071
4072 else if (bytes >= 4
4073 && ! TARGET_SR71K
4074 && ! TARGET_MIPS16)
4075 {
4076 if (BYTES_BIG_ENDIAN)
4077 {
4078 load_store[num].load = "lwl\t%0,%1\n\tlwr\t%0,%2";
4079 load_store[num].load_nop = "lwl\t%0,%1\n\tlwr\t%0,%2%#";
4080 load_store[num].store = "swl\t%0,%1\n\tswr\t%0,%2";
4081 load_store[num].last_store = "swr\t%0,%2";
4082 load_store[num].final = "swl\t%0,%1";
4083 }
4084 else
4085 {
4086 load_store[num].load = "lwl\t%0,%2\n\tlwr\t%0,%1";
4087 load_store[num].load_nop = "lwl\t%0,%2\n\tlwr\t%0,%1%#";
4088 load_store[num].store = "swl\t%0,%2\n\tswr\t%0,%1";
4089 load_store[num].last_store = "swr\t%0,%1";
4090 load_store[num].final = "swl\t%0,%2";
4091 }
4092
4093 load_store[num].mode = SImode;
4094 offset += 4;
4095 bytes -= 4;
4096 use_lwl_lwr = 1;
4097 }
4098
4099 else if (bytes >= 2 && align >= 2)
4100 {
4101 load_store[num].load = "lh\t%0,%1";
4102 load_store[num].load_nop = "lh\t%0,%1%#";
4103 load_store[num].store = "sh\t%0,%1";
4104 load_store[num].last_store = "sh\t%0,%1";
4105 load_store[num].final = 0;
4106 load_store[num].mode = HImode;
4107 offset += 2;
4108 bytes -= 2;
4109 }
4110 else
4111 {
4112 load_store[num].load = "lb\t%0,%1";
4113 load_store[num].load_nop = "lb\t%0,%1%#";
4114 load_store[num].store = "sb\t%0,%1";
4115 load_store[num].last_store = "sb\t%0,%1";
4116 load_store[num].final = 0;
4117 load_store[num].mode = QImode;
4118 offset++;
4119 bytes--;
4120 }
4121
4122 if (TARGET_STATS && move_type != BLOCK_MOVE_LAST)
4123 {
4124 dslots_load_total++;
4125 dslots_load_filled++;
4126
4127 if (CONSTANT_P (src_reg))
4128 mips_count_memory_refs (src_reg, 1);
4129
4130 if (CONSTANT_P (dest_reg))
4131 mips_count_memory_refs (dest_reg, 1);
4132 }
4133
4134 /* Emit load/stores now if we have run out of registers or are
4135 at the end of the move. */
4136
4137 if (++num == num_regs || bytes == 0)
4138 {
4139 /* If only load/store, we need a NOP after the load. */
4140 if (num == 1)
4141 {
4142 load_store[0].load = load_store[0].load_nop;
4143 if (TARGET_STATS && move_type != BLOCK_MOVE_LAST)
4144 dslots_load_filled--;
4145 }
4146
4147 if (move_type != BLOCK_MOVE_LAST)
4148 {
4149 for (i = 0; i < num; i++)
4150 {
4151 int offset;
4152
4153 if (!operands[i + 4])
4154 abort ();
4155
4156 if (GET_MODE (operands[i + 4]) != load_store[i].mode)
4157 operands[i + 4] = gen_rtx_REG (load_store[i].mode,
4158 REGNO (operands[i + 4]));
4159
4160 offset = load_store[i].offset;
4161 xoperands[0] = operands[i + 4];
4162 xoperands[1] = gen_rtx_MEM (load_store[i].mode,
4163 plus_constant (src_reg, offset));
4164
4165 if (use_lwl_lwr)
4166 {
4167 int extra_offset
4168 = GET_MODE_SIZE (load_store[i].mode) - 1;
4169
4170 xoperands[2] = gen_rtx_MEM (load_store[i].mode,
4171 plus_constant (src_reg,
4172 extra_offset
4173 + offset));
4174 }
4175
4176 output_asm_insn (load_store[i].load, xoperands);
4177 }
4178 }
4179
4180 for (i = 0; i < num; i++)
4181 {
4182 int last_p = (i == num-1 && bytes == 0);
4183 int offset = load_store[i].offset;
4184
4185 xoperands[0] = operands[i + 4];
4186 xoperands[1] = gen_rtx_MEM (load_store[i].mode,
4187 plus_constant (dest_reg, offset));
4188
4189
4190 if (use_lwl_lwr)
4191 {
4192 int extra_offset = GET_MODE_SIZE (load_store[i].mode) - 1;
4193 xoperands[2] = gen_rtx_MEM (load_store[i].mode,
4194 plus_constant (dest_reg,
4195 extra_offset
4196 + offset));
4197 }
4198
4199 if (move_type == BLOCK_MOVE_NORMAL)
4200 output_asm_insn (load_store[i].store, xoperands);
4201
4202 else if (move_type == BLOCK_MOVE_NOT_LAST)
4203 {
4204 if (!last_p)
4205 output_asm_insn (load_store[i].store, xoperands);
4206
4207 else if (load_store[i].final != 0)
4208 output_asm_insn (load_store[i].final, xoperands);
4209 }
4210
4211 else if (last_p)
4212 output_asm_insn (load_store[i].last_store, xoperands);
4213 }
4214
4215 num = 0; /* reset load_store */
4216 use_lwl_lwr = 0;
4217 }
4218 }
4219
4220 return "";
4221 }
4222
4223 /* Argument support functions. */
4224
4225 /* Initialize CUMULATIVE_ARGS for a function. */
4226
4227 void
init_cumulative_args(cum,fntype,libname)4228 init_cumulative_args (cum, fntype, libname)
4229 CUMULATIVE_ARGS *cum; /* argument info to initialize */
4230 tree fntype; /* tree ptr for function decl */
4231 rtx libname ATTRIBUTE_UNUSED; /* SYMBOL_REF of library name or 0 */
4232 {
4233 static CUMULATIVE_ARGS zero_cum;
4234 tree param, next_param;
4235
4236 if (TARGET_DEBUG_E_MODE)
4237 {
4238 fprintf (stderr,
4239 "\ninit_cumulative_args, fntype = 0x%.8lx", (long)fntype);
4240
4241 if (!fntype)
4242 fputc ('\n', stderr);
4243
4244 else
4245 {
4246 tree ret_type = TREE_TYPE (fntype);
4247 fprintf (stderr, ", fntype code = %s, ret code = %s\n",
4248 tree_code_name[(int)TREE_CODE (fntype)],
4249 tree_code_name[(int)TREE_CODE (ret_type)]);
4250 }
4251 }
4252
4253 *cum = zero_cum;
4254 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
4255
4256 /* Determine if this function has variable arguments. This is
4257 indicated by the last argument being 'void_type_mode' if there
4258 are no variable arguments. The standard MIPS calling sequence
4259 passes all arguments in the general purpose registers in this case. */
4260
4261 for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0;
4262 param != 0; param = next_param)
4263 {
4264 next_param = TREE_CHAIN (param);
4265 if (next_param == 0 && TREE_VALUE (param) != void_type_node)
4266 cum->gp_reg_found = 1;
4267 }
4268 }
4269
4270 static void
mips_arg_info(cum,mode,type,named,info)4271 mips_arg_info (cum, mode, type, named, info)
4272 const CUMULATIVE_ARGS *cum;
4273 enum machine_mode mode;
4274 tree type;
4275 int named;
4276 struct mips_arg_info *info;
4277 {
4278 bool even_reg_p;
4279 unsigned int num_words, max_regs;
4280
4281 info->struct_p = (type != 0
4282 && (TREE_CODE (type) == RECORD_TYPE
4283 || TREE_CODE (type) == UNION_TYPE
4284 || TREE_CODE (type) == QUAL_UNION_TYPE));
4285
4286 /* Decide whether this argument should go in a floating-point register,
4287 assuming one is free. Later code checks for availablity. */
4288
4289 info->fpr_p = false;
4290 if (GET_MODE_CLASS (mode) == MODE_FLOAT
4291 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE)
4292 {
4293 switch (mips_abi)
4294 {
4295 case ABI_32:
4296 case ABI_O64:
4297 info->fpr_p = (!cum->gp_reg_found && cum->arg_number < 2);
4298 break;
4299
4300 case ABI_EABI:
4301 info->fpr_p = true;
4302 break;
4303
4304 case ABI_MEABI:
4305 /* The MIPS eabi says only structures containing doubles get
4306 passed in a fp register, so force a structure containing
4307 a float to be passed in the integer registers. */
4308 info->fpr_p = (named && !(mode == SFmode && info->struct_p));
4309 break;
4310
4311 default:
4312 info->fpr_p = named;
4313 break;
4314 }
4315 }
4316
4317 /* Now decide whether the argument must go in an even-numbered register. */
4318
4319 even_reg_p = false;
4320 if (info->fpr_p)
4321 {
4322 /* Under the O64 ABI, the second float argument goes in $f13 if it
4323 is a double, but $f14 if it is a single. Otherwise, on a
4324 32-bit double-float machine, each FP argument must start in a
4325 new register pair. */
4326 even_reg_p = (GET_MODE_SIZE (mode) > UNITS_PER_HWFPVALUE
4327 || (mips_abi == ABI_O64 && mode == SFmode)
4328 || FP_INC > 1);
4329 }
4330 else if (!TARGET_64BIT || LONG_DOUBLE_TYPE_SIZE == 128)
4331 {
4332 if (GET_MODE_CLASS (mode) == MODE_INT
4333 || GET_MODE_CLASS (mode) == MODE_FLOAT)
4334 even_reg_p = (GET_MODE_SIZE (mode) > UNITS_PER_WORD);
4335
4336 else if (type != NULL_TREE && TYPE_ALIGN (type) > BITS_PER_WORD)
4337 even_reg_p = true;
4338 }
4339
4340 /* Set REG_OFFSET to the register count we're interested in.
4341 The EABI allocates the floating-point registers separately,
4342 but the other ABIs allocate them like integer registers. */
4343 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
4344 ? cum->num_fprs
4345 : cum->num_gprs);
4346
4347 if (even_reg_p)
4348 info->reg_offset += info->reg_offset & 1;
4349
4350 /* The alignment applied to registers is also applied to stack arguments. */
4351 info->stack_offset = cum->stack_words;
4352 if (even_reg_p)
4353 info->stack_offset += info->stack_offset & 1;
4354
4355 if (mode == BLKmode)
4356 info->num_bytes = int_size_in_bytes (type);
4357 else
4358 info->num_bytes = GET_MODE_SIZE (mode);
4359
4360 num_words = (info->num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4361 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
4362
4363 /* Partition the argument between registers and stack. */
4364 info->reg_words = MIN (num_words, max_regs);
4365 info->stack_words = num_words - info->reg_words;
4366 }
4367
4368
4369 /* Advance the argument to the next argument position. */
4370
4371 void
function_arg_advance(cum,mode,type,named)4372 function_arg_advance (cum, mode, type, named)
4373 CUMULATIVE_ARGS *cum; /* current arg information */
4374 enum machine_mode mode; /* current arg mode */
4375 tree type; /* type of the argument or 0 if lib support */
4376 int named; /* whether or not the argument was named */
4377 {
4378 struct mips_arg_info info;
4379
4380 mips_arg_info (cum, mode, type, named, &info);
4381
4382 /* The following is a hack in order to pass 1 byte structures
4383 the same way that the MIPS compiler does (namely by passing
4384 the structure in the high byte or half word of the register).
4385 This also makes varargs work. If we have such a structure,
4386 we save the adjustment RTL, and the call define expands will
4387 emit them. For the VOIDmode argument (argument after the
4388 last real argument), pass back a parallel vector holding each
4389 of the adjustments. */
4390
4391 /* ??? This scheme requires everything smaller than the word size to
4392 shifted to the left, but when TARGET_64BIT and ! TARGET_INT64,
4393 that would mean every int needs to be shifted left, which is very
4394 inefficient. Let's not carry this compatibility to the 64 bit
4395 calling convention for now. */
4396
4397 if (info.struct_p
4398 && info.reg_words == 1
4399 && info.num_bytes < UNITS_PER_WORD
4400 && !TARGET_64BIT
4401 && mips_abi != ABI_EABI
4402 && mips_abi != ABI_MEABI)
4403 {
4404 rtx amount = GEN_INT (BITS_PER_WORD - info.num_bytes * BITS_PER_UNIT);
4405 rtx reg = gen_rtx_REG (word_mode, GP_ARG_FIRST + info.reg_offset);
4406
4407 if (TARGET_64BIT)
4408 cum->adjust[cum->num_adjusts++] = PATTERN (gen_ashldi3 (reg, reg, amount));
4409 else
4410 cum->adjust[cum->num_adjusts++] = PATTERN (gen_ashlsi3 (reg, reg, amount));
4411 }
4412
4413 if (!info.fpr_p)
4414 cum->gp_reg_found = true;
4415
4416 /* See the comment above the cumulative args structure in mips.h
4417 for an explanation of what this code does. It assumes the O32
4418 ABI, which passes at most 2 arguments in float registers. */
4419 if (cum->arg_number < 2 && info.fpr_p)
4420 cum->fp_code += (mode == SFmode ? 1 : 2) << ((cum->arg_number - 1) * 2);
4421
4422 if (mips_abi != ABI_EABI || !info.fpr_p)
4423 cum->num_gprs = info.reg_offset + info.reg_words;
4424 else if (info.reg_words > 0)
4425 cum->num_fprs += FP_INC;
4426
4427 if (info.stack_words > 0)
4428 cum->stack_words = info.stack_offset + info.stack_words;
4429
4430 cum->arg_number++;
4431 }
4432
4433 /* Return an RTL expression containing the register for the given mode,
4434 or 0 if the argument is to be passed on the stack. */
4435
4436 struct rtx_def *
function_arg(cum,mode,type,named)4437 function_arg (cum, mode, type, named)
4438 const CUMULATIVE_ARGS *cum; /* current arg information */
4439 enum machine_mode mode; /* current arg mode */
4440 tree type; /* type of the argument or 0 if lib support */
4441 int named; /* != 0 for normal args, == 0 for ... args */
4442 {
4443 struct mips_arg_info info;
4444
4445 /* We will be called with a mode of VOIDmode after the last argument
4446 has been seen. Whatever we return will be passed to the call
4447 insn. If we need any shifts for small structures, return them in
4448 a PARALLEL; in that case, stuff the mips16 fp_code in as the
4449 mode. Otherwise, if we need a mips16 fp_code, return a REG
4450 with the code stored as the mode. */
4451 if (mode == VOIDmode)
4452 {
4453 if (cum->num_adjusts > 0)
4454 return gen_rtx_PARALLEL ((enum machine_mode) cum->fp_code,
4455 gen_rtvec_v (cum->num_adjusts,
4456 (rtx *) cum->adjust));
4457
4458 else if (TARGET_MIPS16 && cum->fp_code != 0)
4459 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
4460
4461 else
4462 return 0;
4463 }
4464
4465 mips_arg_info (cum, mode, type, named, &info);
4466
4467 /* Return straight away if the whole argument is passed on the stack. */
4468 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
4469 return 0;
4470
4471 if (type != 0
4472 && TREE_CODE (type) == RECORD_TYPE
4473 && (mips_abi == ABI_N32 || mips_abi == ABI_64)
4474 && TYPE_SIZE_UNIT (type)
4475 && host_integerp (TYPE_SIZE_UNIT (type), 1)
4476 && named
4477 && mode != DFmode)
4478 {
4479 /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
4480 structure contains a double in its entirety, then that 64 bit
4481 chunk is passed in a floating point register. */
4482 tree field;
4483
4484 /* First check to see if there is any such field. */
4485 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4486 if (TREE_CODE (field) == FIELD_DECL
4487 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4488 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
4489 && host_integerp (bit_position (field), 0)
4490 && int_bit_position (field) % BITS_PER_WORD == 0)
4491 break;
4492
4493 if (field != 0)
4494 {
4495 /* Now handle the special case by returning a PARALLEL
4496 indicating where each 64 bit chunk goes. INFO.REG_WORDS
4497 chunks are passed in registers. */
4498 unsigned int i;
4499 HOST_WIDE_INT bitpos;
4500 rtx ret;
4501
4502 /* assign_parms checks the mode of ENTRY_PARM, so we must
4503 use the actual mode here. */
4504 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
4505
4506 bitpos = 0;
4507 field = TYPE_FIELDS (type);
4508 for (i = 0; i < info.reg_words; i++)
4509 {
4510 rtx reg;
4511
4512 for (; field; field = TREE_CHAIN (field))
4513 if (TREE_CODE (field) == FIELD_DECL
4514 && int_bit_position (field) >= bitpos)
4515 break;
4516
4517 if (field
4518 && int_bit_position (field) == bitpos
4519 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4520 && !TARGET_SOFT_FLOAT
4521 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
4522 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
4523 else
4524 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
4525
4526 XVECEXP (ret, 0, i)
4527 = gen_rtx_EXPR_LIST (VOIDmode, reg,
4528 GEN_INT (bitpos / BITS_PER_UNIT));
4529
4530 bitpos += BITS_PER_WORD;
4531 }
4532 return ret;
4533 }
4534 }
4535
4536 if (mips_abi == ABI_MEABI && info.fpr_p && !cum->prototype)
4537 {
4538 /* To make K&R varargs work we need to pass floating
4539 point arguments in both integer and FP registers. */
4540 return gen_rtx_PARALLEL
4541 (mode,
4542 gen_rtvec (2,
4543 gen_rtx_EXPR_LIST (VOIDmode,
4544 gen_rtx_REG (mode,
4545 GP_ARG_FIRST
4546 + info.reg_offset),
4547 const0_rtx),
4548 gen_rtx_EXPR_LIST (VOIDmode,
4549 gen_rtx_REG (mode,
4550 FP_ARG_FIRST
4551 + info.reg_offset),
4552 const0_rtx)));
4553 }
4554
4555 if (info.fpr_p)
4556 return gen_rtx_REG (mode, FP_ARG_FIRST + info.reg_offset);
4557 else
4558 return gen_rtx_REG (mode, GP_ARG_FIRST + info.reg_offset);
4559 }
4560
4561 int
function_arg_partial_nregs(cum,mode,type,named)4562 function_arg_partial_nregs (cum, mode, type, named)
4563 const CUMULATIVE_ARGS *cum; /* current arg information */
4564 enum machine_mode mode; /* current arg mode */
4565 tree type; /* type of the argument or 0 if lib support */
4566 int named; /* != 0 for normal args, == 0 for ... args */
4567 {
4568 struct mips_arg_info info;
4569
4570 mips_arg_info (cum, mode, type, named, &info);
4571 return info.stack_words > 0 ? info.reg_words : 0;
4572 }
4573
4574 int
mips_setup_incoming_varargs(cum,mode,type,no_rtl)4575 mips_setup_incoming_varargs (cum, mode, type, no_rtl)
4576 const CUMULATIVE_ARGS *cum;
4577 enum machine_mode mode;
4578 tree type;
4579 int no_rtl;
4580 {
4581 CUMULATIVE_ARGS local_cum;
4582 int gp_saved, fp_saved;
4583
4584 if (mips_abi == ABI_32 || mips_abi == ABI_O64)
4585 return 0;
4586
4587 /* The caller has advanced CUM up to, but not beyond, the last named
4588 argument. Advance a local copy of CUM past the last "real" named
4589 argument, to find out how many registers are left over. */
4590
4591 local_cum = *cum;
4592 FUNCTION_ARG_ADVANCE (local_cum, mode, type, 1);
4593
4594 /* Found out how many registers we need to save. */
4595 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
4596 fp_saved = (EABI_FLOAT_VARARGS_P
4597 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
4598 : 0);
4599
4600 if (!no_rtl)
4601 {
4602 if (gp_saved > 0)
4603 {
4604 rtx ptr, mem;
4605
4606 ptr = virtual_incoming_args_rtx;
4607 if (mips_abi == ABI_EABI)
4608 ptr = plus_constant (ptr, -gp_saved * UNITS_PER_WORD);
4609 mem = gen_rtx_MEM (BLKmode, ptr);
4610
4611 /* va_arg is an array access in this case, which causes
4612 it to get MEM_IN_STRUCT_P set. We must set it here
4613 so that the insn scheduler won't assume that these
4614 stores can't possibly overlap with the va_arg loads. */
4615 if (mips_abi != ABI_EABI && BYTES_BIG_ENDIAN)
4616 MEM_SET_IN_STRUCT_P (mem, 1);
4617
4618 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST, mem,
4619 gp_saved, gp_saved * UNITS_PER_WORD);
4620 }
4621 if (fp_saved > 0)
4622 {
4623 /* We can't use move_block_from_reg, because it will use
4624 the wrong mode. */
4625 enum machine_mode mode;
4626 int off, i;
4627
4628 /* Set OFF to the offset from virtual_incoming_args_rtx of
4629 the first float register. The FP save area lies below
4630 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
4631 off = -gp_saved * UNITS_PER_WORD;
4632 off &= ~(UNITS_PER_FPVALUE - 1);
4633 off -= fp_saved * UNITS_PER_FPREG;
4634
4635 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
4636
4637 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS; i += FP_INC)
4638 {
4639 rtx ptr = plus_constant (virtual_incoming_args_rtx, off);
4640 emit_move_insn (gen_rtx_MEM (mode, ptr),
4641 gen_rtx_REG (mode, FP_ARG_FIRST + i));
4642 off += UNITS_PER_HWFPVALUE;
4643 }
4644 }
4645 }
4646 return (gp_saved * UNITS_PER_WORD) + (fp_saved * UNITS_PER_FPREG);
4647 }
4648
4649 /* Create the va_list data type.
4650 We keep 3 pointers, and two offsets.
4651 Two pointers are to the overflow area, which starts at the CFA.
4652 One of these is constant, for addressing into the GPR save area below it.
4653 The other is advanced up the stack through the overflow region.
4654 The third pointer is to the GPR save area. Since the FPR save area
4655 is just below it, we can address FPR slots off this pointer.
4656 We also keep two one-byte offsets, which are to be subtracted from the
4657 constant pointers to yield addresses in the GPR and FPR save areas.
4658 These are downcounted as float or non-float arguments are used,
4659 and when they get to zero, the argument must be obtained from the
4660 overflow region.
4661 If !EABI_FLOAT_VARARGS_P, then no FPR save area exists, and a single
4662 pointer is enough. It's started at the GPR save area, and is
4663 advanced, period.
4664 Note that the GPR save area is not constant size, due to optimization
4665 in the prologue. Hence, we can't use a design with two pointers
4666 and two offsets, although we could have designed this with two pointers
4667 and three offsets. */
4668
4669
4670 tree
mips_build_va_list()4671 mips_build_va_list ()
4672 {
4673 if (EABI_FLOAT_VARARGS_P)
4674 {
4675 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, record;
4676
4677 record = make_node (RECORD_TYPE);
4678
4679 f_ovfl = build_decl (FIELD_DECL, get_identifier ("__overflow_argptr"),
4680 ptr_type_node);
4681 f_gtop = build_decl (FIELD_DECL, get_identifier ("__gpr_top"),
4682 ptr_type_node);
4683 f_ftop = build_decl (FIELD_DECL, get_identifier ("__fpr_top"),
4684 ptr_type_node);
4685 f_goff = build_decl (FIELD_DECL, get_identifier ("__gpr_offset"),
4686 unsigned_char_type_node);
4687 f_foff = build_decl (FIELD_DECL, get_identifier ("__fpr_offset"),
4688 unsigned_char_type_node);
4689
4690
4691 DECL_FIELD_CONTEXT (f_ovfl) = record;
4692 DECL_FIELD_CONTEXT (f_gtop) = record;
4693 DECL_FIELD_CONTEXT (f_ftop) = record;
4694 DECL_FIELD_CONTEXT (f_goff) = record;
4695 DECL_FIELD_CONTEXT (f_foff) = record;
4696
4697 TYPE_FIELDS (record) = f_ovfl;
4698 TREE_CHAIN (f_ovfl) = f_gtop;
4699 TREE_CHAIN (f_gtop) = f_ftop;
4700 TREE_CHAIN (f_ftop) = f_goff;
4701 TREE_CHAIN (f_goff) = f_foff;
4702
4703 layout_type (record);
4704 return record;
4705 }
4706 else
4707 return ptr_type_node;
4708 }
4709
4710 /* Implement va_start. stdarg_p is always 1. */
4711
4712 void
mips_va_start(valist,nextarg)4713 mips_va_start (valist, nextarg)
4714 tree valist;
4715 rtx nextarg;
4716 {
4717 const CUMULATIVE_ARGS *cum = ¤t_function_args_info;
4718
4719 /* ARG_POINTER_REGNUM is initialized to STACK_POINTER_BOUNDARY, but
4720 since the stack is aligned for a pair of argument-passing slots,
4721 and the beginning of a variable argument list may be an odd slot,
4722 we have to decrease its alignment. */
4723 if (cfun && cfun->emit->regno_pointer_align)
4724 while (((current_function_pretend_args_size * BITS_PER_UNIT)
4725 & (REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) - 1)) != 0)
4726 REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) /= 2;
4727
4728 if (mips_abi == ABI_EABI)
4729 {
4730 int gpr_save_area_size;
4731
4732 gpr_save_area_size
4733 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
4734
4735 if (EABI_FLOAT_VARARGS_P)
4736 {
4737 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4738 tree ovfl, gtop, ftop, goff, foff;
4739 tree t;
4740 int fpr_offset;
4741 int fpr_save_area_size;
4742
4743 f_ovfl = TYPE_FIELDS (va_list_type_node);
4744 f_gtop = TREE_CHAIN (f_ovfl);
4745 f_ftop = TREE_CHAIN (f_gtop);
4746 f_goff = TREE_CHAIN (f_ftop);
4747 f_foff = TREE_CHAIN (f_goff);
4748
4749 ovfl = build (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl);
4750 gtop = build (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop);
4751 ftop = build (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop);
4752 goff = build (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff);
4753 foff = build (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff);
4754
4755 /* Emit code to initialize OVFL, which points to the next varargs
4756 stack argument. CUM->STACK_WORDS gives the number of stack
4757 words used by named arguments. */
4758 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
4759 if (cum->stack_words > 0)
4760 t = build (PLUS_EXPR, TREE_TYPE (ovfl), t,
4761 build_int_2 (cum->stack_words * UNITS_PER_WORD, 0));
4762 t = build (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
4763 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4764
4765 /* Emit code to initialize GTOP, the top of the GPR save area. */
4766 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
4767 t = build (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
4768 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4769
4770 /* Emit code to initialize FTOP, the top of the FPR save area.
4771 This address is gpr_save_area_bytes below GTOP, rounded
4772 down to the next fp-aligned boundary. */
4773 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
4774 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
4775 fpr_offset &= ~(UNITS_PER_FPVALUE - 1);
4776 if (fpr_offset)
4777 t = build (PLUS_EXPR, TREE_TYPE (ftop), t,
4778 build_int_2 (-fpr_offset, -1));
4779 t = build (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
4780 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4781
4782 /* Emit code to initialize GOFF, the offset from GTOP of the
4783 next GPR argument. */
4784 t = build (MODIFY_EXPR, TREE_TYPE (goff), goff,
4785 build_int_2 (gpr_save_area_size, 0));
4786 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4787
4788 /* Likewise emit code to initialize FOFF, the offset from FTOP
4789 of the next FPR argument. */
4790 fpr_save_area_size
4791 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
4792 t = build (MODIFY_EXPR, TREE_TYPE (foff), foff,
4793 build_int_2 (fpr_save_area_size, 0));
4794 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4795 }
4796 else
4797 {
4798 /* Everything is in the GPR save area, or in the overflow
4799 area which is contiguous with it. */
4800 nextarg = plus_constant (nextarg, -gpr_save_area_size);
4801 std_expand_builtin_va_start (valist, nextarg);
4802 }
4803 }
4804 else
4805 std_expand_builtin_va_start (valist, nextarg);
4806 }
4807
4808 /* Implement va_arg. */
4809
4810 rtx
mips_va_arg(valist,type)4811 mips_va_arg (valist, type)
4812 tree valist, type;
4813 {
4814 HOST_WIDE_INT size, rsize;
4815 rtx addr_rtx;
4816 tree t;
4817
4818 size = int_size_in_bytes (type);
4819 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
4820
4821 if (mips_abi == ABI_EABI)
4822 {
4823 bool indirect;
4824 rtx r;
4825
4826 indirect
4827 = function_arg_pass_by_reference (NULL, TYPE_MODE (type), type, 0);
4828
4829 if (indirect)
4830 {
4831 size = POINTER_SIZE / BITS_PER_UNIT;
4832 rsize = UNITS_PER_WORD;
4833 }
4834
4835 addr_rtx = gen_reg_rtx (Pmode);
4836
4837 if (!EABI_FLOAT_VARARGS_P)
4838 {
4839 /* Case of all args in a merged stack. No need to check bounds,
4840 just advance valist along the stack. */
4841
4842 tree gpr = valist;
4843 if (!indirect
4844 && !TARGET_64BIT
4845 && TYPE_ALIGN (type) > (unsigned) BITS_PER_WORD)
4846 {
4847 /* Align the pointer using: ap = (ap + align - 1) & -align,
4848 where align is 2 * UNITS_PER_WORD. */
4849 t = build (PLUS_EXPR, TREE_TYPE (gpr), gpr,
4850 build_int_2 (2 * UNITS_PER_WORD - 1, 0));
4851 t = build (BIT_AND_EXPR, TREE_TYPE (t), t,
4852 build_int_2 (-2 * UNITS_PER_WORD, -1));
4853 t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr, t);
4854 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4855 }
4856
4857 /* Emit code to set addr_rtx to the valist, and postincrement
4858 the valist by the size of the argument, rounded up to the
4859 next word. */
4860 t = build (POSTINCREMENT_EXPR, TREE_TYPE (gpr), gpr,
4861 size_int (rsize));
4862 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4863 if (r != addr_rtx)
4864 emit_move_insn (addr_rtx, r);
4865
4866 /* Flush the POSTINCREMENT. */
4867 emit_queue();
4868 }
4869 else
4870 {
4871 /* Not a simple merged stack. */
4872
4873 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4874 tree ovfl, top, off;
4875 rtx lab_over = NULL_RTX, lab_false;
4876 HOST_WIDE_INT osize;
4877
4878 f_ovfl = TYPE_FIELDS (va_list_type_node);
4879 f_gtop = TREE_CHAIN (f_ovfl);
4880 f_ftop = TREE_CHAIN (f_gtop);
4881 f_goff = TREE_CHAIN (f_ftop);
4882 f_foff = TREE_CHAIN (f_goff);
4883
4884 /* We maintain separate pointers and offsets for floating-point
4885 and integer arguments, but we need similar code in both cases.
4886 Let:
4887
4888 TOP be the top of the register save area;
4889 OFF be the offset from TOP of the next register;
4890 ADDR_RTX be the address of the argument; and
4891 RSIZE be the number of bytes used to store the argument
4892 when it's in the register save area
4893 OSIZE be the number of bytes used to store it when it's
4894 in the stack overflow area
4895 PADDING be (BYTES_BIG_ENDIAN ? OSIZE - RSIZE : 0)
4896
4897 The code we want is:
4898
4899 1: off &= -rsize; // round down
4900 2: if (off != 0)
4901 3: {
4902 4: addr_rtx = top - off;
4903 5: off -= rsize;
4904 6: }
4905 7: else
4906 8: {
4907 9: ovfl += ((intptr_t) ovfl + osize - 1) & -osize;
4908 10: addr_rtx = ovfl + PADDING;
4909 11: ovfl += osize;
4910 14: }
4911
4912 [1] and [9] can sometimes be optimized away. */
4913
4914 lab_false = gen_label_rtx ();
4915 lab_over = gen_label_rtx ();
4916
4917 ovfl = build (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl);
4918
4919 if (TREE_CODE (type) == REAL_TYPE)
4920 {
4921 top = build (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop);
4922 off = build (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff);
4923
4924 /* When floating-point registers are saved to the stack,
4925 each one will take up UNITS_PER_HWFPVALUE bytes, regardless
4926 of the float's precision. */
4927 rsize = UNITS_PER_HWFPVALUE;
4928 }
4929 else
4930 {
4931 top = build (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop);
4932 off = build (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff);
4933 if (rsize > UNITS_PER_WORD)
4934 {
4935 /* [1] Emit code for: off &= -rsize. */
4936 t = build (BIT_AND_EXPR, TREE_TYPE (off), off,
4937 build_int_2 (-rsize, -1));
4938 t = build (MODIFY_EXPR, TREE_TYPE (off), off, t);
4939 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4940 }
4941 }
4942 /* Every overflow argument must take up at least UNITS_PER_WORD
4943 bytes (= PARM_BOUNDARY bits). RSIZE can sometimes be smaller
4944 than that, such as in the combination -mgp64 -msingle-float
4945 -fshort-double. Doubles passed in registers will then take
4946 up UNITS_PER_HWFPVALUE bytes, but those passed on the stack
4947 take up UNITS_PER_WORD bytes. */
4948 osize = MAX (rsize, UNITS_PER_WORD);
4949
4950 /* [2] Emit code to branch if off == 0. */
4951 r = expand_expr (off, NULL_RTX, TYPE_MODE (TREE_TYPE (off)),
4952 EXPAND_NORMAL);
4953 emit_cmp_and_jump_insns (r, const0_rtx, EQ, const1_rtx, GET_MODE (r),
4954 1, lab_false);
4955
4956 /* [4] Emit code for: addr_rtx = top - off. */
4957 t = build (MINUS_EXPR, TREE_TYPE (top), top, off);
4958 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4959 if (r != addr_rtx)
4960 emit_move_insn (addr_rtx, r);
4961
4962 /* [5] Emit code for: off -= rsize. */
4963 t = build (MINUS_EXPR, TREE_TYPE (off), off, build_int_2 (rsize, 0));
4964 t = build (MODIFY_EXPR, TREE_TYPE (off), off, t);
4965 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4966
4967 /* [7] Emit code to jump over the else clause, then the label
4968 that starts it. */
4969 emit_queue();
4970 emit_jump (lab_over);
4971 emit_barrier ();
4972 emit_label (lab_false);
4973
4974 if (osize > UNITS_PER_WORD)
4975 {
4976 /* [9] Emit: ovfl += ((intptr_t) ovfl + osize - 1) & -osize. */
4977 t = build (PLUS_EXPR, TREE_TYPE (ovfl), ovfl,
4978 build_int_2 (osize - 1, 0));
4979 t = build (BIT_AND_EXPR, TREE_TYPE (ovfl), t,
4980 build_int_2 (-osize, -1));
4981 t = build (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
4982 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4983 }
4984
4985 /* [10, 11]. Emit code to store ovfl in addr_rtx, then
4986 post-increment ovfl by osize. On big-endian machines,
4987 the argument has OSIZE - RSIZE bytes of leading padding. */
4988 t = build (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl,
4989 size_int (osize));
4990 if (BYTES_BIG_ENDIAN && osize > rsize)
4991 t = build (PLUS_EXPR, TREE_TYPE (t), t,
4992 build_int_2 (osize - rsize, 0));
4993 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4994 if (r != addr_rtx)
4995 emit_move_insn (addr_rtx, r);
4996
4997 emit_queue();
4998 emit_label (lab_over);
4999 }
5000 if (indirect)
5001 {
5002 addr_rtx = force_reg (Pmode, addr_rtx);
5003 r = gen_rtx_MEM (Pmode, addr_rtx);
5004 set_mem_alias_set (r, get_varargs_alias_set ());
5005 emit_move_insn (addr_rtx, r);
5006 }
5007 else
5008 {
5009 if (BYTES_BIG_ENDIAN && rsize != size)
5010 addr_rtx = plus_constant (addr_rtx, rsize - size);
5011 }
5012 return addr_rtx;
5013 }
5014 else
5015 {
5016 /* Not EABI. */
5017 int align;
5018
5019 /* ??? The original va-mips.h did always align, despite the fact
5020 that alignments <= UNITS_PER_WORD are preserved by the va_arg
5021 increment mechanism. */
5022
5023 if ((mips_abi == ABI_N32 || mips_abi == ABI_64)
5024 && TYPE_ALIGN (type) > 64)
5025 align = 16;
5026 else if (TARGET_64BIT)
5027 align = 8;
5028 else if (TYPE_ALIGN (type) > 32)
5029 align = 8;
5030 else
5031 align = 4;
5032
5033 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
5034 build_int_2 (align - 1, 0));
5035 t = build (BIT_AND_EXPR, TREE_TYPE (t), t, build_int_2 (-align, -1));
5036 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
5037 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5038
5039 /* Everything past the alignment is standard. */
5040 return std_expand_builtin_va_arg (valist, type);
5041 }
5042 }
5043
5044 /* Abort after printing out a specific insn. */
5045
5046 static void
abort_with_insn(insn,reason)5047 abort_with_insn (insn, reason)
5048 rtx insn;
5049 const char *reason;
5050 {
5051 error (reason);
5052 debug_rtx (insn);
5053 abort ();
5054 }
5055
5056 /* Set up globals to generate code for the ISA or processor
5057 described by INFO. */
5058
5059 static void
mips_set_architecture(info)5060 mips_set_architecture (info)
5061 const struct mips_cpu_info *info;
5062 {
5063 if (info != 0)
5064 {
5065 mips_arch_info = info;
5066 mips_arch = info->cpu;
5067 mips_isa = info->isa;
5068 }
5069 }
5070
5071
5072 /* Likewise for tuning. */
5073
5074 static void
mips_set_tune(info)5075 mips_set_tune (info)
5076 const struct mips_cpu_info *info;
5077 {
5078 if (info != 0)
5079 {
5080 mips_tune_info = info;
5081 mips_tune = info->cpu;
5082 }
5083 }
5084
5085
5086 /* Set up the threshold for data to go into the small data area, instead
5087 of the normal data area, and detect any conflicts in the switches. */
5088
5089 void
override_options()5090 override_options ()
5091 {
5092 int i, start, regno;
5093 enum machine_mode mode;
5094
5095 mips_section_threshold = g_switch_set ? g_switch_value : MIPS_DEFAULT_GVALUE;
5096
5097 if (mips_section_threshold <= 0)
5098 target_flags &= ~MASK_GPOPT;
5099 else if (optimize)
5100 target_flags |= MASK_GPOPT;
5101
5102 /* If both single-float and soft-float are set, then clear the one that
5103 was set by TARGET_DEFAULT, leaving the one that was set by the
5104 user. We assume here that the specs prevent both being set by the
5105 user. */
5106 #ifdef TARGET_DEFAULT
5107 if (TARGET_SINGLE_FLOAT && TARGET_SOFT_FLOAT)
5108 target_flags &= ~((TARGET_DEFAULT) & (MASK_SOFT_FLOAT | MASK_SINGLE_FLOAT));
5109 #endif
5110
5111 /* Interpret -mabi. */
5112 mips_abi = MIPS_ABI_DEFAULT;
5113 if (mips_abi_string != 0)
5114 {
5115 if (strcmp (mips_abi_string, "32") == 0)
5116 mips_abi = ABI_32;
5117 else if (strcmp (mips_abi_string, "o64") == 0)
5118 mips_abi = ABI_O64;
5119 else if (strcmp (mips_abi_string, "n32") == 0)
5120 mips_abi = ABI_N32;
5121 else if (strcmp (mips_abi_string, "64") == 0)
5122 mips_abi = ABI_64;
5123 else if (strcmp (mips_abi_string, "eabi") == 0)
5124 mips_abi = ABI_EABI;
5125 else if (strcmp (mips_abi_string, "meabi") == 0)
5126 mips_abi = ABI_MEABI;
5127 else
5128 fatal_error ("bad value (%s) for -mabi= switch", mips_abi_string);
5129 }
5130
5131 /* The following code determines the architecture and register size.
5132 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
5133 The GAS and GCC code should be kept in sync as much as possible. */
5134
5135 if (mips_arch_string != 0)
5136 mips_set_architecture (mips_parse_cpu ("-march", mips_arch_string));
5137
5138 if (mips_tune_string != 0)
5139 mips_set_tune (mips_parse_cpu ("-mtune", mips_tune_string));
5140
5141 if (mips_isa_string != 0)
5142 {
5143 /* Handle -mipsN. */
5144 int level = atoi (mips_isa_string);
5145 if (level == 16)
5146 {
5147 /* -mips16 specifies an ASE rather than a processor, so don't
5148 change mips_arch here. -mno-mips16 overrides -mips16. */
5149 if (mips_no_mips16_string == NULL)
5150 target_flags |= MASK_MIPS16;
5151 }
5152 else if (mips_arch_info != 0)
5153 {
5154 /* -march takes precedence over -mipsN, since it is more descriptive.
5155 There's no harm in specifying both as long as the ISA levels
5156 are the same. */
5157 if (mips_isa != level)
5158 error ("-mips%d conflicts with the other architecture options, which specify a MIPS%d processor",
5159 level, mips_isa);
5160 }
5161 else
5162 {
5163 mips_set_architecture (mips_cpu_info_from_isa (level));
5164 if (mips_arch_info == 0)
5165 error ("bad value (%s) for -mips switch", mips_isa_string);
5166 }
5167 }
5168
5169 if (mips_arch_info == 0)
5170 {
5171 #ifdef MIPS_CPU_STRING_DEFAULT
5172 mips_set_architecture (mips_parse_cpu ("default CPU",
5173 MIPS_CPU_STRING_DEFAULT));
5174 #else
5175 mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT));
5176 #endif
5177 }
5178
5179 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
5180 error ("-march=%s is not compatible with the selected ABI",
5181 mips_arch_info->name);
5182
5183 /* Optimize for mips_arch, unless -mtune selects a different processor. */
5184 if (mips_tune_info == 0)
5185 mips_set_tune (mips_arch_info);
5186
5187 if ((target_flags_explicit & MASK_64BIT) != 0)
5188 {
5189 /* The user specified the size of the integer registers. Make sure
5190 it agrees with the ABI and ISA. */
5191 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
5192 error ("-mgp64 used with a 32-bit processor");
5193 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
5194 error ("-mgp32 used with a 64-bit ABI");
5195 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
5196 error ("-mgp64 used with a 32-bit ABI");
5197 }
5198 else
5199 {
5200 /* Infer the integer register size from the ABI and processor.
5201 Restrict ourselves to 32-bit registers if that's all the
5202 processor has, or if the ABI cannot handle 64-bit registers. */
5203 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
5204 target_flags &= ~MASK_64BIT;
5205 else
5206 target_flags |= MASK_64BIT;
5207 }
5208
5209 if ((target_flags_explicit & MASK_FLOAT64) != 0)
5210 {
5211 /* Really, -mfp32 and -mfp64 are ornamental options. There's
5212 only one right answer here. */
5213 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
5214 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
5215 else if (!TARGET_64BIT && TARGET_FLOAT64)
5216 error ("unsupported combination: %s", "-mgp32 -mfp64");
5217 else if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
5218 error ("unsupported combination: %s", "-mfp64 -msingle-float");
5219 }
5220 else
5221 {
5222 /* -msingle-float selects 32-bit float registers. Otherwise the
5223 float registers should be the same size as the integer ones. */
5224 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
5225 target_flags |= MASK_FLOAT64;
5226 else
5227 target_flags &= ~MASK_FLOAT64;
5228 }
5229
5230 /* End of code shared with GAS. */
5231
5232 if ((target_flags_explicit & MASK_LONG64) == 0)
5233 {
5234 /* If no type size setting options (-mlong64,-mint64,-mlong32)
5235 were used, then set the type sizes. In the EABI in 64 bit mode,
5236 longs and pointers are 64 bits. Likewise for the SGI Irix6 N64
5237 ABI. */
5238 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
5239 target_flags |= MASK_LONG64;
5240 else
5241 target_flags &= ~MASK_LONG64;
5242 }
5243
5244 if (MIPS_MARCH_CONTROLS_SOFT_FLOAT
5245 && (target_flags_explicit & MASK_SOFT_FLOAT) == 0)
5246 {
5247 /* For some configurations, it is useful to have -march control
5248 the default setting of MASK_SOFT_FLOAT. */
5249 switch ((int) mips_arch)
5250 {
5251 case PROCESSOR_R4100:
5252 case PROCESSOR_R4120:
5253 target_flags |= MASK_SOFT_FLOAT;
5254 break;
5255
5256 default:
5257 target_flags &= ~MASK_SOFT_FLOAT;
5258 break;
5259 }
5260 }
5261
5262 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
5263 flag_pcc_struct_return = 0;
5264
5265 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
5266 {
5267 /* If neither -mbranch-likely nor -mno-branch-likely was given
5268 on the command line, set MASK_BRANCHLIKELY based on the target
5269 architecture.
5270
5271 By default, we enable use of Branch Likely instructions on
5272 all architectures which support them except for MIPS32 and MIPS64
5273 (i.e., the generic MIPS32 and MIPS64 ISAs, and processors which
5274 implement them).
5275
5276 The MIPS32 and MIPS64 architecture specifications say "Software
5277 is strongly encouraged to avoid use of Branch Likely
5278 instructions, as they will be removed from a future revision
5279 of the [MIPS32 and MIPS64] architecture." Therefore, we do not
5280 issue those instructions unless instructed to do so by
5281 -mbranch-likely. */
5282 if (ISA_HAS_BRANCHLIKELY && !(ISA_MIPS32 || ISA_MIPS64))
5283 target_flags |= MASK_BRANCHLIKELY;
5284 else
5285 target_flags &= ~MASK_BRANCHLIKELY;
5286 }
5287 if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
5288 warning ("generation of Branch Likely instructions enabled, but not supported by architecture");
5289
5290 /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined. We need
5291 to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work. */
5292 /* ??? -non_shared turns off pic code generation, but this is not
5293 implemented. */
5294 if (TARGET_ABICALLS)
5295 {
5296 mips_abicalls = MIPS_ABICALLS_YES;
5297 flag_pic = 1;
5298 if (mips_section_threshold > 0)
5299 warning ("-G is incompatible with PIC code which is the default");
5300 }
5301 else
5302 mips_abicalls = MIPS_ABICALLS_NO;
5303
5304 /* -membedded-pic is a form of PIC code suitable for embedded
5305 systems. All calls are made using PC relative addressing, and
5306 all data is addressed using the $gp register. This requires gas,
5307 which does most of the work, and GNU ld, which automatically
5308 expands PC relative calls which are out of range into a longer
5309 instruction sequence. All gcc really does differently is
5310 generate a different sequence for a switch. */
5311 if (TARGET_EMBEDDED_PIC)
5312 {
5313 flag_pic = 1;
5314 if (TARGET_ABICALLS)
5315 warning ("-membedded-pic and -mabicalls are incompatible");
5316
5317 if (g_switch_set)
5318 warning ("-G and -membedded-pic are incompatible");
5319
5320 /* Setting mips_section_threshold is not required, because gas
5321 will force everything to be GP addressable anyhow, but
5322 setting it will cause gcc to make better estimates of the
5323 number of instructions required to access a particular data
5324 item. */
5325 mips_section_threshold = 0x7fffffff;
5326 }
5327
5328 /* This optimization requires a linker that can support a R_MIPS_LO16
5329 relocation which is not immediately preceded by a R_MIPS_HI16 relocation.
5330 GNU ld has this support, but not all other MIPS linkers do, so we enable
5331 this optimization only if the user requests it, or if GNU ld is the
5332 standard linker for this configuration. */
5333 /* ??? This does not work when target addresses are DImode.
5334 This is because we are missing DImode high/lo_sum patterns. */
5335 if (TARGET_GAS && ! TARGET_MIPS16 && TARGET_SPLIT_ADDRESSES && optimize && ! flag_pic
5336 && Pmode == SImode)
5337 mips_split_addresses = 1;
5338 else
5339 mips_split_addresses = 0;
5340
5341 /* -mrnames says to use the MIPS software convention for register
5342 names instead of the hardware names (ie, $a0 instead of $4).
5343 We do this by switching the names in mips_reg_names, which the
5344 reg_names points into via the REGISTER_NAMES macro. */
5345
5346 if (TARGET_NAME_REGS)
5347 memcpy (mips_reg_names, mips_sw_reg_names, sizeof (mips_reg_names));
5348
5349 /* When compiling for the mips16, we can not use floating point. We
5350 record the original hard float value in mips16_hard_float. */
5351 if (TARGET_MIPS16)
5352 {
5353 if (TARGET_SOFT_FLOAT)
5354 mips16_hard_float = 0;
5355 else
5356 mips16_hard_float = 1;
5357 target_flags |= MASK_SOFT_FLOAT;
5358
5359 /* Don't run the scheduler before reload, since it tends to
5360 increase register pressure. */
5361 flag_schedule_insns = 0;
5362 }
5363
5364 /* We put -mentry in TARGET_OPTIONS rather than TARGET_SWITCHES only
5365 to avoid using up another bit in target_flags. */
5366 if (mips_entry_string != NULL)
5367 {
5368 if (*mips_entry_string != '\0')
5369 error ("invalid option `entry%s'", mips_entry_string);
5370
5371 if (! TARGET_MIPS16)
5372 warning ("-mentry is only meaningful with -mips-16");
5373 else
5374 mips_entry = 1;
5375 }
5376
5377 /* We copy TARGET_MIPS16 into the mips16 global variable, so that
5378 attributes can access it. */
5379 if (TARGET_MIPS16)
5380 mips16 = 1;
5381 else
5382 mips16 = 0;
5383
5384 #ifdef MIPS_TFMODE_FORMAT
5385 real_format_for_mode[TFmode - QFmode] = &MIPS_TFMODE_FORMAT;
5386 #endif
5387
5388 mips_print_operand_punct['?'] = 1;
5389 mips_print_operand_punct['#'] = 1;
5390 mips_print_operand_punct['&'] = 1;
5391 mips_print_operand_punct['!'] = 1;
5392 mips_print_operand_punct['*'] = 1;
5393 mips_print_operand_punct['@'] = 1;
5394 mips_print_operand_punct['.'] = 1;
5395 mips_print_operand_punct['('] = 1;
5396 mips_print_operand_punct[')'] = 1;
5397 mips_print_operand_punct['['] = 1;
5398 mips_print_operand_punct[']'] = 1;
5399 mips_print_operand_punct['<'] = 1;
5400 mips_print_operand_punct['>'] = 1;
5401 mips_print_operand_punct['{'] = 1;
5402 mips_print_operand_punct['}'] = 1;
5403 mips_print_operand_punct['^'] = 1;
5404 mips_print_operand_punct['$'] = 1;
5405 mips_print_operand_punct['+'] = 1;
5406 mips_print_operand_punct['~'] = 1;
5407
5408 mips_char_to_class['d'] = TARGET_MIPS16 ? M16_REGS : GR_REGS;
5409 mips_char_to_class['e'] = M16_NA_REGS;
5410 mips_char_to_class['t'] = T_REG;
5411 mips_char_to_class['f'] = (TARGET_HARD_FLOAT ? FP_REGS : NO_REGS);
5412 mips_char_to_class['h'] = HI_REG;
5413 mips_char_to_class['l'] = LO_REG;
5414 mips_char_to_class['a'] = HILO_REG;
5415 mips_char_to_class['x'] = MD_REGS;
5416 mips_char_to_class['b'] = ALL_REGS;
5417 mips_char_to_class['y'] = GR_REGS;
5418 mips_char_to_class['z'] = ST_REGS;
5419 mips_char_to_class['B'] = COP0_REGS;
5420 mips_char_to_class['C'] = COP2_REGS;
5421 mips_char_to_class['D'] = COP3_REGS;
5422
5423 /* Set up array to map GCC register number to debug register number.
5424 Ignore the special purpose register numbers. */
5425
5426 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5427 mips_dbx_regno[i] = -1;
5428
5429 start = GP_DBX_FIRST - GP_REG_FIRST;
5430 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
5431 mips_dbx_regno[i] = i + start;
5432
5433 start = FP_DBX_FIRST - FP_REG_FIRST;
5434 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
5435 mips_dbx_regno[i] = i + start;
5436
5437 /* Set up array giving whether a given register can hold a given mode.
5438 At present, restrict ints from being in FP registers, because reload
5439 is a little enthusiastic about storing extra values in FP registers,
5440 and this is not good for things like OS kernels. Also, due to the
5441 mandatory delay, it is as fast to load from cached memory as to move
5442 from the FP register. */
5443
5444 for (mode = VOIDmode;
5445 mode != MAX_MACHINE_MODE;
5446 mode = (enum machine_mode) ((int)mode + 1))
5447 {
5448 register int size = GET_MODE_SIZE (mode);
5449 register enum mode_class class = GET_MODE_CLASS (mode);
5450
5451 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
5452 {
5453 register int temp;
5454
5455 if (mode == CCmode)
5456 {
5457 if (! ISA_HAS_8CC)
5458 temp = (regno == FPSW_REGNUM);
5459 else
5460 temp = (ST_REG_P (regno) || GP_REG_P (regno)
5461 || FP_REG_P (regno));
5462 }
5463
5464 else if (GP_REG_P (regno))
5465 temp = ((regno & 1) == 0 || size <= UNITS_PER_WORD);
5466
5467 else if (FP_REG_P (regno))
5468 temp = (((regno % FP_INC) == 0
5469 /* I think this change is OK regardless of abi, but
5470 I'm being cautions untill I can test this more.
5471 HARD_REGNO_MODE_OK is about whether or not you
5472 can move to and from a register without changing
5473 the value, not about whether math works on the
5474 register. */
5475 || (mips_abi == ABI_MEABI && size <= 4))
5476 && (((class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT)
5477 && size <= UNITS_PER_FPVALUE)
5478 /* Allow integer modes that fit into a single
5479 register. We need to put integers into FPRs
5480 when using instructions like cvt and trunc. */
5481 || (class == MODE_INT && size <= UNITS_PER_FPREG)
5482 /* Allow TFmode for CCmode reloads. */
5483 || (ISA_HAS_8CC && mode == TFmode)));
5484
5485 else if (MD_REG_P (regno))
5486 temp = (class == MODE_INT
5487 && (size <= UNITS_PER_WORD
5488 || (regno == MD_REG_FIRST
5489 && size == 2 * UNITS_PER_WORD)));
5490
5491 else if (ALL_COP_REG_P (regno))
5492 temp = (class == MODE_INT && size <= UNITS_PER_WORD);
5493 else
5494 temp = 0;
5495
5496 mips_hard_regno_mode_ok[(int)mode][regno] = temp;
5497 }
5498 }
5499
5500 /* Save GPR registers in word_mode sized hunks. word_mode hasn't been
5501 initialized yet, so we can't use that here. */
5502 gpr_mode = TARGET_64BIT ? DImode : SImode;
5503
5504 /* Provide default values for align_* for 64-bit targets. */
5505 if (TARGET_64BIT && !TARGET_MIPS16)
5506 {
5507 if (align_loops == 0)
5508 align_loops = 8;
5509 if (align_jumps == 0)
5510 align_jumps = 8;
5511 if (align_functions == 0)
5512 align_functions = 8;
5513 }
5514
5515 /* Function to allocate machine-dependent function status. */
5516 init_machine_status = &mips_init_machine_status;
5517 }
5518
5519 /* Implement CONDITIONAL_REGISTER_USAGE. */
5520
5521 void
mips_conditional_register_usage()5522 mips_conditional_register_usage ()
5523 {
5524 if (!TARGET_HARD_FLOAT)
5525 {
5526 int regno;
5527
5528 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
5529 fixed_regs[regno] = call_used_regs[regno] = 1;
5530 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
5531 fixed_regs[regno] = call_used_regs[regno] = 1;
5532 }
5533 else if (! ISA_HAS_8CC)
5534 {
5535 int regno;
5536
5537 /* We only have a single condition code register. We
5538 implement this by hiding all the condition code registers,
5539 and generating RTL that refers directly to ST_REG_FIRST. */
5540 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
5541 fixed_regs[regno] = call_used_regs[regno] = 1;
5542 }
5543 /* In mips16 mode, we permit the $t temporary registers to be used
5544 for reload. We prohibit the unused $s registers, since they
5545 are caller saved, and saving them via a mips16 register would
5546 probably waste more time than just reloading the value. */
5547 if (TARGET_MIPS16)
5548 {
5549 fixed_regs[18] = call_used_regs[18] = 1;
5550 fixed_regs[19] = call_used_regs[19] = 1;
5551 fixed_regs[20] = call_used_regs[20] = 1;
5552 fixed_regs[21] = call_used_regs[21] = 1;
5553 fixed_regs[22] = call_used_regs[22] = 1;
5554 fixed_regs[23] = call_used_regs[23] = 1;
5555 fixed_regs[26] = call_used_regs[26] = 1;
5556 fixed_regs[27] = call_used_regs[27] = 1;
5557 fixed_regs[30] = call_used_regs[30] = 1;
5558 }
5559 /* fp20-23 are now caller saved. */
5560 if (mips_abi == ABI_64)
5561 {
5562 int regno;
5563 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
5564 call_really_used_regs[regno] = call_used_regs[regno] = 1;
5565 }
5566 /* odd registers from fp21 to fp31 are now caller saved. */
5567 if (mips_abi == ABI_N32 || mips_abi == ABI_MEABI)
5568 {
5569 int regno;
5570 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
5571 call_really_used_regs[regno] = call_used_regs[regno] = 1;
5572 }
5573 }
5574
5575 /* Allocate a chunk of memory for per-function machine-dependent data. */
5576 static struct machine_function *
mips_init_machine_status()5577 mips_init_machine_status ()
5578 {
5579 return ((struct machine_function *)
5580 ggc_alloc_cleared (sizeof (struct machine_function)));
5581 }
5582
5583 /* On the mips16, we want to allocate $24 (T_REG) before other
5584 registers for instructions for which it is possible. This helps
5585 avoid shuffling registers around in order to set up for an xor,
5586 encouraging the compiler to use a cmp instead. */
5587
5588 void
mips_order_regs_for_local_alloc()5589 mips_order_regs_for_local_alloc ()
5590 {
5591 register int i;
5592
5593 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5594 reg_alloc_order[i] = i;
5595
5596 if (TARGET_MIPS16)
5597 {
5598 /* It really doesn't matter where we put register 0, since it is
5599 a fixed register anyhow. */
5600 reg_alloc_order[0] = 24;
5601 reg_alloc_order[24] = 0;
5602 }
5603 }
5604
5605
5606 /* The MIPS debug format wants all automatic variables and arguments
5607 to be in terms of the virtual frame pointer (stack pointer before
5608 any adjustment in the function), while the MIPS 3.0 linker wants
5609 the frame pointer to be the stack pointer after the initial
5610 adjustment. So, we do the adjustment here. The arg pointer (which
5611 is eliminated) points to the virtual frame pointer, while the frame
5612 pointer (which may be eliminated) points to the stack pointer after
5613 the initial adjustments. */
5614
5615 HOST_WIDE_INT
mips_debugger_offset(addr,offset)5616 mips_debugger_offset (addr, offset)
5617 rtx addr;
5618 HOST_WIDE_INT offset;
5619 {
5620 rtx offset2 = const0_rtx;
5621 rtx reg = eliminate_constant_term (addr, &offset2);
5622
5623 if (offset == 0)
5624 offset = INTVAL (offset2);
5625
5626 if (reg == stack_pointer_rtx || reg == frame_pointer_rtx
5627 || reg == hard_frame_pointer_rtx)
5628 {
5629 HOST_WIDE_INT frame_size = (!cfun->machine->frame.initialized)
5630 ? compute_frame_size (get_frame_size ())
5631 : cfun->machine->frame.total_size;
5632
5633 /* MIPS16 frame is smaller */
5634 if (frame_pointer_needed && TARGET_MIPS16)
5635 frame_size -= current_function_outgoing_args_size;
5636
5637 offset = offset - frame_size;
5638 }
5639
5640 /* sdbout_parms does not want this to crash for unrecognized cases. */
5641 #if 0
5642 else if (reg != arg_pointer_rtx)
5643 abort_with_insn (addr, "mips_debugger_offset called with non stack/frame/arg pointer");
5644 #endif
5645
5646 return offset;
5647 }
5648
5649 /* A C compound statement to output to stdio stream STREAM the
5650 assembler syntax for an instruction operand X. X is an RTL
5651 expression.
5652
5653 CODE is a value that can be used to specify one of several ways
5654 of printing the operand. It is used when identical operands
5655 must be printed differently depending on the context. CODE
5656 comes from the `%' specification that was used to request
5657 printing of the operand. If the specification was just `%DIGIT'
5658 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
5659 is the ASCII code for LTR.
5660
5661 If X is a register, this macro should print the register's name.
5662 The names can be found in an array `reg_names' whose type is
5663 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
5664
5665 When the machine description has a specification `%PUNCT' (a `%'
5666 followed by a punctuation character), this macro is called with
5667 a null pointer for X and the punctuation character for CODE.
5668
5669 The MIPS specific codes are:
5670
5671 'X' X is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
5672 'x' X is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
5673 'd' output integer constant in decimal,
5674 'z' if the operand is 0, use $0 instead of normal operand.
5675 'D' print second part of double-word register or memory operand.
5676 'L' print low-order register of double-word register operand.
5677 'M' print high-order register of double-word register operand.
5678 'C' print part of opcode for a branch condition.
5679 'F' print part of opcode for a floating-point branch condition.
5680 'N' print part of opcode for a branch condition, inverted.
5681 'W' print part of opcode for a floating-point branch condition, inverted.
5682 'S' X is CODE_LABEL, print with prefix of "LS" (for embedded switch).
5683 'B' print 'z' for EQ, 'n' for NE
5684 'b' print 'n' for EQ, 'z' for NE
5685 'T' print 'f' for EQ, 't' for NE
5686 't' print 't' for EQ, 'f' for NE
5687 'Z' print register and a comma, but print nothing for $fcc0
5688 '(' Turn on .set noreorder
5689 ')' Turn on .set reorder
5690 '[' Turn on .set noat
5691 ']' Turn on .set at
5692 '<' Turn on .set nomacro
5693 '>' Turn on .set macro
5694 '{' Turn on .set volatile (not GAS)
5695 '}' Turn on .set novolatile (not GAS)
5696 '&' Turn on .set noreorder if filling delay slots
5697 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
5698 '!' Turn on .set nomacro if filling delay slots
5699 '#' Print nop if in a .set noreorder section.
5700 '?' Print 'l' if we are to use a branch likely instead of normal branch.
5701 '@' Print the name of the assembler temporary register (at or $1).
5702 '.' Print the name of the register with a hard-wired zero (zero or $0).
5703 '^' Print the name of the pic call-through register (t9 or $25).
5704 '$' Print the name of the stack pointer register (sp or $29).
5705 '+' Print the name of the gp register (gp or $28).
5706 '~' Output an branch alignment to LABEL_ALIGN(NULL). */
5707
5708 void
print_operand(file,op,letter)5709 print_operand (file, op, letter)
5710 FILE *file; /* file to write to */
5711 rtx op; /* operand to print */
5712 int letter; /* %<letter> or 0 */
5713 {
5714 register enum rtx_code code;
5715
5716 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
5717 {
5718 switch (letter)
5719 {
5720 case '?':
5721 if (mips_branch_likely)
5722 putc ('l', file);
5723 break;
5724
5725 case '@':
5726 fputs (reg_names [GP_REG_FIRST + 1], file);
5727 break;
5728
5729 case '^':
5730 fputs (reg_names [PIC_FUNCTION_ADDR_REGNUM], file);
5731 break;
5732
5733 case '.':
5734 fputs (reg_names [GP_REG_FIRST + 0], file);
5735 break;
5736
5737 case '$':
5738 fputs (reg_names[STACK_POINTER_REGNUM], file);
5739 break;
5740
5741 case '+':
5742 fputs (reg_names[GP_REG_FIRST + 28], file);
5743 break;
5744
5745 case '&':
5746 if (final_sequence != 0 && set_noreorder++ == 0)
5747 fputs (".set\tnoreorder\n\t", file);
5748 break;
5749
5750 case '*':
5751 if (final_sequence != 0)
5752 {
5753 if (set_noreorder++ == 0)
5754 fputs (".set\tnoreorder\n\t", file);
5755
5756 if (set_nomacro++ == 0)
5757 fputs (".set\tnomacro\n\t", file);
5758 }
5759 break;
5760
5761 case '!':
5762 if (final_sequence != 0 && set_nomacro++ == 0)
5763 fputs ("\n\t.set\tnomacro", file);
5764 break;
5765
5766 case '#':
5767 if (set_noreorder != 0)
5768 fputs ("\n\tnop", file);
5769 else if (TARGET_STATS)
5770 fputs ("\n\t#nop", file);
5771
5772 break;
5773
5774 case '(':
5775 if (set_noreorder++ == 0)
5776 fputs (".set\tnoreorder\n\t", file);
5777 break;
5778
5779 case ')':
5780 if (set_noreorder == 0)
5781 error ("internal error: %%) found without a %%( in assembler pattern");
5782
5783 else if (--set_noreorder == 0)
5784 fputs ("\n\t.set\treorder", file);
5785
5786 break;
5787
5788 case '[':
5789 if (set_noat++ == 0)
5790 fputs (".set\tnoat\n\t", file);
5791 break;
5792
5793 case ']':
5794 if (set_noat == 0)
5795 error ("internal error: %%] found without a %%[ in assembler pattern");
5796 else if (--set_noat == 0)
5797 fputs ("\n\t.set\tat", file);
5798
5799 break;
5800
5801 case '<':
5802 if (set_nomacro++ == 0)
5803 fputs (".set\tnomacro\n\t", file);
5804 break;
5805
5806 case '>':
5807 if (set_nomacro == 0)
5808 error ("internal error: %%> found without a %%< in assembler pattern");
5809 else if (--set_nomacro == 0)
5810 fputs ("\n\t.set\tmacro", file);
5811
5812 break;
5813
5814 case '{':
5815 if (set_volatile++ == 0)
5816 fprintf (file, "%s.set\tvolatile\n\t", TARGET_MIPS_AS ? "" : "#");
5817 break;
5818
5819 case '}':
5820 if (set_volatile == 0)
5821 error ("internal error: %%} found without a %%{ in assembler pattern");
5822 else if (--set_volatile == 0)
5823 fprintf (file, "\n\t%s.set\tnovolatile", (TARGET_MIPS_AS) ? "" : "#");
5824
5825 break;
5826
5827 case '~':
5828 {
5829 if (align_labels_log > 0)
5830 ASM_OUTPUT_ALIGN (file, align_labels_log);
5831 }
5832 break;
5833
5834 default:
5835 error ("PRINT_OPERAND: unknown punctuation '%c'", letter);
5836 break;
5837 }
5838
5839 return;
5840 }
5841
5842 if (! op)
5843 {
5844 error ("PRINT_OPERAND null pointer");
5845 return;
5846 }
5847
5848 code = GET_CODE (op);
5849
5850 if (code == SIGN_EXTEND)
5851 op = XEXP (op, 0), code = GET_CODE (op);
5852
5853 if (letter == 'C')
5854 switch (code)
5855 {
5856 case EQ: fputs ("eq", file); break;
5857 case NE: fputs ("ne", file); break;
5858 case GT: fputs ("gt", file); break;
5859 case GE: fputs ("ge", file); break;
5860 case LT: fputs ("lt", file); break;
5861 case LE: fputs ("le", file); break;
5862 case GTU: fputs ("gtu", file); break;
5863 case GEU: fputs ("geu", file); break;
5864 case LTU: fputs ("ltu", file); break;
5865 case LEU: fputs ("leu", file); break;
5866 default:
5867 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%C");
5868 }
5869
5870 else if (letter == 'N')
5871 switch (code)
5872 {
5873 case EQ: fputs ("ne", file); break;
5874 case NE: fputs ("eq", file); break;
5875 case GT: fputs ("le", file); break;
5876 case GE: fputs ("lt", file); break;
5877 case LT: fputs ("ge", file); break;
5878 case LE: fputs ("gt", file); break;
5879 case GTU: fputs ("leu", file); break;
5880 case GEU: fputs ("ltu", file); break;
5881 case LTU: fputs ("geu", file); break;
5882 case LEU: fputs ("gtu", file); break;
5883 default:
5884 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%N");
5885 }
5886
5887 else if (letter == 'F')
5888 switch (code)
5889 {
5890 case EQ: fputs ("c1f", file); break;
5891 case NE: fputs ("c1t", file); break;
5892 default:
5893 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%F");
5894 }
5895
5896 else if (letter == 'W')
5897 switch (code)
5898 {
5899 case EQ: fputs ("c1t", file); break;
5900 case NE: fputs ("c1f", file); break;
5901 default:
5902 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%W");
5903 }
5904
5905 else if (letter == 'S')
5906 {
5907 char buffer[100];
5908
5909 ASM_GENERATE_INTERNAL_LABEL (buffer, "LS", CODE_LABEL_NUMBER (op));
5910 assemble_name (file, buffer);
5911 }
5912
5913 else if (letter == 'Z')
5914 {
5915 register int regnum;
5916
5917 if (code != REG)
5918 abort ();
5919
5920 regnum = REGNO (op);
5921 if (! ST_REG_P (regnum))
5922 abort ();
5923
5924 if (regnum != ST_REG_FIRST)
5925 fprintf (file, "%s,", reg_names[regnum]);
5926 }
5927
5928 else if (code == REG || code == SUBREG)
5929 {
5930 register int regnum;
5931
5932 if (code == REG)
5933 regnum = REGNO (op);
5934 else
5935 regnum = true_regnum (op);
5936
5937 if ((letter == 'M' && ! WORDS_BIG_ENDIAN)
5938 || (letter == 'L' && WORDS_BIG_ENDIAN)
5939 || letter == 'D')
5940 regnum++;
5941
5942 fprintf (file, "%s", reg_names[regnum]);
5943 }
5944
5945 else if (code == MEM)
5946 {
5947 if (letter == 'D')
5948 output_address (plus_constant (XEXP (op, 0), 4));
5949 else
5950 output_address (XEXP (op, 0));
5951 }
5952
5953 else if (code == CONST_DOUBLE
5954 && GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT)
5955 {
5956 char s[60];
5957
5958 real_to_decimal (s, CONST_DOUBLE_REAL_VALUE (op), sizeof (s), 0, 1);
5959 fputs (s, file);
5960 }
5961
5962 else if (letter == 'x' && GET_CODE (op) == CONST_INT)
5963 fprintf (file, HOST_WIDE_INT_PRINT_HEX, 0xffff & INTVAL(op));
5964
5965 else if (letter == 'X' && GET_CODE(op) == CONST_INT)
5966 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
5967
5968 else if (letter == 'd' && GET_CODE(op) == CONST_INT)
5969 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (INTVAL(op)));
5970
5971 else if (letter == 'z' && GET_CODE (op) == CONST_INT && INTVAL (op) == 0)
5972 fputs (reg_names[GP_REG_FIRST], file);
5973
5974 else if (letter == 'd' || letter == 'x' || letter == 'X')
5975 output_operand_lossage ("invalid use of %%d, %%x, or %%X");
5976
5977 else if (letter == 'B')
5978 fputs (code == EQ ? "z" : "n", file);
5979 else if (letter == 'b')
5980 fputs (code == EQ ? "n" : "z", file);
5981 else if (letter == 'T')
5982 fputs (code == EQ ? "f" : "t", file);
5983 else if (letter == 't')
5984 fputs (code == EQ ? "t" : "f", file);
5985
5986 else if (code == CONST && GET_CODE (XEXP (op, 0)) == REG)
5987 {
5988 /* This case arises on the mips16; see mips16_gp_pseudo_reg. */
5989 print_operand (file, XEXP (op, 0), letter);
5990 }
5991
5992 else if (TARGET_MIPS16 && code == CONST && mips16_gp_offset_p (op))
5993 {
5994 fputs ("%gprel(", file);
5995 mips16_output_gp_offset (file, op);
5996 fputs (")", file);
5997 }
5998
5999 else
6000 output_addr_const (file, op);
6001 }
6002
6003 /* A C compound statement to output to stdio stream STREAM the
6004 assembler syntax for an instruction operand that is a memory
6005 reference whose address is ADDR. ADDR is an RTL expression. */
6006
6007 void
print_operand_address(file,addr)6008 print_operand_address (file, addr)
6009 FILE *file;
6010 rtx addr;
6011 {
6012 if (!addr)
6013 error ("PRINT_OPERAND_ADDRESS, null pointer");
6014
6015 else
6016 switch (GET_CODE (addr))
6017 {
6018 case REG:
6019 if (! TARGET_MIPS16 && REGNO (addr) == ARG_POINTER_REGNUM)
6020 abort_with_insn (addr, "arg pointer not eliminated");
6021
6022 fprintf (file, "0(%s)", reg_names [REGNO (addr)]);
6023 break;
6024
6025 case LO_SUM:
6026 {
6027 register rtx arg0 = XEXP (addr, 0);
6028 register rtx arg1 = XEXP (addr, 1);
6029
6030 if (! mips_split_addresses)
6031 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, Spurious LO_SUM");
6032
6033 if (GET_CODE (arg0) != REG)
6034 abort_with_insn (addr,
6035 "PRINT_OPERAND_ADDRESS, LO_SUM with #1 not REG");
6036
6037 fprintf (file, "%%lo(");
6038 print_operand_address (file, arg1);
6039 fprintf (file, ")(%s)", reg_names [REGNO (arg0)]);
6040 }
6041 break;
6042
6043 case PLUS:
6044 {
6045 register rtx reg = 0;
6046 register rtx offset = 0;
6047 register rtx arg0 = XEXP (addr, 0);
6048 register rtx arg1 = XEXP (addr, 1);
6049
6050 if (GET_CODE (arg0) == REG)
6051 {
6052 reg = arg0;
6053 offset = arg1;
6054 if (GET_CODE (offset) == REG)
6055 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, 2 regs");
6056 }
6057
6058 else if (GET_CODE (arg1) == REG)
6059 reg = arg1, offset = arg0;
6060 else if (CONSTANT_P (arg0) && CONSTANT_P (arg1))
6061 {
6062 output_addr_const (file, addr);
6063 break;
6064 }
6065 else
6066 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, no regs");
6067
6068 if (! CONSTANT_P (offset))
6069 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, invalid insn #2");
6070
6071 if (REGNO (reg) == ARG_POINTER_REGNUM)
6072 abort_with_insn (addr, "arg pointer not eliminated");
6073
6074 if (TARGET_MIPS16
6075 && GET_CODE (offset) == CONST
6076 && mips16_gp_offset_p (offset))
6077 {
6078 fputs ("%gprel(", file);
6079 mips16_output_gp_offset (file, offset);
6080 fputs (")", file);
6081 }
6082 else
6083 output_addr_const (file, offset);
6084 fprintf (file, "(%s)", reg_names [REGNO (reg)]);
6085 }
6086 break;
6087
6088 case LABEL_REF:
6089 case SYMBOL_REF:
6090 case CONST_INT:
6091 case CONST:
6092 output_addr_const (file, addr);
6093 break;
6094
6095 default:
6096 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, invalid insn #1");
6097 break;
6098 }
6099 }
6100
6101 /* Target hook for assembling integer objects. It appears that the Irix
6102 6 assembler can't handle 64-bit decimal integers, so avoid printing
6103 such an integer here. */
6104
6105 static bool
mips_assemble_integer(x,size,aligned_p)6106 mips_assemble_integer (x, size, aligned_p)
6107 rtx x;
6108 unsigned int size;
6109 int aligned_p;
6110 {
6111 if ((TARGET_64BIT || TARGET_GAS) && size == 8 && aligned_p)
6112 {
6113 fputs ("\t.dword\t", asm_out_file);
6114 if (HOST_BITS_PER_WIDE_INT < 64 || GET_CODE (x) != CONST_INT)
6115 output_addr_const (asm_out_file, x);
6116 else
6117 print_operand (asm_out_file, x, 'X');
6118 fputc ('\n', asm_out_file);
6119 return true;
6120 }
6121 return default_assemble_integer (x, size, aligned_p);
6122 }
6123
6124 /* If optimizing for the global pointer, keep track of all of the externs, so
6125 that at the end of the file, we can emit the appropriate .extern
6126 declaration for them, before writing out the text section. We assume all
6127 names passed to us are in the permanent obstack, so they will be valid at
6128 the end of the compilation.
6129
6130 If we have -G 0, or the extern size is unknown, or the object is in a user
6131 specified section that is not .sbss/.sdata, don't bother emitting the
6132 .externs. In the case of user specified sections this behavior is
6133 required as otherwise GAS will think the object lives in .sbss/.sdata. */
6134
6135 int
mips_output_external(file,decl,name)6136 mips_output_external (file, decl, name)
6137 FILE *file ATTRIBUTE_UNUSED;
6138 tree decl;
6139 const char *name;
6140 {
6141 register struct extern_list *p;
6142 int len;
6143 tree section_name;
6144
6145 if (TARGET_GP_OPT
6146 && TREE_CODE (decl) != FUNCTION_DECL
6147 && !DECL_COMDAT (decl)
6148 && (len = int_size_in_bytes (TREE_TYPE (decl))) > 0
6149 && ((section_name = DECL_SECTION_NAME (decl)) == NULL
6150 || strcmp (TREE_STRING_POINTER (section_name), ".sbss") == 0
6151 || strcmp (TREE_STRING_POINTER (section_name), ".sdata") == 0))
6152 {
6153 p = (struct extern_list *) xmalloc (sizeof (struct extern_list));
6154 p->next = extern_head;
6155 p->name = name;
6156 p->size = len;
6157 extern_head = p;
6158 }
6159
6160 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
6161 if (TREE_CODE (decl) == FUNCTION_DECL
6162 /* ??? Don't include alloca, since gcc will always expand it
6163 inline. If we don't do this, the C++ library fails to build. */
6164 && strcmp (name, "alloca")
6165 /* ??? Don't include __builtin_next_arg, because then gcc will not
6166 bootstrap under Irix 5.1. */
6167 && strcmp (name, "__builtin_next_arg"))
6168 {
6169 p = (struct extern_list *) xmalloc (sizeof (struct extern_list));
6170 p->next = extern_head;
6171 p->name = name;
6172 p->size = -1;
6173 extern_head = p;
6174 }
6175 #endif
6176
6177 return 0;
6178 }
6179
6180 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
6181 int
mips_output_external_libcall(file,name)6182 mips_output_external_libcall (file, name)
6183 FILE *file ATTRIBUTE_UNUSED;
6184 const char *name;
6185 {
6186 register struct extern_list *p;
6187
6188 p = (struct extern_list *) xmalloc (sizeof (struct extern_list));
6189 p->next = extern_head;
6190 p->name = name;
6191 p->size = -1;
6192 extern_head = p;
6193
6194 return 0;
6195 }
6196 #endif
6197
6198 /* Emit a new filename to a stream. If this is MIPS ECOFF, watch out
6199 for .file's that start within a function. If we are smuggling stabs, try to
6200 put out a MIPS ECOFF file and a stab. */
6201
6202 void
mips_output_filename(stream,name)6203 mips_output_filename (stream, name)
6204 FILE *stream;
6205 const char *name;
6206 {
6207 static int first_time = 1;
6208 char ltext_label_name[100];
6209
6210 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
6211 directives. */
6212 if (write_symbols == DWARF2_DEBUG)
6213 return;
6214 else if (first_time)
6215 {
6216 first_time = 0;
6217 SET_FILE_NUMBER ();
6218 current_function_file = name;
6219 ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
6220 /* This tells mips-tfile that stabs will follow. */
6221 if (!TARGET_GAS && write_symbols == DBX_DEBUG)
6222 fprintf (stream, "\t#@stabs\n");
6223 }
6224
6225 else if (write_symbols == DBX_DEBUG)
6226 {
6227 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name, "Ltext", 0);
6228 fprintf (stream, "%s", ASM_STABS_OP);
6229 output_quoted_string (stream, name);
6230 fprintf (stream, ",%d,0,0,%s\n", N_SOL, <ext_label_name[1]);
6231 }
6232
6233 else if (name != current_function_file
6234 && strcmp (name, current_function_file) != 0)
6235 {
6236 if (inside_function && !TARGET_GAS)
6237 {
6238 if (!file_in_function_warning)
6239 {
6240 file_in_function_warning = 1;
6241 ignore_line_number = 1;
6242 warning ("MIPS ECOFF format does not allow changing filenames within functions with #line");
6243 }
6244 }
6245 else
6246 {
6247 SET_FILE_NUMBER ();
6248 current_function_file = name;
6249 ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
6250 }
6251 }
6252 }
6253
6254 /* Emit a linenumber. For encapsulated stabs, we need to put out a stab
6255 as well as a .loc, since it is possible that MIPS ECOFF might not be
6256 able to represent the location for inlines that come from a different
6257 file. */
6258
6259 void
mips_output_lineno(stream,line)6260 mips_output_lineno (stream, line)
6261 FILE *stream;
6262 int line;
6263 {
6264 if (write_symbols == DBX_DEBUG)
6265 {
6266 ++sym_lineno;
6267 fprintf (stream, "%sLM%d:\n%s%d,0,%d,%sLM%d\n",
6268 LOCAL_LABEL_PREFIX, sym_lineno, ASM_STABN_OP, N_SLINE, line,
6269 LOCAL_LABEL_PREFIX, sym_lineno);
6270 }
6271 else
6272 {
6273 fprintf (stream, "\n\t%s.loc\t%d %d\n",
6274 (ignore_line_number) ? "#" : "",
6275 num_source_filenames, line);
6276
6277 LABEL_AFTER_LOC (stream);
6278 }
6279 }
6280
6281 /* Output an ASCII string, in a space-saving way. */
6282
6283 void
mips_output_ascii(stream,string_param,len)6284 mips_output_ascii (stream, string_param, len)
6285 FILE *stream;
6286 const char *string_param;
6287 size_t len;
6288 {
6289 size_t i;
6290 int cur_pos = 17;
6291 register const unsigned char *string =
6292 (const unsigned char *)string_param;
6293
6294 fprintf (stream, "\t.ascii\t\"");
6295 for (i = 0; i < len; i++)
6296 {
6297 register int c = string[i];
6298
6299 switch (c)
6300 {
6301 case '\"':
6302 case '\\':
6303 putc ('\\', stream);
6304 putc (c, stream);
6305 cur_pos += 2;
6306 break;
6307
6308 case TARGET_NEWLINE:
6309 fputs ("\\n", stream);
6310 if (i+1 < len
6311 && (((c = string[i+1]) >= '\040' && c <= '~')
6312 || c == TARGET_TAB))
6313 cur_pos = 32767; /* break right here */
6314 else
6315 cur_pos += 2;
6316 break;
6317
6318 case TARGET_TAB:
6319 fputs ("\\t", stream);
6320 cur_pos += 2;
6321 break;
6322
6323 case TARGET_FF:
6324 fputs ("\\f", stream);
6325 cur_pos += 2;
6326 break;
6327
6328 case TARGET_BS:
6329 fputs ("\\b", stream);
6330 cur_pos += 2;
6331 break;
6332
6333 case TARGET_CR:
6334 fputs ("\\r", stream);
6335 cur_pos += 2;
6336 break;
6337
6338 default:
6339 if (c >= ' ' && c < 0177)
6340 {
6341 putc (c, stream);
6342 cur_pos++;
6343 }
6344 else
6345 {
6346 fprintf (stream, "\\%03o", c);
6347 cur_pos += 4;
6348 }
6349 }
6350
6351 if (cur_pos > 72 && i+1 < len)
6352 {
6353 cur_pos = 17;
6354 fprintf (stream, "\"\n\t.ascii\t\"");
6355 }
6356 }
6357 fprintf (stream, "\"\n");
6358 }
6359
6360 /* If defined, a C statement to be executed just prior to the output of
6361 assembler code for INSN, to modify the extracted operands so they will be
6362 output differently.
6363
6364 Here the argument OPVEC is the vector containing the operands extracted
6365 from INSN, and NOPERANDS is the number of elements of the vector which
6366 contain meaningful data for this insn. The contents of this vector are
6367 what will be used to convert the insn template into assembler code, so you
6368 can change the assembler output by changing the contents of the vector.
6369
6370 We use it to check if the current insn needs a nop in front of it because
6371 of load delays, and also to update the delay slot statistics. */
6372
6373 /* ??? There is no real need for this function, because it never actually
6374 emits a NOP anymore. */
6375
6376 void
final_prescan_insn(insn,opvec,noperands)6377 final_prescan_insn (insn, opvec, noperands)
6378 rtx insn;
6379 rtx opvec[] ATTRIBUTE_UNUSED;
6380 int noperands ATTRIBUTE_UNUSED;
6381 {
6382 if (dslots_number_nops > 0)
6383 {
6384 rtx pattern = PATTERN (insn);
6385 int length = get_attr_length (insn);
6386
6387 /* Do we need to emit a NOP? */
6388 if (length == 0
6389 || (mips_load_reg != 0 && reg_mentioned_p (mips_load_reg, pattern))
6390 || (mips_load_reg2 != 0 && reg_mentioned_p (mips_load_reg2, pattern))
6391 || (mips_load_reg3 != 0 && reg_mentioned_p (mips_load_reg3, pattern))
6392 || (mips_load_reg4 != 0
6393 && reg_mentioned_p (mips_load_reg4, pattern)))
6394 fputs ("\t#nop\n", asm_out_file);
6395
6396 else
6397 dslots_load_filled++;
6398
6399 while (--dslots_number_nops > 0)
6400 fputs ("\t#nop\n", asm_out_file);
6401
6402 mips_load_reg = 0;
6403 mips_load_reg2 = 0;
6404 mips_load_reg3 = 0;
6405 mips_load_reg4 = 0;
6406 }
6407
6408 if (TARGET_STATS
6409 && (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CALL_INSN))
6410 dslots_jump_total++;
6411 }
6412
6413 /* Output at beginning of assembler file.
6414
6415 If we are optimizing to use the global pointer, create a temporary file to
6416 hold all of the text stuff, and write it out to the end. This is needed
6417 because the MIPS assembler is evidently one pass, and if it hasn't seen the
6418 relevant .comm/.lcomm/.extern/.sdata declaration when the code is
6419 processed, it generates a two instruction sequence. */
6420
6421 void
mips_asm_file_start(stream)6422 mips_asm_file_start (stream)
6423 FILE *stream;
6424 {
6425 ASM_OUTPUT_SOURCE_FILENAME (stream, main_input_filename);
6426
6427 /* Versions of the MIPS assembler before 2.20 generate errors if a branch
6428 inside of a .set noreorder section jumps to a label outside of the .set
6429 noreorder section. Revision 2.20 just set nobopt silently rather than
6430 fixing the bug. */
6431
6432 if (TARGET_MIPS_AS && optimize && flag_delayed_branch)
6433 fprintf (stream, "\t.set\tnobopt\n");
6434
6435 if (TARGET_GAS)
6436 {
6437 #if defined(OBJECT_FORMAT_ELF) && !(TARGET_IRIX5 || TARGET_IRIX6)
6438 /* Generate a special section to describe the ABI switches used to
6439 produce the resultant binary. This used to be done by the assembler
6440 setting bits in the ELF header's flags field, but we have run out of
6441 bits. GDB needs this information in order to be able to correctly
6442 debug these binaries. See the function mips_gdbarch_init() in
6443 gdb/mips-tdep.c. This is unnecessary for the IRIX 5/6 ABIs and
6444 causes unnecessary IRIX 6 ld warnings. */
6445 const char * abi_string = NULL;
6446
6447 switch (mips_abi)
6448 {
6449 case ABI_32: abi_string = "abi32"; break;
6450 case ABI_N32: abi_string = "abiN32"; break;
6451 case ABI_64: abi_string = "abi64"; break;
6452 case ABI_O64: abi_string = "abiO64"; break;
6453 case ABI_EABI: abi_string = TARGET_64BIT ? "eabi64" : "eabi32"; break;
6454 case ABI_MEABI:abi_string = TARGET_64BIT ? "meabi64" : "meabi32"; break;
6455 default:
6456 abort ();
6457 }
6458 /* Note - we use fprintf directly rather than called named_section()
6459 because in this way we can avoid creating an allocated section. We
6460 do not want this section to take up any space in the running
6461 executable. */
6462 fprintf (stream, "\t.section .mdebug.%s\n", abi_string);
6463
6464 /* Restore the default section. */
6465 fprintf (stream, "\t.previous\n");
6466 #endif
6467 }
6468
6469
6470
6471 /* Generate the pseudo ops that System V.4 wants. */
6472 #ifndef ABICALLS_ASM_OP
6473 #define ABICALLS_ASM_OP "\t.abicalls"
6474 #endif
6475 if (TARGET_ABICALLS)
6476 /* ??? but do not want this (or want pic0) if -non-shared? */
6477 fprintf (stream, "%s\n", ABICALLS_ASM_OP);
6478
6479 if (TARGET_MIPS16)
6480 fprintf (stream, "\t.set\tmips16\n");
6481
6482 /* This code exists so that we can put all externs before all symbol
6483 references. This is necessary for the MIPS assembler's global pointer
6484 optimizations to work. */
6485 if (TARGET_FILE_SWITCHING)
6486 {
6487 asm_out_data_file = stream;
6488 asm_out_text_file = tmpfile ();
6489 }
6490 else
6491 asm_out_data_file = asm_out_text_file = stream;
6492
6493 if (flag_verbose_asm)
6494 fprintf (stream, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
6495 ASM_COMMENT_START,
6496 mips_section_threshold, mips_arch_info->name, mips_isa);
6497 }
6498
6499 /* If we are optimizing the global pointer, emit the text section now and any
6500 small externs which did not have .comm, etc that are needed. Also, give a
6501 warning if the data area is more than 32K and -pic because 3 instructions
6502 are needed to reference the data pointers. */
6503
6504 void
mips_asm_file_end(file)6505 mips_asm_file_end (file)
6506 FILE *file;
6507 {
6508 tree name_tree;
6509 struct extern_list *p;
6510
6511 if (extern_head)
6512 {
6513 fputs ("\n", file);
6514
6515 for (p = extern_head; p != 0; p = p->next)
6516 {
6517 name_tree = get_identifier (p->name);
6518
6519 /* Positively ensure only one .extern for any given symbol. */
6520 if (! TREE_ASM_WRITTEN (name_tree))
6521 {
6522 TREE_ASM_WRITTEN (name_tree) = 1;
6523 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
6524 if (p->size == -1)
6525 ASM_OUTPUT_UNDEF_FUNCTION (file, p->name);
6526 else
6527 #endif
6528 {
6529 fputs ("\t.extern\t", file);
6530 assemble_name (file, p->name);
6531 fprintf (file, ", %d\n", p->size);
6532 }
6533 }
6534 }
6535 }
6536
6537 if (TARGET_FILE_SWITCHING)
6538 {
6539 fprintf (file, "\n\t.text\n");
6540 copy_file_data (file, asm_out_text_file);
6541 }
6542 }
6543
6544 static void
copy_file_data(to,from)6545 copy_file_data (to, from)
6546 FILE *to, *from;
6547 {
6548 char buffer[8192];
6549 size_t len;
6550 rewind (from);
6551 if (ferror (from))
6552 fatal_io_error ("can't rewind temp file");
6553
6554 while ((len = fread (buffer, 1, sizeof (buffer), from)) > 0)
6555 if (fwrite (buffer, 1, len, to) != len)
6556 fatal_io_error ("can't write to output file");
6557
6558 if (ferror (from))
6559 fatal_io_error ("can't read from temp file");
6560
6561 if (fclose (from))
6562 fatal_io_error ("can't close temp file");
6563 }
6564
6565 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as
6566 the elfos.h version, but we also need to handle -muninit-const-in-rodata
6567 and the limitations of the SGI o32 assembler. */
6568
6569 void
mips_output_aligned_decl_common(stream,decl,name,size,align)6570 mips_output_aligned_decl_common (stream, decl, name, size, align)
6571 FILE *stream;
6572 tree decl;
6573 const char *name;
6574 unsigned HOST_WIDE_INT size;
6575 unsigned int align;
6576 {
6577 const char *format;
6578
6579 /* If the target wants uninitialized const declarations in
6580 .rdata then don't put them in .comm. */
6581 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA
6582 && TREE_CODE (decl) == VAR_DECL && TREE_READONLY (decl)
6583 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
6584 {
6585 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
6586 targetm.asm_out.globalize_label (stream, name);
6587
6588 readonly_data_section ();
6589 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
6590
6591 format = ACONCAT ((":\n\t.space\t", HOST_WIDE_INT_PRINT_UNSIGNED,
6592 "\n", NULL));
6593 mips_declare_object (stream, name, "", format, size);
6594 }
6595 #ifdef TARGET_IRIX6
6596 /* The SGI o32 assembler doesn't accept an alignment, so round up
6597 the size instead. */
6598 else if (mips_abi == ABI_32 && !TARGET_GAS)
6599 {
6600 size += (align / BITS_PER_UNIT) - 1;
6601 size -= size % (align / BITS_PER_UNIT);
6602 format = ACONCAT ((",", HOST_WIDE_INT_PRINT_UNSIGNED, "\n", NULL));
6603 mips_declare_object (stream, name, "\n\t.comm\t", format, size);
6604 }
6605 #endif
6606 else
6607 {
6608 format = ACONCAT ((",", HOST_WIDE_INT_PRINT_UNSIGNED, ",%u\n", NULL));
6609 mips_declare_object (stream, name, "\n\t.comm\t", format,
6610 size, align / BITS_PER_UNIT);
6611 }
6612 }
6613
6614 /* Emit either a label, .comm, or .lcomm directive. When using assembler
6615 macros, mark the symbol as written so that mips_file_end won't emit an
6616 .extern for it. STREAM is the output file, NAME is the name of the
6617 symbol, INIT_STRING is the string that should be written before the
6618 symbol and FINAL_STRING is the string that shoulbe written after it.
6619 FINAL_STRING is a printf() format that consumes the remaining arguments. */
6620
6621 void
mips_declare_object(FILE * stream,const char * name,const char * init_string,const char * final_string,...)6622 mips_declare_object VPARAMS ((FILE *stream, const char *name,
6623 const char *init_string,
6624 const char *final_string, ...))
6625 {
6626 VA_OPEN (ap, final_string);
6627 VA_FIXEDARG (ap, FILE *, stream);
6628 VA_FIXEDARG (ap, const char *, name);
6629 VA_FIXEDARG (ap, const char *, init_string);
6630 VA_FIXEDARG (ap, const char *, final_string);
6631
6632 fputs (init_string, stream);
6633 assemble_name (stream, name);
6634 vfprintf (stream, final_string, ap);
6635
6636 if (TARGET_GP_OPT)
6637 {
6638 tree name_tree = get_identifier (name);
6639 TREE_ASM_WRITTEN (name_tree) = 1;
6640 }
6641
6642 VA_CLOSE (ap);
6643 }
6644
6645 /* Return the bytes needed to compute the frame pointer from the current
6646 stack pointer.
6647
6648 Mips stack frames look like:
6649
6650 Before call After call
6651 +-----------------------+ +-----------------------+
6652 high | | | |
6653 mem. | | | |
6654 | caller's temps. | | caller's temps. |
6655 | | | |
6656 +-----------------------+ +-----------------------+
6657 | | | |
6658 | arguments on stack. | | arguments on stack. |
6659 | | | |
6660 +-----------------------+ +-----------------------+
6661 | 4 words to save | | 4 words to save |
6662 | arguments passed | | arguments passed |
6663 | in registers, even | | in registers, even |
6664 SP->| if not passed. | VFP->| if not passed. |
6665 +-----------------------+ +-----------------------+
6666 | |
6667 | fp register save |
6668 | |
6669 +-----------------------+
6670 | |
6671 | gp register save |
6672 | |
6673 +-----------------------+
6674 | |
6675 | local variables |
6676 | |
6677 +-----------------------+
6678 | |
6679 | alloca allocations |
6680 | |
6681 +-----------------------+
6682 | |
6683 | GP save for V.4 abi |
6684 | |
6685 +-----------------------+
6686 | |
6687 | arguments on stack |
6688 | |
6689 +-----------------------+
6690 | 4 words to save |
6691 | arguments passed |
6692 | in registers, even |
6693 low SP->| if not passed. |
6694 memory +-----------------------+
6695
6696 */
6697
6698 HOST_WIDE_INT
compute_frame_size(size)6699 compute_frame_size (size)
6700 HOST_WIDE_INT size; /* # of var. bytes allocated */
6701 {
6702 unsigned int regno;
6703 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
6704 HOST_WIDE_INT var_size; /* # bytes that variables take up */
6705 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
6706 HOST_WIDE_INT extra_size; /* # extra bytes */
6707 HOST_WIDE_INT gp_reg_rounded; /* # bytes needed to store gp after rounding */
6708 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
6709 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
6710 long mask; /* mask of saved gp registers */
6711 long fmask; /* mask of saved fp registers */
6712 tree return_type;
6713
6714 gp_reg_size = 0;
6715 fp_reg_size = 0;
6716 mask = 0;
6717 fmask = 0;
6718 extra_size = MIPS_STACK_ALIGN (((TARGET_ABICALLS) ? UNITS_PER_WORD : 0));
6719 var_size = MIPS_STACK_ALIGN (size);
6720 args_size = MIPS_STACK_ALIGN (current_function_outgoing_args_size);
6721
6722 /* The MIPS 3.0 linker does not like functions that dynamically
6723 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
6724 looks like we are trying to create a second frame pointer to the
6725 function, so allocate some stack space to make it happy. */
6726
6727 if (args_size == 0 && current_function_calls_alloca)
6728 args_size = 4 * UNITS_PER_WORD;
6729
6730 total_size = var_size + args_size + extra_size;
6731 return_type = DECL_RESULT (current_function_decl);
6732
6733 /* Calculate space needed for gp registers. */
6734 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
6735 {
6736 /* $18 is a special case on the mips16. It may be used to call
6737 a function which returns a floating point value, but it is
6738 marked in call_used_regs. $31 is also a special case. When
6739 not using -mentry, it will be used to copy a return value
6740 into the floating point registers if the return value is
6741 floating point. */
6742 if (MUST_SAVE_REGISTER (regno)
6743 || (TARGET_MIPS16
6744 && regno == GP_REG_FIRST + 18
6745 && regs_ever_live[regno])
6746 || (TARGET_MIPS16
6747 && regno == GP_REG_FIRST + 31
6748 && mips16_hard_float
6749 && ! mips_entry
6750 && ! aggregate_value_p (return_type)
6751 && GET_MODE_CLASS (DECL_MODE (return_type)) == MODE_FLOAT
6752 && GET_MODE_SIZE (DECL_MODE (return_type)) <= UNITS_PER_FPVALUE))
6753 {
6754 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6755 mask |= 1L << (regno - GP_REG_FIRST);
6756
6757 /* The entry and exit pseudo instructions can not save $17
6758 without also saving $16. */
6759 if (mips_entry
6760 && regno == GP_REG_FIRST + 17
6761 && ! MUST_SAVE_REGISTER (GP_REG_FIRST + 16))
6762 {
6763 gp_reg_size += UNITS_PER_WORD;
6764 mask |= 1L << 16;
6765 }
6766 }
6767 }
6768
6769 /* We need to restore these for the handler. */
6770 if (current_function_calls_eh_return)
6771 {
6772 unsigned int i;
6773 for (i = 0; ; ++i)
6774 {
6775 regno = EH_RETURN_DATA_REGNO (i);
6776 if (regno == INVALID_REGNUM)
6777 break;
6778 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6779 mask |= 1L << (regno - GP_REG_FIRST);
6780 }
6781 }
6782
6783 /* This loop must iterate over the same space as its companion in
6784 save_restore_insns. */
6785 for (regno = (FP_REG_LAST - FP_INC + 1);
6786 regno >= FP_REG_FIRST;
6787 regno -= FP_INC)
6788 {
6789 if (regs_ever_live[regno] && !call_used_regs[regno])
6790 {
6791 fp_reg_size += FP_INC * UNITS_PER_FPREG;
6792 fmask |= ((1 << FP_INC) - 1) << (regno - FP_REG_FIRST);
6793 }
6794 }
6795
6796 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
6797 total_size += gp_reg_rounded + MIPS_STACK_ALIGN (fp_reg_size);
6798
6799 /* The gp reg is caller saved in the 32 bit ABI, so there is no need
6800 for leaf routines (total_size == extra_size) to save the gp reg.
6801 The gp reg is callee saved in the 64 bit ABI, so all routines must
6802 save the gp reg. This is not a leaf routine if -p, because of the
6803 call to mcount. */
6804 if (total_size == extra_size
6805 && (mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI)
6806 && ! current_function_profile)
6807 total_size = extra_size = 0;
6808 else if (TARGET_ABICALLS)
6809 {
6810 /* Add the context-pointer to the saved registers. */
6811 gp_reg_size += UNITS_PER_WORD;
6812 mask |= 1L << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST);
6813 total_size -= gp_reg_rounded;
6814 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
6815 total_size += gp_reg_rounded;
6816 }
6817
6818 /* Add in space reserved on the stack by the callee for storing arguments
6819 passed in registers. */
6820 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
6821 total_size += MIPS_STACK_ALIGN (current_function_pretend_args_size);
6822
6823 /* The entry pseudo instruction will allocate 32 bytes on the stack. */
6824 if (mips_entry && total_size > 0 && total_size < 32)
6825 total_size = 32;
6826
6827 /* Save other computed information. */
6828 cfun->machine->frame.total_size = total_size;
6829 cfun->machine->frame.var_size = var_size;
6830 cfun->machine->frame.args_size = args_size;
6831 cfun->machine->frame.extra_size = extra_size;
6832 cfun->machine->frame.gp_reg_size = gp_reg_size;
6833 cfun->machine->frame.fp_reg_size = fp_reg_size;
6834 cfun->machine->frame.mask = mask;
6835 cfun->machine->frame.fmask = fmask;
6836 cfun->machine->frame.initialized = reload_completed;
6837 cfun->machine->frame.num_gp = gp_reg_size / UNITS_PER_WORD;
6838 cfun->machine->frame.num_fp = fp_reg_size / (FP_INC * UNITS_PER_FPREG);
6839
6840 if (mask)
6841 {
6842 unsigned long offset;
6843
6844 /* When using mips_entry, the registers are always saved at the
6845 top of the stack. */
6846 if (! mips_entry)
6847 offset = (args_size + extra_size + var_size
6848 + gp_reg_size - GET_MODE_SIZE (gpr_mode));
6849 else
6850 offset = total_size - GET_MODE_SIZE (gpr_mode);
6851
6852 cfun->machine->frame.gp_sp_offset = offset;
6853 cfun->machine->frame.gp_save_offset = offset - total_size;
6854 }
6855 else
6856 {
6857 cfun->machine->frame.gp_sp_offset = 0;
6858 cfun->machine->frame.gp_save_offset = 0;
6859 }
6860
6861 if (fmask)
6862 {
6863 unsigned long offset = (args_size + extra_size + var_size
6864 + gp_reg_rounded + fp_reg_size
6865 - FP_INC * UNITS_PER_FPREG);
6866 cfun->machine->frame.fp_sp_offset = offset;
6867 cfun->machine->frame.fp_save_offset = offset - total_size;
6868 }
6869 else
6870 {
6871 cfun->machine->frame.fp_sp_offset = 0;
6872 cfun->machine->frame.fp_save_offset = 0;
6873 }
6874
6875 /* Ok, we're done. */
6876 return total_size;
6877 }
6878
6879 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame
6880 pointer, argument pointer, or return address pointer. TO is either
6881 the stack pointer or hard frame pointer. */
6882
6883 int
mips_initial_elimination_offset(from,to)6884 mips_initial_elimination_offset (from, to)
6885 int from, to;
6886 {
6887 int offset;
6888
6889 /* Set OFFSET to the offset from the stack pointer. */
6890 switch (from)
6891 {
6892 case FRAME_POINTER_REGNUM:
6893 offset = 0;
6894 break;
6895
6896 case ARG_POINTER_REGNUM:
6897 compute_frame_size (get_frame_size ());
6898 offset = cfun->machine->frame.total_size;
6899 if (mips_abi == ABI_N32 || mips_abi == ABI_64 || mips_abi == ABI_MEABI)
6900 offset -= current_function_pretend_args_size;
6901 break;
6902
6903 case RETURN_ADDRESS_POINTER_REGNUM:
6904 compute_frame_size (get_frame_size ());
6905 offset = cfun->machine->frame.gp_sp_offset;
6906 if (BYTES_BIG_ENDIAN)
6907 offset += UNITS_PER_WORD - (POINTER_SIZE / BITS_PER_UNIT);
6908 break;
6909
6910 default:
6911 abort ();
6912 }
6913
6914 if (TARGET_MIPS16 && to == HARD_FRAME_POINTER_REGNUM)
6915 offset -= current_function_outgoing_args_size;
6916
6917 return offset;
6918 }
6919
6920 /* Common code to emit the insns (or to write the instructions to a file)
6921 to save/restore registers.
6922
6923 Other parts of the code assume that MIPS_TEMP1_REGNUM (aka large_reg)
6924 is not modified within save_restore_insns. */
6925
6926 #define BITSET_P(VALUE,BIT) (((VALUE) & (1L << (BIT))) != 0)
6927
6928 /* Emit instructions to load the value (SP + OFFSET) into MIPS_TEMP2_REGNUM
6929 and return an rtl expression for the register.
6930
6931 This function is a subroutine of save_restore_insns. It is used when
6932 OFFSET is too large to add in a single instruction. */
6933
6934 static rtx
mips_add_large_offset_to_sp(offset)6935 mips_add_large_offset_to_sp (offset)
6936 HOST_WIDE_INT offset;
6937 {
6938 rtx reg = gen_rtx_REG (Pmode, MIPS_TEMP2_REGNUM);
6939 rtx offset_rtx = GEN_INT (offset);
6940
6941 emit_move_insn (reg, offset_rtx);
6942 if (Pmode == DImode)
6943 emit_insn (gen_adddi3 (reg, reg, stack_pointer_rtx));
6944 else
6945 emit_insn (gen_addsi3 (reg, reg, stack_pointer_rtx));
6946 return reg;
6947 }
6948
6949 /* Make INSN frame related and note that it performs the frame-related
6950 operation DWARF_PATTERN. */
6951
6952 static void
mips_annotate_frame_insn(insn,dwarf_pattern)6953 mips_annotate_frame_insn (insn, dwarf_pattern)
6954 rtx insn, dwarf_pattern;
6955 {
6956 RTX_FRAME_RELATED_P (insn) = 1;
6957 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
6958 dwarf_pattern,
6959 REG_NOTES (insn));
6960 }
6961
6962 /* Return a frame-related rtx that stores register REGNO at (SP + OFFSET).
6963 The expression should only be used to store single registers. */
6964
6965 static rtx
mips_frame_set(mode,regno,offset)6966 mips_frame_set (mode, regno, offset)
6967 enum machine_mode mode;
6968 int regno;
6969 int offset;
6970 {
6971 rtx address = plus_constant (stack_pointer_rtx, offset);
6972 rtx set = gen_rtx_SET (mode,
6973 gen_rtx_MEM (mode, address),
6974 gen_rtx_REG (mode, regno));
6975 RTX_FRAME_RELATED_P (set) = 1;
6976 return set;
6977 }
6978
6979
6980 /* Emit a move instruction that stores REG in MEM. Make the instruction
6981 frame related and note that it stores REG at (SP + OFFSET). This
6982 function may be asked to store an FPR pair. */
6983
6984 static void
mips_emit_frame_related_store(mem,reg,offset)6985 mips_emit_frame_related_store (mem, reg, offset)
6986 rtx mem;
6987 rtx reg;
6988 HOST_WIDE_INT offset;
6989 {
6990 rtx dwarf_expr;
6991
6992 if (GET_MODE (reg) == DFmode && ! TARGET_FLOAT64)
6993 {
6994 /* Two registers are being stored, so the frame-related expression
6995 must be a PARALLEL rtx with one SET for each register. The
6996 higher numbered register is stored in the lower address on
6997 big-endian targets. */
6998 int regno1 = TARGET_BIG_ENDIAN ? REGNO (reg) + 1 : REGNO (reg);
6999 int regno2 = TARGET_BIG_ENDIAN ? REGNO (reg) : REGNO (reg) + 1;
7000 rtx set1 = mips_frame_set (SFmode, regno1, offset);
7001 rtx set2 = mips_frame_set (SFmode, regno2, offset + UNITS_PER_FPREG);
7002 dwarf_expr = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set1, set2));
7003 }
7004 else
7005 dwarf_expr = mips_frame_set (GET_MODE (reg), REGNO (reg), offset);
7006
7007 mips_annotate_frame_insn (emit_move_insn (mem, reg), dwarf_expr);
7008 }
7009
7010 static void
save_restore_insns(store_p,large_reg,large_offset)7011 save_restore_insns (store_p, large_reg, large_offset)
7012 int store_p; /* true if this is prologue */
7013 rtx large_reg; /* register holding large offset constant or NULL */
7014 long large_offset; /* large constant offset value */
7015 {
7016 long mask = cfun->machine->frame.mask;
7017 long fmask = cfun->machine->frame.fmask;
7018 long real_mask = mask;
7019 int regno;
7020 rtx base_reg_rtx;
7021 HOST_WIDE_INT base_offset;
7022 HOST_WIDE_INT gp_offset;
7023 HOST_WIDE_INT fp_offset;
7024 HOST_WIDE_INT end_offset;
7025 rtx insn;
7026
7027 if (frame_pointer_needed
7028 && ! BITSET_P (mask, HARD_FRAME_POINTER_REGNUM - GP_REG_FIRST))
7029 abort ();
7030
7031 /* Do not restore GP under certain conditions. */
7032 if (! store_p
7033 && TARGET_ABICALLS
7034 && (mips_abi == ABI_32 || mips_abi == ABI_O64))
7035 mask &= ~(1L << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST));
7036
7037 if (mask == 0 && fmask == 0)
7038 return;
7039
7040 /* Save registers starting from high to low. The debuggers prefer at least
7041 the return register be stored at func+4, and also it allows us not to
7042 need a nop in the epilog if at least one register is reloaded in
7043 addition to return address. */
7044
7045 /* Save GP registers if needed. */
7046 if (mask)
7047 {
7048 /* Pick which pointer to use as a base register. For small frames, just
7049 use the stack pointer. Otherwise, use a temporary register. Save 2
7050 cycles if the save area is near the end of a large frame, by reusing
7051 the constant created in the prologue/epilogue to adjust the stack
7052 frame. */
7053
7054 gp_offset = cfun->machine->frame.gp_sp_offset;
7055 end_offset
7056 = gp_offset - (cfun->machine->frame.gp_reg_size
7057 - GET_MODE_SIZE (gpr_mode));
7058
7059 if (gp_offset < 0 || end_offset < 0)
7060 internal_error
7061 ("gp_offset (%ld) or end_offset (%ld) is less than zero",
7062 (long) gp_offset, (long) end_offset);
7063
7064 /* If we see a large frame in mips16 mode, we save the registers
7065 before adjusting the stack pointer, and load them afterward. */
7066 else if (TARGET_MIPS16 && large_offset > 32767)
7067 base_reg_rtx = stack_pointer_rtx, base_offset = large_offset;
7068
7069 else if (gp_offset < 32768)
7070 base_reg_rtx = stack_pointer_rtx, base_offset = 0;
7071
7072 else if (large_reg != 0
7073 && (unsigned HOST_WIDE_INT) (large_offset - gp_offset) < 32768
7074 && (unsigned HOST_WIDE_INT) (large_offset - end_offset) < 32768)
7075 {
7076 base_reg_rtx = gen_rtx_REG (Pmode, MIPS_TEMP2_REGNUM);
7077 base_offset = large_offset;
7078 if (Pmode == DImode)
7079 insn = emit_insn (gen_adddi3 (base_reg_rtx, large_reg,
7080 stack_pointer_rtx));
7081 else
7082 insn = emit_insn (gen_addsi3 (base_reg_rtx, large_reg,
7083 stack_pointer_rtx));
7084 }
7085 else
7086 {
7087 base_offset = gp_offset;
7088 base_reg_rtx = mips_add_large_offset_to_sp (base_offset);
7089 }
7090
7091 /* When we restore the registers in MIPS16 mode, then if we are
7092 using a frame pointer, and this is not a large frame, the
7093 current stack pointer will be offset by
7094 current_function_outgoing_args_size. Doing it this way lets
7095 us avoid offsetting the frame pointer before copying it into
7096 the stack pointer; there is no instruction to set the stack
7097 pointer to the sum of a register and a constant. */
7098 if (TARGET_MIPS16
7099 && ! store_p
7100 && frame_pointer_needed
7101 && large_offset <= 32767)
7102 base_offset += current_function_outgoing_args_size;
7103
7104 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
7105 {
7106 if (BITSET_P (mask, regno - GP_REG_FIRST))
7107 {
7108 rtx reg_rtx;
7109 rtx mem_rtx
7110 = gen_rtx (MEM, gpr_mode,
7111 gen_rtx (PLUS, Pmode, base_reg_rtx,
7112 GEN_INT (gp_offset - base_offset)));
7113
7114 if (! current_function_calls_eh_return)
7115 RTX_UNCHANGING_P (mem_rtx) = 1;
7116
7117 /* The mips16 does not have an instruction to load
7118 $31, so we load $7 instead, and work things out
7119 in mips_expand_epilogue. */
7120 if (TARGET_MIPS16 && ! store_p && regno == GP_REG_FIRST + 31)
7121 reg_rtx = gen_rtx (REG, gpr_mode, GP_REG_FIRST + 7);
7122 /* The mips16 sometimes needs to save $18. */
7123 else if (TARGET_MIPS16
7124 && regno != GP_REG_FIRST + 31
7125 && ! M16_REG_P (regno))
7126 {
7127 if (! store_p)
7128 reg_rtx = gen_rtx (REG, gpr_mode, 6);
7129 else
7130 {
7131 reg_rtx = gen_rtx (REG, gpr_mode, 3);
7132 emit_move_insn (reg_rtx,
7133 gen_rtx (REG, gpr_mode, regno));
7134 }
7135 }
7136 else
7137 reg_rtx = gen_rtx (REG, gpr_mode, regno);
7138
7139 if (store_p)
7140 mips_emit_frame_related_store (mem_rtx, reg_rtx, gp_offset);
7141 else
7142 {
7143 emit_move_insn (reg_rtx, mem_rtx);
7144 if (TARGET_MIPS16
7145 && regno != GP_REG_FIRST + 31
7146 && ! M16_REG_P (regno))
7147 emit_move_insn (gen_rtx (REG, gpr_mode, regno),
7148 reg_rtx);
7149 }
7150 }
7151 /* If the restore is being supressed, still take into account
7152 the offset at which it is stored. */
7153 if (BITSET_P (real_mask, regno - GP_REG_FIRST))
7154 gp_offset -= GET_MODE_SIZE (gpr_mode);
7155 }
7156 }
7157 else
7158 base_reg_rtx = 0, base_offset = 0;
7159
7160 /* Save floating point registers if needed. */
7161 if (fmask)
7162 {
7163 /* Pick which pointer to use as a base register. */
7164 fp_offset = cfun->machine->frame.fp_sp_offset;
7165 end_offset = fp_offset - (cfun->machine->frame.fp_reg_size
7166 - UNITS_PER_HWFPVALUE);
7167
7168 if (fp_offset < 0 || end_offset < 0)
7169 internal_error
7170 ("fp_offset (%ld) or end_offset (%ld) is less than zero",
7171 (long) fp_offset, (long) end_offset);
7172
7173 else if (fp_offset < 32768)
7174 base_reg_rtx = stack_pointer_rtx, base_offset = 0;
7175
7176 else if (base_reg_rtx != 0
7177 && (unsigned HOST_WIDE_INT) (base_offset - fp_offset) < 32768
7178 && (unsigned HOST_WIDE_INT) (base_offset - end_offset) < 32768)
7179 ; /* already set up for gp registers above */
7180
7181 else if (large_reg != 0
7182 && (unsigned HOST_WIDE_INT) (large_offset - fp_offset) < 32768
7183 && (unsigned HOST_WIDE_INT) (large_offset - end_offset) < 32768)
7184 {
7185 base_reg_rtx = gen_rtx_REG (Pmode, MIPS_TEMP2_REGNUM);
7186 base_offset = large_offset;
7187 if (Pmode == DImode)
7188 insn = emit_insn (gen_adddi3 (base_reg_rtx, large_reg,
7189 stack_pointer_rtx));
7190 else
7191 insn = emit_insn (gen_addsi3 (base_reg_rtx, large_reg,
7192 stack_pointer_rtx));
7193 }
7194 else
7195 {
7196 base_offset = fp_offset;
7197 base_reg_rtx = mips_add_large_offset_to_sp (fp_offset);
7198 }
7199
7200 /* This loop must iterate over the same space as its companion in
7201 compute_frame_size. */
7202 for (regno = (FP_REG_LAST - FP_INC + 1);
7203 regno >= FP_REG_FIRST;
7204 regno -= FP_INC)
7205 if (BITSET_P (fmask, regno - FP_REG_FIRST))
7206 {
7207 enum machine_mode sz = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
7208 rtx reg_rtx = gen_rtx (REG, sz, regno);
7209 rtx mem_rtx = gen_rtx (MEM, sz,
7210 gen_rtx (PLUS, Pmode, base_reg_rtx,
7211 GEN_INT (fp_offset
7212 - base_offset)));
7213 if (! current_function_calls_eh_return)
7214 RTX_UNCHANGING_P (mem_rtx) = 1;
7215
7216 if (store_p)
7217 mips_emit_frame_related_store (mem_rtx, reg_rtx, fp_offset);
7218 else
7219 emit_move_insn (reg_rtx, mem_rtx);
7220
7221 fp_offset -= UNITS_PER_HWFPVALUE;
7222 }
7223 }
7224 }
7225
7226 /* Set up the stack and frame (if desired) for the function. */
7227
7228 static void
mips_output_function_prologue(file,size)7229 mips_output_function_prologue (file, size)
7230 FILE *file;
7231 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
7232 {
7233 #ifndef FUNCTION_NAME_ALREADY_DECLARED
7234 const char *fnname;
7235 #endif
7236 HOST_WIDE_INT tsize = cfun->machine->frame.total_size;
7237
7238 /* ??? When is this really needed? At least the GNU assembler does not
7239 need the source filename more than once in the file, beyond what is
7240 emitted by the debug information. */
7241 if (!TARGET_GAS)
7242 ASM_OUTPUT_SOURCE_FILENAME (file, DECL_SOURCE_FILE (current_function_decl));
7243
7244 #ifdef SDB_DEBUGGING_INFO
7245 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
7246 ASM_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
7247 #endif
7248
7249 /* In mips16 mode, we may need to generate a 32 bit to handle
7250 floating point arguments. The linker will arrange for any 32 bit
7251 functions to call this stub, which will then jump to the 16 bit
7252 function proper. */
7253 if (TARGET_MIPS16 && !TARGET_SOFT_FLOAT
7254 && current_function_args_info.fp_code != 0)
7255 build_mips16_function_stub (file);
7256
7257 inside_function = 1;
7258
7259 #ifndef FUNCTION_NAME_ALREADY_DECLARED
7260 /* Get the function name the same way that toplev.c does before calling
7261 assemble_start_function. This is needed so that the name used here
7262 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
7263 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
7264
7265 if (!flag_inhibit_size_directive)
7266 {
7267 fputs ("\t.ent\t", file);
7268 assemble_name (file, fnname);
7269 fputs ("\n", file);
7270 }
7271
7272 assemble_name (file, fnname);
7273 fputs (":\n", file);
7274 #endif
7275
7276 if (!flag_inhibit_size_directive)
7277 {
7278 /* .frame FRAMEREG, FRAMESIZE, RETREG */
7279 fprintf (file,
7280 "\t.frame\t%s,%ld,%s\t\t# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n",
7281 (reg_names[(frame_pointer_needed)
7282 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM]),
7283 ((frame_pointer_needed && TARGET_MIPS16)
7284 ? ((long) tsize - current_function_outgoing_args_size)
7285 : (long) tsize),
7286 reg_names[GP_REG_FIRST + 31],
7287 cfun->machine->frame.var_size,
7288 cfun->machine->frame.num_gp,
7289 cfun->machine->frame.num_fp,
7290 current_function_outgoing_args_size,
7291 cfun->machine->frame.extra_size);
7292
7293 /* .mask MASK, GPOFFSET; .fmask FPOFFSET */
7294 fprintf (file, "\t.mask\t0x%08lx,%ld\n\t.fmask\t0x%08lx,%ld\n",
7295 cfun->machine->frame.mask,
7296 cfun->machine->frame.gp_save_offset,
7297 cfun->machine->frame.fmask,
7298 cfun->machine->frame.fp_save_offset);
7299
7300 /* Require:
7301 OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
7302 HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
7303 }
7304
7305 if (mips_entry && ! mips_can_use_return_insn ())
7306 {
7307 int save16 = BITSET_P (cfun->machine->frame.mask, 16);
7308 int save17 = BITSET_P (cfun->machine->frame.mask, 17);
7309 int save31 = BITSET_P (cfun->machine->frame.mask, 31);
7310 int savearg = 0;
7311 rtx insn;
7312
7313 /* Look through the initial insns to see if any of them store
7314 the function parameters into the incoming parameter storage
7315 area. If they do, we delete the insn, and save the register
7316 using the entry pseudo-instruction instead. We don't try to
7317 look past a label, jump, or call. */
7318 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
7319 {
7320 rtx note, set, src, dest, base, offset;
7321 int hireg;
7322
7323 if (GET_CODE (insn) == CODE_LABEL
7324 || GET_CODE (insn) == JUMP_INSN
7325 || GET_CODE (insn) == CALL_INSN)
7326 break;
7327 if (GET_CODE (insn) != INSN)
7328 continue;
7329 set = PATTERN (insn);
7330 if (GET_CODE (set) != SET)
7331 continue;
7332
7333 /* An insn storing a function parameter will still have a
7334 REG_EQUIV note on it mentioning the argument pointer. */
7335 note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
7336 if (note == NULL_RTX)
7337 continue;
7338 if (! reg_mentioned_p (arg_pointer_rtx, XEXP (note, 0)))
7339 continue;
7340
7341 src = SET_SRC (set);
7342 if (GET_CODE (src) != REG
7343 || REGNO (src) < GP_REG_FIRST + 4
7344 || REGNO (src) > GP_REG_FIRST + 7)
7345 continue;
7346
7347 dest = SET_DEST (set);
7348 if (GET_CODE (dest) != MEM)
7349 continue;
7350 if (GET_MODE_SIZE (GET_MODE (dest)) == (unsigned) UNITS_PER_WORD)
7351 ;
7352 else if (GET_MODE_SIZE (GET_MODE (dest)) == (unsigned)2 * UNITS_PER_WORD
7353 && REGNO (src) < GP_REG_FIRST + 7)
7354 ;
7355 else
7356 continue;
7357 offset = const0_rtx;
7358 base = eliminate_constant_term (XEXP (dest, 0), &offset);
7359 if (GET_CODE (base) != REG
7360 || GET_CODE (offset) != CONST_INT)
7361 continue;
7362 if (REGNO (base) == (unsigned) STACK_POINTER_REGNUM
7363 && INTVAL (offset) == tsize + (REGNO (src) - 4) * UNITS_PER_WORD)
7364 ;
7365 else if (REGNO (base) == (unsigned) HARD_FRAME_POINTER_REGNUM
7366 && (INTVAL (offset)
7367 == (tsize
7368 + (REGNO (src) - 4) * UNITS_PER_WORD
7369 - current_function_outgoing_args_size)))
7370 ;
7371 else
7372 continue;
7373
7374 /* This insn stores a parameter onto the stack, in the same
7375 location where the entry pseudo-instruction will put it.
7376 Delete the insn, and arrange to tell the entry
7377 instruction to save the register. */
7378 PUT_CODE (insn, NOTE);
7379 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
7380 NOTE_SOURCE_FILE (insn) = 0;
7381
7382 hireg = (REGNO (src)
7383 + HARD_REGNO_NREGS (REGNO (src), GET_MODE (dest))
7384 - 1);
7385 if (hireg > savearg)
7386 savearg = hireg;
7387 }
7388
7389 /* If this is a varargs function, we need to save all the
7390 registers onto the stack anyhow. */
7391 if (current_function_stdarg)
7392 savearg = GP_REG_FIRST + 7;
7393
7394 fprintf (file, "\tentry\t");
7395 if (savearg > 0)
7396 {
7397 if (savearg == GP_REG_FIRST + 4)
7398 fprintf (file, "%s", reg_names[savearg]);
7399 else
7400 fprintf (file, "%s-%s", reg_names[GP_REG_FIRST + 4],
7401 reg_names[savearg]);
7402 }
7403 if (save16 || save17)
7404 {
7405 if (savearg > 0)
7406 fprintf (file, ",");
7407 fprintf (file, "%s", reg_names[GP_REG_FIRST + 16]);
7408 if (save17)
7409 fprintf (file, "-%s", reg_names[GP_REG_FIRST + 17]);
7410 }
7411 if (save31)
7412 {
7413 if (savearg > 0 || save16 || save17)
7414 fprintf (file, ",");
7415 fprintf (file, "%s", reg_names[GP_REG_FIRST + 31]);
7416 }
7417 fprintf (file, "\n");
7418 }
7419
7420 if (TARGET_ABICALLS && (mips_abi == ABI_32 || mips_abi == ABI_O64))
7421 {
7422 const char *const sp_str = reg_names[STACK_POINTER_REGNUM];
7423
7424 fprintf (file, "\t.set\tnoreorder\n\t.cpload\t%s\n\t.set\treorder\n",
7425 reg_names[PIC_FUNCTION_ADDR_REGNUM]);
7426 if (tsize > 0)
7427 {
7428 fprintf (file, "\t%s\t%s,%s,%ld\n",
7429 (Pmode == DImode ? "dsubu" : "subu"),
7430 sp_str, sp_str, (long) tsize);
7431 fprintf (file, "\t.cprestore %ld\n", cfun->machine->frame.args_size);
7432 }
7433
7434 if (dwarf2out_do_frame ())
7435 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, tsize);
7436 }
7437 }
7438
7439 /* Expand the prologue into a bunch of separate insns. */
7440
7441 void
mips_expand_prologue()7442 mips_expand_prologue ()
7443 {
7444 int regno;
7445 HOST_WIDE_INT tsize;
7446 rtx tmp_rtx = 0;
7447 int last_arg_is_vararg_marker = 0;
7448 tree fndecl = current_function_decl;
7449 tree fntype = TREE_TYPE (fndecl);
7450 tree fnargs = DECL_ARGUMENTS (fndecl);
7451 rtx next_arg_reg;
7452 int i;
7453 tree next_arg;
7454 tree cur_arg;
7455 CUMULATIVE_ARGS args_so_far;
7456 rtx reg_18_save = NULL_RTX;
7457 int store_args_on_stack = (mips_abi == ABI_32 || mips_abi == ABI_O64)
7458 && (! mips_entry || mips_can_use_return_insn ());
7459
7460 /* If struct value address is treated as the first argument, make it so. */
7461 if (aggregate_value_p (DECL_RESULT (fndecl))
7462 && ! current_function_returns_pcc_struct
7463 && struct_value_incoming_rtx == 0)
7464 {
7465 tree type = build_pointer_type (fntype);
7466 tree function_result_decl = build_decl (PARM_DECL, NULL_TREE, type);
7467
7468 DECL_ARG_TYPE (function_result_decl) = type;
7469 TREE_CHAIN (function_result_decl) = fnargs;
7470 fnargs = function_result_decl;
7471 }
7472
7473 /* For arguments passed in registers, find the register number
7474 of the first argument in the variable part of the argument list,
7475 otherwise GP_ARG_LAST+1. Note also if the last argument is
7476 the varargs special argument, and treat it as part of the
7477 variable arguments.
7478
7479 This is only needed if store_args_on_stack is true. */
7480
7481 INIT_CUMULATIVE_ARGS (args_so_far, fntype, NULL_RTX, 0);
7482 regno = GP_ARG_FIRST;
7483
7484 for (cur_arg = fnargs; cur_arg != 0; cur_arg = next_arg)
7485 {
7486 tree passed_type = DECL_ARG_TYPE (cur_arg);
7487 enum machine_mode passed_mode = TYPE_MODE (passed_type);
7488 rtx entry_parm;
7489
7490 if (TREE_ADDRESSABLE (passed_type))
7491 {
7492 passed_type = build_pointer_type (passed_type);
7493 passed_mode = Pmode;
7494 }
7495
7496 entry_parm = FUNCTION_ARG (args_so_far, passed_mode, passed_type, 1);
7497
7498 FUNCTION_ARG_ADVANCE (args_so_far, passed_mode, passed_type, 1);
7499 next_arg = TREE_CHAIN (cur_arg);
7500
7501 if (entry_parm && store_args_on_stack)
7502 {
7503 if (next_arg == 0
7504 && DECL_NAME (cur_arg)
7505 && ((0 == strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)),
7506 "__builtin_va_alist"))
7507 || (0 == strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)),
7508 "va_alist"))))
7509 {
7510 last_arg_is_vararg_marker = 1;
7511 if (GET_CODE (entry_parm) == REG)
7512 regno = REGNO (entry_parm);
7513 else
7514 regno = GP_ARG_LAST + 1;
7515 break;
7516 }
7517 else
7518 regno = GP_ARG_FIRST + args_so_far.num_gprs;
7519 }
7520 else
7521 {
7522 regno = GP_ARG_LAST+1;
7523 break;
7524 }
7525 }
7526
7527 /* In order to pass small structures by value in registers compatibly with
7528 the MIPS compiler, we need to shift the value into the high part of the
7529 register. Function_arg has encoded a PARALLEL rtx, holding a vector of
7530 adjustments to be made as the next_arg_reg variable, so we split up the
7531 insns, and emit them separately. */
7532
7533 next_arg_reg = FUNCTION_ARG (args_so_far, VOIDmode, void_type_node, 1);
7534 if (next_arg_reg != 0 && GET_CODE (next_arg_reg) == PARALLEL)
7535 {
7536 rtvec adjust = XVEC (next_arg_reg, 0);
7537 int num = GET_NUM_ELEM (adjust);
7538
7539 for (i = 0; i < num; i++)
7540 {
7541 rtx insn, pattern;
7542
7543 pattern = RTVEC_ELT (adjust, i);
7544 if (GET_CODE (pattern) != SET
7545 || GET_CODE (SET_SRC (pattern)) != ASHIFT)
7546 abort_with_insn (pattern, "insn is not a shift");
7547 PUT_CODE (SET_SRC (pattern), ASHIFTRT);
7548
7549 insn = emit_insn (pattern);
7550
7551 /* Global life information isn't valid at this point, so we
7552 can't check whether these shifts are actually used. Mark
7553 them MAYBE_DEAD so that flow2 will remove them, and not
7554 complain about dead code in the prologue. */
7555 REG_NOTES(insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, NULL_RTX,
7556 REG_NOTES (insn));
7557 }
7558 }
7559
7560 tsize = compute_frame_size (get_frame_size ());
7561
7562 if (warn_stack_larger_than
7563 && cfun->machine->frame.var_size > stack_larger_than_size)
7564 warning ("stack usage is %d bytes", cfun->machine->frame.var_size);
7565
7566 /* If this function is a varargs function, store any registers that
7567 would normally hold arguments ($4 - $7) on the stack. */
7568 if (store_args_on_stack
7569 && ((TYPE_ARG_TYPES (fntype) != 0
7570 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
7571 != void_type_node))
7572 || last_arg_is_vararg_marker))
7573 {
7574 int offset = (regno - GP_ARG_FIRST) * UNITS_PER_WORD;
7575 rtx ptr = stack_pointer_rtx;
7576
7577 /* If we are doing svr4-abi, sp has already been decremented by tsize. */
7578 if (TARGET_ABICALLS)
7579 offset += tsize;
7580
7581 for (; regno <= GP_ARG_LAST; regno++)
7582 {
7583 if (offset != 0)
7584 ptr = gen_rtx (PLUS, Pmode, stack_pointer_rtx, GEN_INT (offset));
7585 emit_move_insn (gen_rtx (MEM, gpr_mode, ptr),
7586 gen_rtx (REG, gpr_mode, regno));
7587
7588 offset += GET_MODE_SIZE (gpr_mode);
7589 }
7590 }
7591
7592 /* If we are using the entry pseudo instruction, it will
7593 automatically subtract 32 from the stack pointer, so we don't
7594 need to. The entry pseudo instruction is emitted by
7595 function_prologue. */
7596 if (mips_entry && ! mips_can_use_return_insn ())
7597 {
7598 if (tsize > 0 && tsize <= 32 && frame_pointer_needed)
7599 {
7600 rtx insn;
7601
7602 /* If we are using a frame pointer with a small stack frame,
7603 we need to initialize it here since it won't be done
7604 below. */
7605 if (TARGET_MIPS16 && current_function_outgoing_args_size != 0)
7606 {
7607 rtx incr = GEN_INT (current_function_outgoing_args_size);
7608 if (Pmode == DImode)
7609 insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
7610 stack_pointer_rtx,
7611 incr));
7612 else
7613 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
7614 stack_pointer_rtx,
7615 incr));
7616 }
7617 else if (Pmode == DImode)
7618 insn = emit_insn (gen_movdi (hard_frame_pointer_rtx,
7619 stack_pointer_rtx));
7620 else
7621 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx,
7622 stack_pointer_rtx));
7623
7624 RTX_FRAME_RELATED_P (insn) = 1;
7625 }
7626
7627 /* We may need to save $18, if it is used to call a function
7628 which may return a floating point value. Set up a sequence
7629 of instructions to do so. Later on we emit them at the right
7630 moment. */
7631 if (TARGET_MIPS16 && BITSET_P (cfun->machine->frame.mask, 18))
7632 {
7633 rtx reg_rtx = gen_rtx (REG, gpr_mode, GP_REG_FIRST + 3);
7634 long gp_offset, base_offset;
7635
7636 gp_offset = cfun->machine->frame.gp_sp_offset;
7637 if (BITSET_P (cfun->machine->frame.mask, 16))
7638 gp_offset -= UNITS_PER_WORD;
7639 if (BITSET_P (cfun->machine->frame.mask, 17))
7640 gp_offset -= UNITS_PER_WORD;
7641 if (BITSET_P (cfun->machine->frame.mask, 31))
7642 gp_offset -= UNITS_PER_WORD;
7643 if (tsize > 32767)
7644 base_offset = tsize;
7645 else
7646 base_offset = 0;
7647 start_sequence ();
7648 emit_move_insn (reg_rtx,
7649 gen_rtx (REG, gpr_mode, GP_REG_FIRST + 18));
7650 emit_move_insn (gen_rtx (MEM, gpr_mode,
7651 gen_rtx (PLUS, Pmode, stack_pointer_rtx,
7652 GEN_INT (gp_offset
7653 - base_offset))),
7654 reg_rtx);
7655 reg_18_save = get_insns ();
7656 end_sequence ();
7657 }
7658
7659 if (tsize > 32)
7660 tsize -= 32;
7661 else
7662 {
7663 tsize = 0;
7664 if (reg_18_save != NULL_RTX)
7665 emit_insn (reg_18_save);
7666 }
7667 }
7668
7669 if (tsize > 0)
7670 {
7671 rtx tsize_rtx = GEN_INT (tsize);
7672
7673 /* If we are doing svr4-abi, sp move is done by
7674 function_prologue. In mips16 mode with a large frame, we
7675 save the registers before adjusting the stack. */
7676 if ((!TARGET_ABICALLS || (mips_abi != ABI_32 && mips_abi != ABI_O64))
7677 && (!TARGET_MIPS16 || tsize <= 32767))
7678 {
7679 rtx adjustment_rtx, insn, dwarf_pattern;
7680
7681 if (tsize > 32767)
7682 {
7683 adjustment_rtx = gen_rtx (REG, Pmode, MIPS_TEMP1_REGNUM);
7684 emit_move_insn (adjustment_rtx, tsize_rtx);
7685 }
7686 else
7687 adjustment_rtx = tsize_rtx;
7688
7689 if (Pmode == DImode)
7690 insn = emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx,
7691 adjustment_rtx));
7692 else
7693 insn = emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
7694 adjustment_rtx));
7695
7696 dwarf_pattern = gen_rtx_SET (Pmode, stack_pointer_rtx,
7697 plus_constant (stack_pointer_rtx,
7698 -tsize));
7699
7700 mips_annotate_frame_insn (insn, dwarf_pattern);
7701 }
7702
7703 if (! mips_entry)
7704 save_restore_insns (1, tmp_rtx, tsize);
7705 else if (reg_18_save != NULL_RTX)
7706 emit_insn (reg_18_save);
7707
7708 if ((!TARGET_ABICALLS || (mips_abi != ABI_32 && mips_abi != ABI_O64))
7709 && TARGET_MIPS16
7710 && tsize > 32767)
7711 {
7712 rtx reg_rtx;
7713
7714 if (!frame_pointer_needed)
7715 abort ();
7716
7717 reg_rtx = gen_rtx (REG, Pmode, 3);
7718 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
7719 emit_move_insn (reg_rtx, tsize_rtx);
7720 if (Pmode == DImode)
7721 emit_insn (gen_subdi3 (hard_frame_pointer_rtx,
7722 hard_frame_pointer_rtx,
7723 reg_rtx));
7724 else
7725 emit_insn (gen_subsi3 (hard_frame_pointer_rtx,
7726 hard_frame_pointer_rtx,
7727 reg_rtx));
7728 emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
7729 }
7730
7731 if (frame_pointer_needed)
7732 {
7733 rtx insn = 0;
7734
7735 /* On the mips16, we encourage the use of unextended
7736 instructions when using the frame pointer by pointing the
7737 frame pointer ahead of the argument space allocated on
7738 the stack. */
7739 if ((! TARGET_ABICALLS || (mips_abi != ABI_32 && mips_abi != ABI_O64))
7740 && TARGET_MIPS16
7741 && tsize > 32767)
7742 {
7743 /* In this case, we have already copied the stack
7744 pointer into the frame pointer, above. We need only
7745 adjust for the outgoing argument size. */
7746 if (current_function_outgoing_args_size != 0)
7747 {
7748 rtx incr = GEN_INT (current_function_outgoing_args_size);
7749 if (Pmode == DImode)
7750 insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
7751 hard_frame_pointer_rtx,
7752 incr));
7753 else
7754 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
7755 hard_frame_pointer_rtx,
7756 incr));
7757 }
7758 }
7759 else if (TARGET_MIPS16 && current_function_outgoing_args_size != 0)
7760 {
7761 rtx incr = GEN_INT (current_function_outgoing_args_size);
7762 if (Pmode == DImode)
7763 insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
7764 stack_pointer_rtx,
7765 incr));
7766 else
7767 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
7768 stack_pointer_rtx,
7769 incr));
7770 }
7771 else if (Pmode == DImode)
7772 insn = emit_insn (gen_movdi (hard_frame_pointer_rtx,
7773 stack_pointer_rtx));
7774 else
7775 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx,
7776 stack_pointer_rtx));
7777
7778 if (insn)
7779 RTX_FRAME_RELATED_P (insn) = 1;
7780 }
7781
7782 if (TARGET_ABICALLS && (mips_abi != ABI_32 && mips_abi != ABI_O64))
7783 emit_insn (gen_loadgp (XEXP (DECL_RTL (current_function_decl), 0),
7784 gen_rtx_REG (DImode, 25)));
7785 }
7786
7787 /* If we are profiling, make sure no instructions are scheduled before
7788 the call to mcount. */
7789
7790 if (current_function_profile)
7791 emit_insn (gen_blockage ());
7792 }
7793
7794 /* Do any necessary cleanup after a function to restore stack, frame,
7795 and regs. */
7796
7797 #define RA_MASK BITMASK_HIGH /* 1 << 31 */
7798 #define PIC_OFFSET_TABLE_MASK (1 << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
7799
7800 static void
mips_output_function_epilogue(file,size)7801 mips_output_function_epilogue (file, size)
7802 FILE *file ATTRIBUTE_UNUSED;
7803 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
7804 {
7805 const char *fnname = ""; /* FIXME: Correct initialisation? */
7806 rtx string;
7807
7808 #ifndef FUNCTION_NAME_ALREADY_DECLARED
7809 /* Get the function name the same way that toplev.c does before calling
7810 assemble_start_function. This is needed so that the name used here
7811 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
7812 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
7813
7814 if (!flag_inhibit_size_directive)
7815 {
7816 fputs ("\t.end\t", file);
7817 assemble_name (file, fnname);
7818 fputs ("\n", file);
7819 }
7820 #endif
7821
7822 if (TARGET_STATS)
7823 {
7824 int num_gp_regs = cfun->machine->frame.gp_reg_size / 4;
7825 int num_fp_regs = cfun->machine->frame.fp_reg_size / 8;
7826 int num_regs = num_gp_regs + num_fp_regs;
7827 const char *name = fnname;
7828
7829 if (name[0] == '*')
7830 name++;
7831
7832 dslots_load_total += num_regs;
7833
7834 fprintf (stderr,
7835 "%-20s fp=%c leaf=%c alloca=%c setjmp=%c stack=%4ld arg=%3d reg=%2d/%d delay=%3d/%3dL %3d/%3dJ refs=%3d/%3d/%3d",
7836 name, frame_pointer_needed ? 'y' : 'n',
7837 (cfun->machine->frame.mask & RA_MASK) != 0 ? 'n' : 'y',
7838 current_function_calls_alloca ? 'y' : 'n',
7839 current_function_calls_setjmp ? 'y' : 'n',
7840 cfun->machine->frame.total_size,
7841 current_function_outgoing_args_size, num_gp_regs, num_fp_regs,
7842 dslots_load_total, dslots_load_filled,
7843 dslots_jump_total, dslots_jump_filled,
7844 num_refs[0], num_refs[1], num_refs[2]);
7845
7846 fputc ('\n', stderr);
7847 }
7848
7849 /* Reset state info for each function. */
7850 inside_function = 0;
7851 ignore_line_number = 0;
7852 dslots_load_total = 0;
7853 dslots_jump_total = 0;
7854 dslots_load_filled = 0;
7855 dslots_jump_filled = 0;
7856 num_refs[0] = 0;
7857 num_refs[1] = 0;
7858 num_refs[2] = 0;
7859 mips_load_reg = 0;
7860 mips_load_reg2 = 0;
7861
7862 while (string_constants != NULL)
7863 {
7864 struct string_constant *next;
7865
7866 next = string_constants->next;
7867 free (string_constants);
7868 string_constants = next;
7869 }
7870
7871 /* If any following function uses the same strings as this one, force
7872 them to refer those strings indirectly. Nearby functions could
7873 refer them using pc-relative addressing, but it isn't safe in
7874 general. For instance, some functions may be placed in sections
7875 other than .text, and we don't know whether they be close enough
7876 to this one. In large files, even other .text functions can be
7877 too far away. */
7878 for (string = mips16_strings; string != 0; string = XEXP (string, 1))
7879 SYMBOL_REF_FLAG (XEXP (string, 0)) = 0;
7880 free_EXPR_LIST_list (&mips16_strings);
7881
7882 /* Restore the output file if optimizing the GP (optimizing the GP causes
7883 the text to be diverted to a tempfile, so that data decls come before
7884 references to the data). */
7885 if (TARGET_FILE_SWITCHING)
7886 {
7887 asm_out_file = asm_out_data_file;
7888 data_section ();
7889 }
7890 }
7891
7892 /* Expand the epilogue into a bunch of separate insns. */
7893
7894 void
mips_expand_epilogue()7895 mips_expand_epilogue ()
7896 {
7897 HOST_WIDE_INT tsize = cfun->machine->frame.total_size;
7898 rtx tsize_rtx = GEN_INT (tsize);
7899 rtx tmp_rtx = (rtx)0;
7900
7901 if (mips_can_use_return_insn ())
7902 {
7903 emit_jump_insn (gen_return ());
7904 return;
7905 }
7906
7907 if (mips_entry && ! mips_can_use_return_insn ())
7908 tsize -= 32;
7909
7910 if (tsize > 32767 && ! TARGET_MIPS16)
7911 {
7912 tmp_rtx = gen_rtx_REG (Pmode, MIPS_TEMP1_REGNUM);
7913 emit_move_insn (tmp_rtx, tsize_rtx);
7914 tsize_rtx = tmp_rtx;
7915 }
7916
7917 if (tsize > 0)
7918 {
7919 long orig_tsize = tsize;
7920
7921 if (frame_pointer_needed)
7922 {
7923 emit_insn (gen_blockage ());
7924
7925 /* On the mips16, the frame pointer is offset from the stack
7926 pointer by current_function_outgoing_args_size. We
7927 account for that by changing tsize. Note that this can
7928 actually make tsize negative. */
7929 if (TARGET_MIPS16)
7930 {
7931 tsize -= current_function_outgoing_args_size;
7932
7933 /* If we have a large frame, it's easier to add to $6
7934 than to $sp, since the mips16 has no instruction to
7935 add a register to $sp. */
7936 if (orig_tsize > 32767)
7937 {
7938 rtx g6_rtx = gen_rtx (REG, Pmode, GP_REG_FIRST + 6);
7939
7940 emit_move_insn (g6_rtx, GEN_INT (tsize));
7941 if (Pmode == DImode)
7942 emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
7943 hard_frame_pointer_rtx,
7944 g6_rtx));
7945 else
7946 emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
7947 hard_frame_pointer_rtx,
7948 g6_rtx));
7949 tsize = 0;
7950 }
7951
7952 if (tsize && tsize != orig_tsize)
7953 tsize_rtx = GEN_INT (tsize);
7954 }
7955
7956 if (Pmode == DImode)
7957 emit_insn (gen_movdi (stack_pointer_rtx, hard_frame_pointer_rtx));
7958 else
7959 emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
7960 }
7961
7962 /* The GP/PIC register is implicitly used by all SYMBOL_REFs, so if we
7963 are going to restore it, then we must emit a blockage insn to
7964 prevent the scheduler from moving the restore out of the epilogue. */
7965 else if (TARGET_ABICALLS && mips_abi != ABI_32 && mips_abi != ABI_O64
7966 && (cfun->machine->frame.mask
7967 & (1L << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))))
7968 emit_insn (gen_blockage ());
7969
7970 save_restore_insns (0, tmp_rtx, orig_tsize);
7971
7972 /* In mips16 mode with a large frame, we adjust the stack
7973 pointer before restoring the registers. In this case, we
7974 should always be using a frame pointer, so everything should
7975 have been handled above. */
7976 if (tsize > 32767 && TARGET_MIPS16)
7977 abort ();
7978
7979 if (current_function_calls_eh_return)
7980 {
7981 rtx eh_ofs = EH_RETURN_STACKADJ_RTX;
7982 if (Pmode == DImode)
7983 emit_insn (gen_adddi3 (eh_ofs, eh_ofs, tsize_rtx));
7984 else
7985 emit_insn (gen_addsi3 (eh_ofs, eh_ofs, tsize_rtx));
7986 tsize_rtx = eh_ofs;
7987 }
7988
7989 emit_insn (gen_blockage ());
7990
7991 if (tsize != 0 || current_function_calls_eh_return)
7992 {
7993 if (!TARGET_MIPS16)
7994 {
7995 if (Pmode == DImode)
7996 emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
7997 tsize_rtx));
7998 else
7999 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
8000 tsize_rtx));
8001 }
8002 else
8003 {
8004 /* We need to work around not being able to add a register
8005 to the stack pointer directly. Use register $6 as an
8006 intermediate step. */
8007
8008 rtx g6_rtx = gen_rtx (REG, Pmode, GP_REG_FIRST + 6);
8009
8010 if (Pmode == DImode)
8011 {
8012 emit_insn (gen_movdi (g6_rtx, stack_pointer_rtx));
8013 emit_insn (gen_adddi3 (g6_rtx, g6_rtx, tsize_rtx));
8014 emit_insn (gen_movdi (stack_pointer_rtx, g6_rtx));
8015 }
8016 else
8017 {
8018 emit_insn (gen_movsi (g6_rtx, stack_pointer_rtx));
8019 emit_insn (gen_addsi3 (g6_rtx, g6_rtx, tsize_rtx));
8020 emit_insn (gen_movsi (stack_pointer_rtx, g6_rtx));
8021 }
8022 }
8023
8024 }
8025 }
8026
8027 /* The mips16 loads the return address into $7, not $31. */
8028 if (TARGET_MIPS16 && (cfun->machine->frame.mask & RA_MASK) != 0)
8029 emit_jump_insn (gen_return_internal (gen_rtx (REG, Pmode,
8030 GP_REG_FIRST + 7)));
8031 else
8032 emit_jump_insn (gen_return_internal (gen_rtx (REG, Pmode,
8033 GP_REG_FIRST + 31)));
8034 }
8035
8036 /* Return nonzero if this function is known to have a null epilogue.
8037 This allows the optimizer to omit jumps to jumps if no stack
8038 was created. */
8039
8040 int
mips_can_use_return_insn()8041 mips_can_use_return_insn ()
8042 {
8043 tree return_type;
8044
8045 if (! reload_completed)
8046 return 0;
8047
8048 if (regs_ever_live[31] || current_function_profile)
8049 return 0;
8050
8051 return_type = DECL_RESULT (current_function_decl);
8052
8053 /* In mips16 mode, a function which returns a floating point value
8054 needs to arrange to copy the return value into the floating point
8055 registers. */
8056 if (TARGET_MIPS16
8057 && mips16_hard_float
8058 && ! aggregate_value_p (return_type)
8059 && GET_MODE_CLASS (DECL_MODE (return_type)) == MODE_FLOAT
8060 && GET_MODE_SIZE (DECL_MODE (return_type)) <= UNITS_PER_FPVALUE)
8061 return 0;
8062
8063 if (cfun->machine->frame.initialized)
8064 return cfun->machine->frame.total_size == 0;
8065
8066 return compute_frame_size (get_frame_size ()) == 0;
8067 }
8068
8069 /* Returns nonzero if X contains a SYMBOL_REF. */
8070
8071 static int
symbolic_expression_p(x)8072 symbolic_expression_p (x)
8073 rtx x;
8074 {
8075 if (GET_CODE (x) == SYMBOL_REF)
8076 return 1;
8077
8078 if (GET_CODE (x) == CONST)
8079 return symbolic_expression_p (XEXP (x, 0));
8080
8081 if (GET_RTX_CLASS (GET_CODE (x)) == '1')
8082 return symbolic_expression_p (XEXP (x, 0));
8083
8084 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
8085 || GET_RTX_CLASS (GET_CODE (x)) == '2')
8086 return (symbolic_expression_p (XEXP (x, 0))
8087 || symbolic_expression_p (XEXP (x, 1)));
8088
8089 return 0;
8090 }
8091
8092 /* Choose the section to use for the constant rtx expression X that has
8093 mode MODE. */
8094
8095 static void
mips_select_rtx_section(mode,x,align)8096 mips_select_rtx_section (mode, x, align)
8097 enum machine_mode mode;
8098 rtx x;
8099 unsigned HOST_WIDE_INT align;
8100 {
8101 if (TARGET_MIPS16)
8102 {
8103 /* In mips16 mode, the constant table always goes in the same section
8104 as the function, so that constants can be loaded using PC relative
8105 addressing. */
8106 function_section (current_function_decl);
8107 }
8108 else if (TARGET_EMBEDDED_DATA)
8109 {
8110 /* For embedded applications, always put constants in read-only data,
8111 in order to reduce RAM usage. */
8112 mergeable_constant_section (mode, align, 0);
8113 }
8114 else
8115 {
8116 /* For hosted applications, always put constants in small data if
8117 possible, as this gives the best performance. */
8118 /* ??? Consider using mergable small data sections. */
8119
8120 if (GET_MODE_SIZE (mode) <= (unsigned) mips_section_threshold
8121 && mips_section_threshold > 0)
8122 SMALL_DATA_SECTION ();
8123 else if (flag_pic && symbolic_expression_p (x))
8124 {
8125 if (targetm.have_named_sections)
8126 named_section (NULL_TREE, ".data.rel.ro", 3);
8127 else
8128 data_section ();
8129 }
8130 else
8131 mergeable_constant_section (mode, align, 0);
8132 }
8133 }
8134
8135 /* Choose the section to use for DECL. RELOC is true if its value contains
8136 any relocatable expression.
8137
8138 Some of the logic used here needs to be replicated in
8139 mips_encode_section_info so that references to these symbols are
8140 done correctly. Specifically, at least all symbols assigned here
8141 to rom (.text and/or .rodata) must not be referenced via
8142 mips_encode_section_info with %gprel, as the rom might be too far
8143 away.
8144
8145 If you need to make a change here, you probably should check
8146 mips_encode_section_info to see if it needs a similar change.
8147
8148 ??? This would be fixed by implementing targetm.is_small_data_p. */
8149
8150 static void
mips_select_section(decl,reloc,align)8151 mips_select_section (decl, reloc, align)
8152 tree decl;
8153 int reloc;
8154 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED;
8155 {
8156 int size = int_size_in_bytes (TREE_TYPE (decl));
8157
8158 if ((TARGET_EMBEDDED_PIC || TARGET_MIPS16)
8159 && TREE_CODE (decl) == STRING_CST
8160 && !flag_writable_strings)
8161 /* For embedded position independent code, put constant strings in the
8162 text section, because the data section is limited to 64K in size.
8163 For mips16 code, put strings in the text section so that a PC
8164 relative load instruction can be used to get their address. */
8165 text_section ();
8166 else if (TARGET_EMBEDDED_DATA)
8167 {
8168 /* For embedded applications, always put an object in read-only data
8169 if possible, in order to reduce RAM usage. */
8170
8171 if (((TREE_CODE (decl) == VAR_DECL
8172 && TREE_READONLY (decl) && !TREE_SIDE_EFFECTS (decl)
8173 && DECL_INITIAL (decl)
8174 && (DECL_INITIAL (decl) == error_mark_node
8175 || TREE_CONSTANT (DECL_INITIAL (decl))))
8176 /* Deal with calls from output_constant_def_contents. */
8177 || (TREE_CODE (decl) != VAR_DECL
8178 && (TREE_CODE (decl) != STRING_CST
8179 || !flag_writable_strings)))
8180 && ! (flag_pic && reloc))
8181 readonly_data_section ();
8182 else if (size > 0 && size <= mips_section_threshold)
8183 SMALL_DATA_SECTION ();
8184 else
8185 data_section ();
8186 }
8187 else
8188 {
8189 /* For hosted applications, always put an object in small data if
8190 possible, as this gives the best performance. */
8191
8192 if (size > 0 && size <= mips_section_threshold)
8193 SMALL_DATA_SECTION ();
8194 else if (((TREE_CODE (decl) == VAR_DECL
8195 && TREE_READONLY (decl) && !TREE_SIDE_EFFECTS (decl)
8196 && DECL_INITIAL (decl)
8197 && (DECL_INITIAL (decl) == error_mark_node
8198 || TREE_CONSTANT (DECL_INITIAL (decl))))
8199 /* Deal with calls from output_constant_def_contents. */
8200 || (TREE_CODE (decl) != VAR_DECL
8201 && (TREE_CODE (decl) != STRING_CST
8202 || !flag_writable_strings)))
8203 && ! (flag_pic && reloc))
8204 readonly_data_section ();
8205 else
8206 data_section ();
8207 }
8208 }
8209
8210 /* When optimizing for the $gp pointer, SYMBOL_REF_FLAG is set for all
8211 small objects.
8212
8213 When generating embedded PIC code, SYMBOL_REF_FLAG is set for
8214 symbols which are not in the .text section.
8215
8216 When generating mips16 code, SYMBOL_REF_FLAG is set for string
8217 constants which are put in the .text section. We also record the
8218 total length of all such strings; this total is used to decide
8219 whether we need to split the constant table, and need not be
8220 precisely correct.
8221
8222 When not mips16 code nor embedded PIC, if a symbol is in a
8223 gp addressable section, SYMBOL_REF_FLAG is set prevent gcc from
8224 splitting the reference so that gas can generate a gp relative
8225 reference.
8226
8227 When TARGET_EMBEDDED_DATA is set, we assume that all const
8228 variables will be stored in ROM, which is too far from %gp to use
8229 %gprel addressing. Note that (1) we include "extern const"
8230 variables in this, which mips_select_section doesn't, and (2) we
8231 can't always tell if they're really const (they might be const C++
8232 objects with non-const constructors), so we err on the side of
8233 caution and won't use %gprel anyway (otherwise we'd have to defer
8234 this decision to the linker/loader). The handling of extern consts
8235 is why the DECL_INITIAL macros differ from mips_select_section. */
8236
8237 static void
mips_encode_section_info(decl,first)8238 mips_encode_section_info (decl, first)
8239 tree decl;
8240 int first;
8241 {
8242 if (TARGET_MIPS16)
8243 {
8244 if (first && TREE_CODE (decl) == STRING_CST
8245 && ! flag_writable_strings
8246 /* If this string is from a function, and the function will
8247 go in a gnu linkonce section, then we can't directly
8248 access the string. This gets an assembler error
8249 "unsupported PC relative reference to different section".
8250 If we modify SELECT_SECTION to put it in function_section
8251 instead of text_section, it still fails because
8252 DECL_SECTION_NAME isn't set until assemble_start_function.
8253 If we fix that, it still fails because strings are shared
8254 among multiple functions, and we have cross section
8255 references again. We force it to work by putting string
8256 addresses in the constant pool and indirecting. */
8257 && (! current_function_decl
8258 || ! DECL_ONE_ONLY (current_function_decl)))
8259 {
8260 rtx symref;
8261
8262 symref = XEXP (TREE_CST_RTL (decl), 0);
8263 mips16_strings = alloc_EXPR_LIST (0, symref, mips16_strings);
8264 SYMBOL_REF_FLAG (symref) = 1;
8265 mips_string_length += TREE_STRING_LENGTH (decl);
8266 }
8267 }
8268
8269 if (TARGET_EMBEDDED_DATA
8270 && (TREE_CODE (decl) == VAR_DECL
8271 && TREE_READONLY (decl) && !TREE_SIDE_EFFECTS (decl))
8272 && (!DECL_INITIAL (decl)
8273 || TREE_CONSTANT (DECL_INITIAL (decl))))
8274 {
8275 SYMBOL_REF_FLAG (XEXP (DECL_RTL (decl), 0)) = 0;
8276 }
8277
8278 else if (TARGET_EMBEDDED_PIC)
8279 {
8280 if (TREE_CODE (decl) == VAR_DECL)
8281 SYMBOL_REF_FLAG (XEXP (DECL_RTL (decl), 0)) = 1;
8282 else if (TREE_CODE (decl) == FUNCTION_DECL)
8283 SYMBOL_REF_FLAG (XEXP (DECL_RTL (decl), 0)) = 0;
8284 else if (TREE_CODE (decl) == STRING_CST
8285 && ! flag_writable_strings)
8286 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (decl), 0)) = 0;
8287 else
8288 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (decl), 0)) = 1;
8289 }
8290
8291 else if (TREE_CODE (decl) == VAR_DECL
8292 && DECL_SECTION_NAME (decl) != NULL_TREE
8293 && (0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (decl)),
8294 ".sdata")
8295 || 0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (decl)),
8296 ".sbss")))
8297 {
8298 SYMBOL_REF_FLAG (XEXP (DECL_RTL (decl), 0)) = 1;
8299 }
8300
8301 /* We can not perform GP optimizations on variables which are in
8302 specific sections, except for .sdata and .sbss which are
8303 handled above. */
8304 else if (TARGET_GP_OPT && TREE_CODE (decl) == VAR_DECL
8305 && DECL_SECTION_NAME (decl) == NULL_TREE
8306 && ! (TARGET_MIPS16 && TREE_PUBLIC (decl)
8307 && (DECL_COMMON (decl)
8308 || DECL_ONE_ONLY (decl)
8309 || DECL_WEAK (decl))))
8310 {
8311 int size = int_size_in_bytes (TREE_TYPE (decl));
8312
8313 if (size > 0 && size <= mips_section_threshold)
8314 SYMBOL_REF_FLAG (XEXP (DECL_RTL (decl), 0)) = 1;
8315 }
8316
8317 }
8318
8319 /* Return register to use for a function return value with VALTYPE for
8320 function FUNC. MODE is used instead of VALTYPE for LIBCALLs. */
8321
8322 rtx
mips_function_value(valtype,func,mode)8323 mips_function_value (valtype, func, mode)
8324 tree valtype;
8325 tree func ATTRIBUTE_UNUSED;
8326 enum machine_mode mode;
8327 {
8328 int reg = GP_RETURN;
8329 enum mode_class mclass;
8330 int unsignedp = 1;
8331
8332 if (valtype)
8333 {
8334 mode = TYPE_MODE (valtype);
8335 unsignedp = TREE_UNSIGNED (valtype);
8336
8337 /* Since we define PROMOTE_FUNCTION_RETURN, we must promote
8338 the mode just as PROMOTE_MODE does. */
8339 mode = promote_mode (valtype, mode, &unsignedp, 1);
8340 }
8341 mclass = GET_MODE_CLASS (mode);
8342
8343 if (mclass == MODE_FLOAT && GET_MODE_SIZE (mode) <= UNITS_PER_HWFPVALUE)
8344 reg = FP_RETURN;
8345
8346 else if (mclass == MODE_FLOAT && mode == TFmode)
8347 /* long doubles are really split between f0 and f2, not f1. Eek.
8348 Use DImode for each component, since GCC wants integer modes
8349 for subregs. */
8350 return gen_rtx_PARALLEL
8351 (VOIDmode,
8352 gen_rtvec (2,
8353 gen_rtx_EXPR_LIST (VOIDmode,
8354 gen_rtx_REG (DImode, FP_RETURN),
8355 GEN_INT (0)),
8356 gen_rtx_EXPR_LIST (VOIDmode,
8357 gen_rtx_REG (DImode, FP_RETURN + 2),
8358 GEN_INT (GET_MODE_SIZE (mode) / 2))));
8359
8360
8361 else if (mclass == MODE_COMPLEX_FLOAT
8362 && GET_MODE_SIZE (mode) <= UNITS_PER_HWFPVALUE * 2)
8363 {
8364 enum machine_mode cmode = GET_MODE_INNER (mode);
8365
8366 return gen_rtx_PARALLEL
8367 (VOIDmode,
8368 gen_rtvec (2,
8369 gen_rtx_EXPR_LIST (VOIDmode,
8370 gen_rtx_REG (cmode, FP_RETURN),
8371 GEN_INT (0)),
8372 gen_rtx_EXPR_LIST (VOIDmode,
8373 gen_rtx_REG (cmode, FP_RETURN + FP_INC),
8374 GEN_INT (GET_MODE_SIZE (cmode)))));
8375 }
8376
8377 else if (valtype && TREE_CODE (valtype) == RECORD_TYPE
8378 && mips_abi != ABI_32
8379 && mips_abi != ABI_O64
8380 && mips_abi != ABI_EABI)
8381 {
8382 /* A struct with only one or two floating point fields is returned in
8383 the floating point registers. */
8384 tree field, fields[2];
8385 int i;
8386
8387 for (i = 0, field = TYPE_FIELDS (valtype); field;
8388 field = TREE_CHAIN (field))
8389 {
8390 if (TREE_CODE (field) != FIELD_DECL)
8391 continue;
8392
8393 if (TREE_CODE (TREE_TYPE (field)) != REAL_TYPE || i >= 2)
8394 break;
8395
8396 fields[i++] = field;
8397 }
8398
8399 /* Must check i, so that we reject structures with no elements. */
8400 if (! field)
8401 {
8402 if (i == 1)
8403 {
8404 /* The structure has DImode, but we don't allow DImode values
8405 in FP registers, so we use a PARALLEL even though it isn't
8406 strictly necessary. */
8407 enum machine_mode field_mode = TYPE_MODE (TREE_TYPE (fields[0]));
8408
8409 return gen_rtx_PARALLEL
8410 (mode,
8411 gen_rtvec (1,
8412 gen_rtx_EXPR_LIST (VOIDmode,
8413 gen_rtx_REG (field_mode,
8414 FP_RETURN),
8415 const0_rtx)));
8416 }
8417
8418 else if (i == 2)
8419 {
8420 enum machine_mode first_mode
8421 = TYPE_MODE (TREE_TYPE (fields[0]));
8422 enum machine_mode second_mode
8423 = TYPE_MODE (TREE_TYPE (fields[1]));
8424 HOST_WIDE_INT first_offset = int_byte_position (fields[0]);
8425 HOST_WIDE_INT second_offset = int_byte_position (fields[1]);
8426
8427 return gen_rtx_PARALLEL
8428 (mode,
8429 gen_rtvec (2,
8430 gen_rtx_EXPR_LIST (VOIDmode,
8431 gen_rtx_REG (first_mode,
8432 FP_RETURN),
8433 GEN_INT (first_offset)),
8434 gen_rtx_EXPR_LIST (VOIDmode,
8435 gen_rtx_REG (second_mode,
8436 FP_RETURN + 2),
8437 GEN_INT (second_offset))));
8438 }
8439 }
8440 }
8441
8442 return gen_rtx_REG (mode, reg);
8443 }
8444
8445 /* The implementation of FUNCTION_ARG_PASS_BY_REFERENCE. Return
8446 nonzero when an argument must be passed by reference. */
8447
8448 int
function_arg_pass_by_reference(cum,mode,type,named)8449 function_arg_pass_by_reference (cum, mode, type, named)
8450 const CUMULATIVE_ARGS *cum;
8451 enum machine_mode mode;
8452 tree type;
8453 int named ATTRIBUTE_UNUSED;
8454 {
8455 int size;
8456
8457 if (mips_abi == ABI_32 || mips_abi == ABI_O64)
8458 return 0;
8459
8460 /* We must pass by reference if we would be both passing in registers
8461 and the stack. This is because any subsequent partial arg would be
8462 handled incorrectly in this case.
8463
8464 ??? This is really a kludge. We should either fix GCC so that such
8465 a situation causes an abort and then do something in the MIPS port
8466 to prevent it, or add code to function.c to properly handle the case. */
8467 /* ??? cum can be NULL when called from mips_va_arg. The problem handled
8468 here hopefully is not relevant to mips_va_arg. */
8469 if (cum && MUST_PASS_IN_STACK (mode, type)
8470 && mips_abi != ABI_MEABI
8471 && FUNCTION_ARG (*cum, mode, type, named) != 0)
8472 return 1;
8473
8474 /* Otherwise, we only do this if EABI is selected. */
8475 if (mips_abi != ABI_EABI)
8476 return 0;
8477
8478 /* ??? How should SCmode be handled? */
8479 if (type == NULL_TREE || mode == DImode || mode == DFmode)
8480 return 0;
8481
8482 size = int_size_in_bytes (type);
8483 return size == -1 || size > UNITS_PER_WORD;
8484 }
8485
8486 /* Return the class of registers for which a mode change from FROM to TO
8487 is invalid.
8488
8489 In little-endian mode, the hi-lo registers are numbered backwards,
8490 so (subreg:SI (reg:DI hi) 0) gets the high word instead of the low
8491 word as intended.
8492
8493 Similarly, when using paired floating-point registers, the first
8494 register holds the low word, regardless of endianness. So in big
8495 endian mode, (subreg:SI (reg:DF $f0) 0) does not get the high word
8496 as intended.
8497
8498 Also, loading a 32-bit value into a 64-bit floating-point register
8499 will not sign-extend the value, despite what LOAD_EXTEND_OP says.
8500 We can't allow 64-bit float registers to change from a 32-bit
8501 mode to a 64-bit mode. */
8502
8503 bool
mips_cannot_change_mode_class(from,to,class)8504 mips_cannot_change_mode_class (from, to, class)
8505 enum machine_mode from, to;
8506 enum reg_class class;
8507 {
8508 if (GET_MODE_SIZE (from) != GET_MODE_SIZE (to))
8509 {
8510 if (TARGET_BIG_ENDIAN)
8511 return reg_classes_intersect_p (FP_REGS, class);
8512 if (TARGET_FLOAT64)
8513 return reg_classes_intersect_p (HI_AND_FP_REGS, class);
8514 return reg_classes_intersect_p (HI_REG, class);
8515 }
8516 return false;
8517 }
8518
8519 /* This function returns the register class required for a secondary
8520 register when copying between one of the registers in CLASS, and X,
8521 using MODE. If IN_P is nonzero, the copy is going from X to the
8522 register, otherwise the register is the source. A return value of
8523 NO_REGS means that no secondary register is required. */
8524
8525 enum reg_class
mips_secondary_reload_class(class,mode,x,in_p)8526 mips_secondary_reload_class (class, mode, x, in_p)
8527 enum reg_class class;
8528 enum machine_mode mode;
8529 rtx x;
8530 int in_p;
8531 {
8532 enum reg_class gr_regs = TARGET_MIPS16 ? M16_REGS : GR_REGS;
8533 int regno = -1;
8534 int gp_reg_p;
8535
8536 if (GET_CODE (x) == SIGN_EXTEND)
8537 {
8538 int off = 0;
8539
8540 x = XEXP (x, 0);
8541
8542 /* We may be called with reg_renumber NULL from regclass.
8543 ??? This is probably a bug. */
8544 if (reg_renumber)
8545 regno = true_regnum (x);
8546 else
8547 {
8548 while (GET_CODE (x) == SUBREG)
8549 {
8550 off += subreg_regno_offset (REGNO (SUBREG_REG (x)),
8551 GET_MODE (SUBREG_REG (x)),
8552 SUBREG_BYTE (x),
8553 GET_MODE (x));
8554 x = SUBREG_REG (x);
8555 }
8556
8557 if (GET_CODE (x) == REG)
8558 regno = REGNO (x) + off;
8559 }
8560
8561 /* 64-bit floating-point registers don't store 32-bit values
8562 in sign-extended form. The only way we can reload
8563 (sign_extend:DI (reg:SI $f0)) is by moving $f0 into
8564 an integer register using a 32-bit move. */
8565 if (FP_REG_P (regno))
8566 return (class == GR_REGS ? NO_REGS : GR_REGS);
8567
8568 /* For the same reason, we can only reload (sign_extend:DI FOO) into
8569 a floating-point register when FOO is an integer register. */
8570 if (class == FP_REGS)
8571 return (GP_REG_P (regno) ? NO_REGS : GR_REGS);
8572 }
8573
8574 else if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
8575 regno = true_regnum (x);
8576
8577 gp_reg_p = TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
8578
8579 /* We always require a general register when copying anything to
8580 HILO_REGNUM, except when copying an SImode value from HILO_REGNUM
8581 to a general register, or when copying from register 0. */
8582 if (class == HILO_REG && regno != GP_REG_FIRST + 0)
8583 return ((! in_p
8584 && gp_reg_p
8585 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode))
8586 ? NO_REGS : gr_regs);
8587 else if (regno == HILO_REGNUM)
8588 return ((in_p
8589 && class == gr_regs
8590 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode))
8591 ? NO_REGS : gr_regs);
8592
8593 /* Copying from HI or LO to anywhere other than a general register
8594 requires a general register. */
8595 if (class == HI_REG || class == LO_REG || class == MD_REGS)
8596 {
8597 if (TARGET_MIPS16 && in_p)
8598 {
8599 /* We can't really copy to HI or LO at all in mips16 mode. */
8600 return M16_REGS;
8601 }
8602 return gp_reg_p ? NO_REGS : gr_regs;
8603 }
8604 if (MD_REG_P (regno))
8605 {
8606 if (TARGET_MIPS16 && ! in_p)
8607 {
8608 /* We can't really copy to HI or LO at all in mips16 mode. */
8609 return M16_REGS;
8610 }
8611 return class == gr_regs ? NO_REGS : gr_regs;
8612 }
8613
8614 /* We can only copy a value to a condition code register from a
8615 floating point register, and even then we require a scratch
8616 floating point register. We can only copy a value out of a
8617 condition code register into a general register. */
8618 if (class == ST_REGS)
8619 {
8620 if (in_p)
8621 return FP_REGS;
8622 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
8623 }
8624 if (ST_REG_P (regno))
8625 {
8626 if (! in_p)
8627 return FP_REGS;
8628 return class == GR_REGS ? NO_REGS : GR_REGS;
8629 }
8630
8631 if (class == FP_REGS)
8632 {
8633 if (GET_CODE (x) == MEM)
8634 {
8635 /* In this case we can use lwc1, swc1, ldc1 or sdc1. */
8636 return NO_REGS;
8637 }
8638 else if (CONSTANT_P (x) && GET_MODE_CLASS (mode) == MODE_FLOAT)
8639 {
8640 /* We can use the l.s and l.d macros to load floating-point
8641 constants. ??? For l.s, we could probably get better
8642 code by returning GR_REGS here. */
8643 return NO_REGS;
8644 }
8645 else if (GP_REG_P (regno) || x == CONST0_RTX (mode))
8646 {
8647 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
8648 return NO_REGS;
8649 }
8650 else if (FP_REG_P (regno))
8651 {
8652 /* In this case we can use mov.s or mov.d. */
8653 return NO_REGS;
8654 }
8655 else
8656 {
8657 /* Otherwise, we need to reload through an integer register. */
8658 return GR_REGS;
8659 }
8660 }
8661
8662 /* In mips16 mode, going between memory and anything but M16_REGS
8663 requires an M16_REG. */
8664 if (TARGET_MIPS16)
8665 {
8666 if (class != M16_REGS && class != M16_NA_REGS)
8667 {
8668 if (gp_reg_p)
8669 return NO_REGS;
8670 return M16_REGS;
8671 }
8672 if (! gp_reg_p)
8673 {
8674 /* The stack pointer isn't a valid operand to an add instruction,
8675 so we need to load it into M16_REGS first. This can happen as
8676 a result of register elimination and form_sum converting
8677 (plus reg (plus SP CONST)) to (plus (plus reg SP) CONST). We
8678 need an extra register if the dest is the same as the other
8679 register. In that case, we can't fix the problem by loading SP
8680 into the dest first. */
8681 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == REG
8682 && GET_CODE (XEXP (x, 1)) == REG
8683 && (XEXP (x, 0) == stack_pointer_rtx
8684 || XEXP (x, 1) == stack_pointer_rtx))
8685 return (class == M16_REGS ? M16_NA_REGS : M16_REGS);
8686
8687 if (class == M16_REGS || class == M16_NA_REGS)
8688 return NO_REGS;
8689 return M16_REGS;
8690 }
8691 }
8692
8693 return NO_REGS;
8694 }
8695
8696 /* This function returns the maximum number of consecutive registers
8697 needed to represent mode MODE in registers of class CLASS. */
8698
8699 int
mips_class_max_nregs(class,mode)8700 mips_class_max_nregs (class, mode)
8701 enum reg_class class;
8702 enum machine_mode mode;
8703 {
8704 if (class == FP_REGS)
8705 return FP_INC;
8706 else
8707 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
8708 }
8709
8710 /* For each mips16 function which refers to GP relative symbols, we
8711 use a pseudo register, initialized at the start of the function, to
8712 hold the $gp value. */
8713
8714 rtx
mips16_gp_pseudo_reg()8715 mips16_gp_pseudo_reg ()
8716 {
8717 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
8718 {
8719 rtx const_gp;
8720 rtx insn, scan;
8721
8722 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
8723 RTX_UNCHANGING_P (cfun->machine->mips16_gp_pseudo_rtx) = 1;
8724
8725 /* We want to initialize this to a value which gcc will believe
8726 is constant. */
8727 const_gp = gen_rtx (CONST, Pmode,
8728 gen_rtx (REG, Pmode, GP_REG_FIRST + 28));
8729
8730 start_sequence ();
8731 emit_move_insn (cfun->machine->mips16_gp_pseudo_rtx,
8732 const_gp);
8733 insn = get_insns ();
8734 end_sequence ();
8735
8736 push_topmost_sequence ();
8737 /* We need to emit the initialization after the FUNCTION_BEG
8738 note, so that it will be integrated. */
8739 for (scan = get_insns (); scan != NULL_RTX; scan = NEXT_INSN (scan))
8740 if (GET_CODE (scan) == NOTE
8741 && NOTE_LINE_NUMBER (scan) == NOTE_INSN_FUNCTION_BEG)
8742 break;
8743 if (scan == NULL_RTX)
8744 scan = get_insns ();
8745 insn = emit_insn_after (insn, scan);
8746 pop_topmost_sequence ();
8747 }
8748
8749 return cfun->machine->mips16_gp_pseudo_rtx;
8750 }
8751
8752 /* Return an RTX which represents the signed 16 bit offset from the
8753 $gp register for the given symbol. This is only used on the
8754 mips16. */
8755
8756 rtx
mips16_gp_offset(sym)8757 mips16_gp_offset (sym)
8758 rtx sym;
8759 {
8760 tree gp;
8761
8762 if (GET_CODE (sym) != SYMBOL_REF
8763 || ! SYMBOL_REF_FLAG (sym))
8764 abort ();
8765
8766 /* We use a special identifier to represent the value of the gp
8767 register. */
8768 gp = get_identifier ("__mips16_gp_value");
8769
8770 return gen_rtx (CONST, Pmode,
8771 gen_rtx (MINUS, Pmode, sym,
8772 gen_rtx (SYMBOL_REF, Pmode,
8773 IDENTIFIER_POINTER (gp))));
8774 }
8775
8776 /* Return nonzero if the given RTX represents a signed 16 bit offset
8777 from the $gp register. */
8778
8779 int
mips16_gp_offset_p(x)8780 mips16_gp_offset_p (x)
8781 rtx x;
8782 {
8783 if (GET_CODE (x) == CONST)
8784 x = XEXP (x, 0);
8785
8786 /* It's OK to add a small integer value to a gp offset. */
8787 if (GET_CODE (x) == PLUS)
8788 {
8789 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8790 && SMALL_INT (XEXP (x, 1)))
8791 return mips16_gp_offset_p (XEXP (x, 0));
8792 if (GET_CODE (XEXP (x, 0)) == CONST_INT
8793 && SMALL_INT (XEXP (x, 0)))
8794 return mips16_gp_offset_p (XEXP (x, 1));
8795 return 0;
8796 }
8797
8798 /* Make sure it is in the form SYM - __mips16_gp_value. */
8799 return (GET_CODE (x) == MINUS
8800 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF
8801 && SYMBOL_REF_FLAG (XEXP (x, 0))
8802 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF
8803 && strcmp (XSTR (XEXP (x, 1), 0), "__mips16_gp_value") == 0);
8804 }
8805
8806 /* Output a GP offset. We don't want to print the subtraction of
8807 __mips16_gp_value; it is implicitly represented by the %gprel which
8808 should have been printed by the caller. */
8809
8810 static void
mips16_output_gp_offset(file,x)8811 mips16_output_gp_offset (file, x)
8812 FILE *file;
8813 rtx x;
8814 {
8815 if (GET_CODE (x) == CONST)
8816 x = XEXP (x, 0);
8817
8818 if (GET_CODE (x) == PLUS)
8819 {
8820 mips16_output_gp_offset (file, XEXP (x, 0));
8821 fputs ("+", file);
8822 mips16_output_gp_offset (file, XEXP (x, 1));
8823 return;
8824 }
8825
8826 if (GET_CODE (x) == MINUS
8827 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF
8828 && strcmp (XSTR (XEXP (x, 1), 0), "__mips16_gp_value") == 0)
8829 {
8830 mips16_output_gp_offset (file, XEXP (x, 0));
8831 return;
8832 }
8833
8834 output_addr_const (file, x);
8835 }
8836
8837 /* Return nonzero if a constant should not be output until after the
8838 function. This is true of most string constants, so that we can
8839 use a more efficient PC relative reference. However, a static
8840 inline function may never call assemble_function_end to write out
8841 the constant pool, so don't try to postpone the constant in that
8842 case.
8843
8844 ??? It's really a bug that a static inline function can put stuff
8845 in the constant pool even if the function itself is not output.
8846
8847 We record which string constants we've seen, so that we know which
8848 ones might use the more efficient reference. */
8849
8850 int
mips16_constant_after_function_p(x)8851 mips16_constant_after_function_p (x)
8852 tree x;
8853 {
8854 if (TREE_CODE (x) == STRING_CST
8855 && ! flag_writable_strings
8856 && current_function_decl != 0
8857 && ! DECL_DEFER_OUTPUT (current_function_decl)
8858 && ! (DECL_INLINE (current_function_decl)
8859 && ((! TREE_PUBLIC (current_function_decl)
8860 && ! TREE_ADDRESSABLE (current_function_decl)
8861 && ! flag_keep_inline_functions)
8862 || DECL_EXTERNAL (current_function_decl))))
8863 {
8864 struct string_constant *n;
8865
8866 n = (struct string_constant *) xmalloc (sizeof *n);
8867 n->label = XSTR (XEXP (TREE_CST_RTL (x), 0), 0);
8868 n->next = string_constants;
8869 string_constants = n;
8870
8871 return 1;
8872 }
8873
8874 return 0;
8875 }
8876
8877 /* Validate a constant for the mips16. This rejects general symbolic
8878 addresses, which must be loaded from memory. If ADDR is nonzero,
8879 this should reject anything which is not a legal address. If
8880 ADDEND is nonzero, this is being added to something else. */
8881
8882 int
mips16_constant(x,mode,addr,addend)8883 mips16_constant (x, mode, addr, addend)
8884 rtx x;
8885 enum machine_mode mode;
8886 int addr;
8887 int addend;
8888 {
8889 while (GET_CODE (x) == CONST)
8890 x = XEXP (x, 0);
8891
8892 switch (GET_CODE (x))
8893 {
8894 default:
8895 return 0;
8896
8897 case PLUS:
8898 return (mips16_constant (XEXP (x, 0), mode, addr, 1)
8899 && mips16_constant (XEXP (x, 1), mode, addr, 1));
8900
8901 case SYMBOL_REF:
8902 if (addr && GET_MODE_SIZE (mode) != 4 && GET_MODE_SIZE (mode) != 8)
8903 return 0;
8904 if (CONSTANT_POOL_ADDRESS_P (x))
8905 return 1;
8906
8907 /* If we aren't looking for a memory address, we can accept a GP
8908 relative symbol, which will have SYMBOL_REF_FLAG set; movsi
8909 knows how to handle this. We can always accept a string
8910 constant, which is the other case in which SYMBOL_REF_FLAG
8911 will be set. */
8912 if (! addr
8913 && ! addend
8914 && SYMBOL_REF_FLAG (x)
8915 && mode == (enum machine_mode) Pmode)
8916 return 1;
8917
8918 /* We can accept a string constant, which will have
8919 SYMBOL_REF_FLAG set but must be recognized by name to
8920 distinguish from a GP accessible symbol. The name of a
8921 string constant will have been generated by
8922 ASM_GENERATE_INTERNAL_LABEL as called by output_constant_def. */
8923 if (SYMBOL_REF_FLAG (x))
8924 {
8925 const char *name = XSTR (x, 0);
8926
8927 return (name[0] == '*'
8928 && strncmp (name + 1, LOCAL_LABEL_PREFIX,
8929 sizeof LOCAL_LABEL_PREFIX - 1) == 0);
8930 }
8931
8932 return 0;
8933
8934 case LABEL_REF:
8935 if (addr && GET_MODE_SIZE (mode) != 4 && GET_MODE_SIZE (mode) != 8)
8936 return 0;
8937 return 1;
8938
8939 case CONST_INT:
8940 if (addr && ! addend)
8941 return 0;
8942 return INTVAL (x) > - 0x10000 && INTVAL (x) <= 0xffff;
8943
8944 case REG:
8945 /* We need to treat $gp as a legitimate constant, because
8946 mips16_gp_pseudo_reg assumes that. */
8947 return REGNO (x) == GP_REG_FIRST + 28;
8948 }
8949 }
8950
8951 /* Write out code to move floating point arguments in or out of
8952 general registers. Output the instructions to FILE. FP_CODE is
8953 the code describing which arguments are present (see the comment at
8954 the definition of CUMULATIVE_ARGS in mips.h). FROM_FP_P is nonzero if
8955 we are copying from the floating point registers. */
8956
8957 static void
mips16_fp_args(file,fp_code,from_fp_p)8958 mips16_fp_args (file, fp_code, from_fp_p)
8959 FILE *file;
8960 int fp_code;
8961 int from_fp_p;
8962 {
8963 const char *s;
8964 int gparg, fparg;
8965 unsigned int f;
8966
8967 /* This code only works for the original 32 bit ABI and the O64 ABI. */
8968 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
8969 abort ();
8970
8971 if (from_fp_p)
8972 s = "mfc1";
8973 else
8974 s = "mtc1";
8975 gparg = GP_ARG_FIRST;
8976 fparg = FP_ARG_FIRST;
8977 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
8978 {
8979 if ((f & 3) == 1)
8980 {
8981 if ((fparg & 1) != 0)
8982 ++fparg;
8983 fprintf (file, "\t%s\t%s,%s\n", s,
8984 reg_names[gparg], reg_names[fparg]);
8985 }
8986 else if ((f & 3) == 2)
8987 {
8988 if (TARGET_64BIT)
8989 fprintf (file, "\td%s\t%s,%s\n", s,
8990 reg_names[gparg], reg_names[fparg]);
8991 else
8992 {
8993 if ((fparg & 1) != 0)
8994 ++fparg;
8995 if (TARGET_BIG_ENDIAN)
8996 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
8997 reg_names[gparg], reg_names[fparg + 1], s,
8998 reg_names[gparg + 1], reg_names[fparg]);
8999 else
9000 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
9001 reg_names[gparg], reg_names[fparg], s,
9002 reg_names[gparg + 1], reg_names[fparg + 1]);
9003 ++gparg;
9004 ++fparg;
9005 }
9006 }
9007 else
9008 abort ();
9009
9010 ++gparg;
9011 ++fparg;
9012 }
9013 }
9014
9015 /* Build a mips16 function stub. This is used for functions which
9016 take aruments in the floating point registers. It is 32 bit code
9017 that moves the floating point args into the general registers, and
9018 then jumps to the 16 bit code. */
9019
9020 static void
build_mips16_function_stub(file)9021 build_mips16_function_stub (file)
9022 FILE *file;
9023 {
9024 const char *fnname;
9025 char *secname, *stubname;
9026 tree stubid, stubdecl;
9027 int need_comma;
9028 unsigned int f;
9029
9030 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
9031 secname = (char *) alloca (strlen (fnname) + 20);
9032 sprintf (secname, ".mips16.fn.%s", fnname);
9033 stubname = (char *) alloca (strlen (fnname) + 20);
9034 sprintf (stubname, "__fn_stub_%s", fnname);
9035 stubid = get_identifier (stubname);
9036 stubdecl = build_decl (FUNCTION_DECL, stubid,
9037 build_function_type (void_type_node, NULL_TREE));
9038 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
9039
9040 fprintf (file, "\t# Stub function for %s (", current_function_name);
9041 need_comma = 0;
9042 for (f = (unsigned int) current_function_args_info.fp_code; f != 0; f >>= 2)
9043 {
9044 fprintf (file, "%s%s",
9045 need_comma ? ", " : "",
9046 (f & 3) == 1 ? "float" : "double");
9047 need_comma = 1;
9048 }
9049 fprintf (file, ")\n");
9050
9051 fprintf (file, "\t.set\tnomips16\n");
9052 function_section (stubdecl);
9053 ASM_OUTPUT_ALIGN (file, floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT));
9054
9055 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
9056 within a .ent, and we can not emit another .ent. */
9057 #ifndef FUNCTION_NAME_ALREADY_DECLARED
9058 fputs ("\t.ent\t", file);
9059 assemble_name (file, stubname);
9060 fputs ("\n", file);
9061 #endif
9062
9063 assemble_name (file, stubname);
9064 fputs (":\n", file);
9065
9066 /* We don't want the assembler to insert any nops here. */
9067 fprintf (file, "\t.set\tnoreorder\n");
9068
9069 mips16_fp_args (file, current_function_args_info.fp_code, 1);
9070
9071 fprintf (asm_out_file, "\t.set\tnoat\n");
9072 fprintf (asm_out_file, "\tla\t%s,", reg_names[GP_REG_FIRST + 1]);
9073 assemble_name (file, fnname);
9074 fprintf (file, "\n");
9075 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
9076 fprintf (asm_out_file, "\t.set\tat\n");
9077
9078 /* Unfortunately, we can't fill the jump delay slot. We can't fill
9079 with one of the mfc1 instructions, because the result is not
9080 available for one instruction, so if the very first instruction
9081 in the function refers to the register, it will see the wrong
9082 value. */
9083 fprintf (file, "\tnop\n");
9084
9085 fprintf (file, "\t.set\treorder\n");
9086
9087 #ifndef FUNCTION_NAME_ALREADY_DECLARED
9088 fputs ("\t.end\t", file);
9089 assemble_name (file, stubname);
9090 fputs ("\n", file);
9091 #endif
9092
9093 fprintf (file, "\t.set\tmips16\n");
9094
9095 function_section (current_function_decl);
9096 }
9097
9098 /* We keep a list of functions for which we have already built stubs
9099 in build_mips16_call_stub. */
9100
9101 struct mips16_stub
9102 {
9103 struct mips16_stub *next;
9104 char *name;
9105 int fpret;
9106 };
9107
9108 static struct mips16_stub *mips16_stubs;
9109
9110 /* Build a call stub for a mips16 call. A stub is needed if we are
9111 passing any floating point values which should go into the floating
9112 point registers. If we are, and the call turns out to be to a 32
9113 bit function, the stub will be used to move the values into the
9114 floating point registers before calling the 32 bit function. The
9115 linker will magically adjust the function call to either the 16 bit
9116 function or the 32 bit stub, depending upon where the function call
9117 is actually defined.
9118
9119 Similarly, we need a stub if the return value might come back in a
9120 floating point register.
9121
9122 RETVAL, FNMEM, and ARG_SIZE are the values passed to the call insn
9123 (RETVAL is NULL if this is call rather than call_value). FP_CODE
9124 is the code built by function_arg. This function returns a nonzero
9125 value if it builds the call instruction itself. */
9126
9127 int
build_mips16_call_stub(retval,fnmem,arg_size,fp_code)9128 build_mips16_call_stub (retval, fnmem, arg_size, fp_code)
9129 rtx retval;
9130 rtx fnmem;
9131 rtx arg_size;
9132 int fp_code;
9133 {
9134 int fpret;
9135 rtx fn;
9136 const char *fnname;
9137 char *secname, *stubname;
9138 struct mips16_stub *l;
9139 tree stubid, stubdecl;
9140 int need_comma;
9141 unsigned int f;
9142
9143 /* We don't need to do anything if we aren't in mips16 mode, or if
9144 we were invoked with the -msoft-float option. */
9145 if (! TARGET_MIPS16 || ! mips16_hard_float)
9146 return 0;
9147
9148 /* Figure out whether the value might come back in a floating point
9149 register. */
9150 fpret = (retval != 0
9151 && GET_MODE_CLASS (GET_MODE (retval)) == MODE_FLOAT
9152 && GET_MODE_SIZE (GET_MODE (retval)) <= UNITS_PER_FPVALUE);
9153
9154 /* We don't need to do anything if there were no floating point
9155 arguments and the value will not be returned in a floating point
9156 register. */
9157 if (fp_code == 0 && ! fpret)
9158 return 0;
9159
9160 if (GET_CODE (fnmem) != MEM)
9161 abort ();
9162 fn = XEXP (fnmem, 0);
9163
9164 /* We don't need to do anything if this is a call to a special
9165 mips16 support function. */
9166 if (GET_CODE (fn) == SYMBOL_REF
9167 && strncmp (XSTR (fn, 0), "__mips16_", 9) == 0)
9168 return 0;
9169
9170 /* This code will only work for o32 and o64 abis. The other ABI's
9171 require more sophisticated support. */
9172 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
9173 abort ();
9174
9175 /* We can only handle SFmode and DFmode floating point return
9176 values. */
9177 if (fpret && GET_MODE (retval) != SFmode && GET_MODE (retval) != DFmode)
9178 abort ();
9179
9180 /* If we're calling via a function pointer, then we must always call
9181 via a stub. There are magic stubs provided in libgcc.a for each
9182 of the required cases. Each of them expects the function address
9183 to arrive in register $2. */
9184
9185 if (GET_CODE (fn) != SYMBOL_REF)
9186 {
9187 char buf[30];
9188 tree id;
9189 rtx stub_fn, stub_mem, insn;
9190
9191 /* ??? If this code is modified to support other ABI's, we need
9192 to handle PARALLEL return values here. */
9193
9194 sprintf (buf, "__mips16_call_stub_%s%d",
9195 (fpret
9196 ? (GET_MODE (retval) == SFmode ? "sf_" : "df_")
9197 : ""),
9198 fp_code);
9199 id = get_identifier (buf);
9200 stub_fn = gen_rtx (SYMBOL_REF, Pmode, IDENTIFIER_POINTER (id));
9201 stub_mem = gen_rtx (MEM, Pmode, stub_fn);
9202
9203 emit_move_insn (gen_rtx (REG, Pmode, 2), fn);
9204
9205 if (retval == NULL_RTX)
9206 insn = gen_call_internal0 (stub_mem, arg_size,
9207 gen_rtx (REG, SImode,
9208 GP_REG_FIRST + 31));
9209 else
9210 insn = gen_call_value_internal0 (retval, stub_mem, arg_size,
9211 gen_rtx (REG, SImode,
9212 GP_REG_FIRST + 31));
9213 insn = emit_call_insn (insn);
9214
9215 /* Put the register usage information on the CALL. */
9216 if (GET_CODE (insn) != CALL_INSN)
9217 abort ();
9218 CALL_INSN_FUNCTION_USAGE (insn) =
9219 gen_rtx (EXPR_LIST, VOIDmode,
9220 gen_rtx (USE, VOIDmode, gen_rtx (REG, Pmode, 2)),
9221 CALL_INSN_FUNCTION_USAGE (insn));
9222
9223 /* If we are handling a floating point return value, we need to
9224 save $18 in the function prologue. Putting a note on the
9225 call will mean that regs_ever_live[$18] will be true if the
9226 call is not eliminated, and we can check that in the prologue
9227 code. */
9228 if (fpret)
9229 CALL_INSN_FUNCTION_USAGE (insn) =
9230 gen_rtx (EXPR_LIST, VOIDmode,
9231 gen_rtx (USE, VOIDmode, gen_rtx (REG, word_mode, 18)),
9232 CALL_INSN_FUNCTION_USAGE (insn));
9233
9234 /* Return 1 to tell the caller that we've generated the call
9235 insn. */
9236 return 1;
9237 }
9238
9239 /* We know the function we are going to call. If we have already
9240 built a stub, we don't need to do anything further. */
9241
9242 fnname = XSTR (fn, 0);
9243 for (l = mips16_stubs; l != NULL; l = l->next)
9244 if (strcmp (l->name, fnname) == 0)
9245 break;
9246
9247 if (l == NULL)
9248 {
9249 /* Build a special purpose stub. When the linker sees a
9250 function call in mips16 code, it will check where the target
9251 is defined. If the target is a 32 bit call, the linker will
9252 search for the section defined here. It can tell which
9253 symbol this section is associated with by looking at the
9254 relocation information (the name is unreliable, since this
9255 might be a static function). If such a section is found, the
9256 linker will redirect the call to the start of the magic
9257 section.
9258
9259 If the function does not return a floating point value, the
9260 special stub section is named
9261 .mips16.call.FNNAME
9262
9263 If the function does return a floating point value, the stub
9264 section is named
9265 .mips16.call.fp.FNNAME
9266 */
9267
9268 secname = (char *) alloca (strlen (fnname) + 40);
9269 sprintf (secname, ".mips16.call.%s%s",
9270 fpret ? "fp." : "",
9271 fnname);
9272 stubname = (char *) alloca (strlen (fnname) + 20);
9273 sprintf (stubname, "__call_stub_%s%s",
9274 fpret ? "fp_" : "",
9275 fnname);
9276 stubid = get_identifier (stubname);
9277 stubdecl = build_decl (FUNCTION_DECL, stubid,
9278 build_function_type (void_type_node, NULL_TREE));
9279 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
9280
9281 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
9282 (fpret
9283 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
9284 : ""),
9285 fnname);
9286 need_comma = 0;
9287 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
9288 {
9289 fprintf (asm_out_file, "%s%s",
9290 need_comma ? ", " : "",
9291 (f & 3) == 1 ? "float" : "double");
9292 need_comma = 1;
9293 }
9294 fprintf (asm_out_file, ")\n");
9295
9296 fprintf (asm_out_file, "\t.set\tnomips16\n");
9297 assemble_start_function (stubdecl, stubname);
9298
9299 #ifndef FUNCTION_NAME_ALREADY_DECLARED
9300 fputs ("\t.ent\t", asm_out_file);
9301 assemble_name (asm_out_file, stubname);
9302 fputs ("\n", asm_out_file);
9303
9304 assemble_name (asm_out_file, stubname);
9305 fputs (":\n", asm_out_file);
9306 #endif
9307
9308 /* We build the stub code by hand. That's the only way we can
9309 do it, since we can't generate 32 bit code during a 16 bit
9310 compilation. */
9311
9312 /* We don't want the assembler to insert any nops here. */
9313 fprintf (asm_out_file, "\t.set\tnoreorder\n");
9314
9315 mips16_fp_args (asm_out_file, fp_code, 0);
9316
9317 if (! fpret)
9318 {
9319 fprintf (asm_out_file, "\t.set\tnoat\n");
9320 fprintf (asm_out_file, "\tla\t%s,%s\n", reg_names[GP_REG_FIRST + 1],
9321 fnname);
9322 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
9323 fprintf (asm_out_file, "\t.set\tat\n");
9324 /* Unfortunately, we can't fill the jump delay slot. We
9325 can't fill with one of the mtc1 instructions, because the
9326 result is not available for one instruction, so if the
9327 very first instruction in the function refers to the
9328 register, it will see the wrong value. */
9329 fprintf (asm_out_file, "\tnop\n");
9330 }
9331 else
9332 {
9333 fprintf (asm_out_file, "\tmove\t%s,%s\n",
9334 reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
9335 fprintf (asm_out_file, "\tjal\t%s\n", fnname);
9336 /* As above, we can't fill the delay slot. */
9337 fprintf (asm_out_file, "\tnop\n");
9338 if (GET_MODE (retval) == SFmode)
9339 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
9340 reg_names[GP_REG_FIRST + 2], reg_names[FP_REG_FIRST + 0]);
9341 else
9342 {
9343 if (TARGET_BIG_ENDIAN)
9344 {
9345 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
9346 reg_names[GP_REG_FIRST + 2],
9347 reg_names[FP_REG_FIRST + 1]);
9348 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
9349 reg_names[GP_REG_FIRST + 3],
9350 reg_names[FP_REG_FIRST + 0]);
9351 }
9352 else
9353 {
9354 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
9355 reg_names[GP_REG_FIRST + 2],
9356 reg_names[FP_REG_FIRST + 0]);
9357 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
9358 reg_names[GP_REG_FIRST + 3],
9359 reg_names[FP_REG_FIRST + 1]);
9360 }
9361 }
9362 fprintf (asm_out_file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 18]);
9363 /* As above, we can't fill the delay slot. */
9364 fprintf (asm_out_file, "\tnop\n");
9365 }
9366
9367 fprintf (asm_out_file, "\t.set\treorder\n");
9368
9369 #ifdef ASM_DECLARE_FUNCTION_SIZE
9370 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
9371 #endif
9372
9373 #ifndef FUNCTION_NAME_ALREADY_DECLARED
9374 fputs ("\t.end\t", asm_out_file);
9375 assemble_name (asm_out_file, stubname);
9376 fputs ("\n", asm_out_file);
9377 #endif
9378
9379 fprintf (asm_out_file, "\t.set\tmips16\n");
9380
9381 /* Record this stub. */
9382 l = (struct mips16_stub *) xmalloc (sizeof *l);
9383 l->name = xstrdup (fnname);
9384 l->fpret = fpret;
9385 l->next = mips16_stubs;
9386 mips16_stubs = l;
9387 }
9388
9389 /* If we expect a floating point return value, but we've built a
9390 stub which does not expect one, then we're in trouble. We can't
9391 use the existing stub, because it won't handle the floating point
9392 value. We can't build a new stub, because the linker won't know
9393 which stub to use for the various calls in this object file.
9394 Fortunately, this case is illegal, since it means that a function
9395 was declared in two different ways in a single compilation. */
9396 if (fpret && ! l->fpret)
9397 error ("can not handle inconsistent calls to `%s'", fnname);
9398
9399 /* If we are calling a stub which handles a floating point return
9400 value, we need to arrange to save $18 in the prologue. We do
9401 this by marking the function call as using the register. The
9402 prologue will later see that it is used, and emit code to save
9403 it. */
9404
9405 if (l->fpret)
9406 {
9407 rtx insn;
9408
9409 if (retval == NULL_RTX)
9410 insn = gen_call_internal0 (fnmem, arg_size,
9411 gen_rtx (REG, SImode,
9412 GP_REG_FIRST + 31));
9413 else
9414 insn = gen_call_value_internal0 (retval, fnmem, arg_size,
9415 gen_rtx (REG, SImode,
9416 GP_REG_FIRST + 31));
9417 insn = emit_call_insn (insn);
9418
9419 if (GET_CODE (insn) != CALL_INSN)
9420 abort ();
9421
9422 CALL_INSN_FUNCTION_USAGE (insn) =
9423 gen_rtx (EXPR_LIST, VOIDmode,
9424 gen_rtx (USE, VOIDmode, gen_rtx (REG, word_mode, 18)),
9425 CALL_INSN_FUNCTION_USAGE (insn));
9426
9427 /* Return 1 to tell the caller that we've generated the call
9428 insn. */
9429 return 1;
9430 }
9431
9432 /* Return 0 to let the caller generate the call insn. */
9433 return 0;
9434 }
9435
9436 /* This function looks through the code for a function, and tries to
9437 optimize the usage of the $gp register. We arrange to copy $gp
9438 into a pseudo-register, and then let gcc's normal reload handling
9439 deal with the pseudo-register. Unfortunately, if reload choose to
9440 put the pseudo-register into a call-clobbered register, it will
9441 emit saves and restores for that register around any function
9442 calls. We don't need the saves, and it's faster to copy $gp than
9443 to do an actual restore. ??? This still means that we waste a
9444 stack slot.
9445
9446 This is an optimization, and the code which gcc has actually
9447 generated is correct, so we do not need to catch all cases. */
9448
9449 static void
mips16_optimize_gp(first)9450 mips16_optimize_gp (first)
9451 rtx first;
9452 {
9453 rtx gpcopy, slot, insn;
9454
9455 /* Look through the instructions. Set GPCOPY to the register which
9456 holds a copy of $gp. Set SLOT to the stack slot where it is
9457 saved. If we find an instruction which sets GPCOPY to anything
9458 other than $gp or SLOT, then we can't use it. If we find an
9459 instruction which sets SLOT to anything other than GPCOPY, we
9460 can't use it. */
9461
9462 gpcopy = NULL_RTX;
9463 slot = NULL_RTX;
9464 for (insn = first; insn != NULL_RTX; insn = next_active_insn (insn))
9465 {
9466 rtx set;
9467
9468 if (! INSN_P (insn))
9469 continue;
9470
9471 set = PATTERN (insn);
9472
9473 /* We know that all references to memory will be inside a SET,
9474 because there is no other way to access memory on the mips16.
9475 We don't have to worry about a PARALLEL here, because the
9476 mips.md file will never generate them for memory references. */
9477 if (GET_CODE (set) != SET)
9478 continue;
9479
9480 if (gpcopy == NULL_RTX
9481 && GET_CODE (SET_SRC (set)) == CONST
9482 && GET_CODE (XEXP (SET_SRC (set), 0)) == REG
9483 && REGNO (XEXP (SET_SRC (set), 0)) == GP_REG_FIRST + 28
9484 && GET_CODE (SET_DEST (set)) == REG
9485 && GET_MODE (SET_DEST (set)) == (unsigned) Pmode)
9486 gpcopy = SET_DEST (set);
9487 else if (slot == NULL_RTX
9488 && gpcopy != NULL_RTX
9489 && GET_CODE (SET_DEST (set)) == MEM
9490 && GET_CODE (SET_SRC (set)) == REG
9491 && REGNO (SET_SRC (set)) == REGNO (gpcopy)
9492 && GET_MODE (SET_DEST (set)) == (unsigned) Pmode)
9493 {
9494 rtx base, offset;
9495
9496 offset = const0_rtx;
9497 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
9498 if (GET_CODE (base) == REG
9499 && (REGNO (base) == STACK_POINTER_REGNUM
9500 || REGNO (base) == FRAME_POINTER_REGNUM))
9501 slot = SET_DEST (set);
9502 }
9503 else if (gpcopy != NULL_RTX
9504 && (GET_CODE (SET_DEST (set)) == REG
9505 || GET_CODE (SET_DEST (set)) == SUBREG)
9506 && reg_overlap_mentioned_p (SET_DEST (set), gpcopy)
9507 && (GET_CODE (SET_DEST (set)) != REG
9508 || REGNO (SET_DEST (set)) != REGNO (gpcopy)
9509 || GET_MODE (SET_DEST (set)) != (unsigned) Pmode
9510 || ((GET_CODE (SET_SRC (set)) != CONST
9511 || GET_CODE (XEXP (SET_SRC (set), 0)) != REG
9512 || (REGNO (XEXP (SET_SRC (set), 0))
9513 != GP_REG_FIRST + 28))
9514 && ! rtx_equal_p (SET_SRC (set), slot))))
9515 break;
9516 else if (slot != NULL_RTX
9517 && GET_CODE (SET_DEST (set)) == MEM
9518 && rtx_equal_p (SET_DEST (set), slot)
9519 && (GET_CODE (SET_SRC (set)) != REG
9520 || REGNO (SET_SRC (set)) != REGNO (gpcopy)))
9521 break;
9522 }
9523
9524 /* If we couldn't find a unique value for GPCOPY or SLOT, then try a
9525 different optimization. Any time we find a copy of $28 into a
9526 register, followed by an add of a symbol_ref to that register, we
9527 convert it to load the value from the constant table instead.
9528 The copy and add will take six bytes, just as the load and
9529 constant table entry will take six bytes. However, it is
9530 possible that the constant table entry will be shared.
9531
9532 This could be a peephole optimization, but I don't know if the
9533 peephole code can call force_const_mem.
9534
9535 Using the same register for the copy of $28 and the add of the
9536 symbol_ref is actually pretty likely, since the add instruction
9537 requires the destination and the first addend to be the same
9538 register. */
9539
9540 if (insn != NULL_RTX || gpcopy == NULL_RTX || slot == NULL_RTX)
9541 {
9542 rtx next;
9543
9544 /* This optimization is only reasonable if the constant table
9545 entries are only 4 bytes. */
9546 if (Pmode != SImode)
9547 return;
9548
9549 for (insn = first; insn != NULL_RTX; insn = next)
9550 {
9551 rtx set1, set2;
9552
9553 next = insn;
9554 do
9555 {
9556 next = NEXT_INSN (next);
9557 }
9558 while (next != NULL_RTX
9559 && (GET_CODE (next) == NOTE
9560 || (GET_CODE (next) == INSN
9561 && (GET_CODE (PATTERN (next)) == USE
9562 || GET_CODE (PATTERN (next)) == CLOBBER))));
9563
9564 if (next == NULL_RTX)
9565 break;
9566
9567 if (! INSN_P (insn))
9568 continue;
9569
9570 if (! INSN_P (next))
9571 continue;
9572
9573 set1 = PATTERN (insn);
9574 if (GET_CODE (set1) != SET)
9575 continue;
9576 set2 = PATTERN (next);
9577 if (GET_CODE (set2) != SET)
9578 continue;
9579
9580 if (GET_CODE (SET_DEST (set1)) == REG
9581 && GET_CODE (SET_SRC (set1)) == CONST
9582 && GET_CODE (XEXP (SET_SRC (set1), 0)) == REG
9583 && REGNO (XEXP (SET_SRC (set1), 0)) == GP_REG_FIRST + 28
9584 && rtx_equal_p (SET_DEST (set1), SET_DEST (set2))
9585 && GET_CODE (SET_SRC (set2)) == PLUS
9586 && rtx_equal_p (SET_DEST (set1), XEXP (SET_SRC (set2), 0))
9587 && mips16_gp_offset_p (XEXP (SET_SRC (set2), 1))
9588 && GET_CODE (XEXP (XEXP (SET_SRC (set2), 1), 0)) == MINUS)
9589 {
9590 rtx sym;
9591
9592 /* We've found a case we can change to load from the
9593 constant table. */
9594
9595 sym = XEXP (XEXP (XEXP (SET_SRC (set2), 1), 0), 0);
9596 if (GET_CODE (sym) != SYMBOL_REF)
9597 abort ();
9598 emit_insn_after (gen_rtx (SET, VOIDmode, SET_DEST (set1),
9599 force_const_mem (Pmode, sym)),
9600 next);
9601
9602 PUT_CODE (insn, NOTE);
9603 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9604 NOTE_SOURCE_FILE (insn) = 0;
9605
9606 PUT_CODE (next, NOTE);
9607 NOTE_LINE_NUMBER (next) = NOTE_INSN_DELETED;
9608 NOTE_SOURCE_FILE (next) = 0;
9609 }
9610 }
9611
9612 return;
9613 }
9614
9615 /* We can safely remove all assignments to SLOT from GPCOPY, and
9616 replace all assignments from SLOT to GPCOPY with assignments from
9617 $28. */
9618
9619 for (insn = first; insn != NULL_RTX; insn = next_active_insn (insn))
9620 {
9621 rtx set;
9622
9623 if (! INSN_P (insn))
9624 continue;
9625
9626 set = PATTERN (insn);
9627 if (GET_CODE (set) != SET
9628 || GET_MODE (SET_DEST (set)) != (unsigned) Pmode)
9629 continue;
9630
9631 if (GET_CODE (SET_DEST (set)) == MEM
9632 && rtx_equal_p (SET_DEST (set), slot)
9633 && GET_CODE (SET_SRC (set)) == REG
9634 && REGNO (SET_SRC (set)) == REGNO (gpcopy))
9635 {
9636 PUT_CODE (insn, NOTE);
9637 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9638 NOTE_SOURCE_FILE (insn) = 0;
9639 }
9640 else if (GET_CODE (SET_DEST (set)) == REG
9641 && REGNO (SET_DEST (set)) == REGNO (gpcopy)
9642 && GET_CODE (SET_SRC (set)) == MEM
9643 && rtx_equal_p (SET_SRC (set), slot))
9644 {
9645 emit_insn_after (gen_rtx (SET, Pmode, SET_DEST (set),
9646 gen_rtx (CONST, Pmode,
9647 gen_rtx (REG, Pmode,
9648 GP_REG_FIRST + 28))),
9649 insn);
9650 PUT_CODE (insn, NOTE);
9651 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9652 NOTE_SOURCE_FILE (insn) = 0;
9653 }
9654 }
9655 }
9656
9657 /* We keep a list of constants we which we have to add to internal
9658 constant tables in the middle of large functions. */
9659
9660 struct constant
9661 {
9662 struct constant *next;
9663 rtx value;
9664 rtx label;
9665 enum machine_mode mode;
9666 };
9667
9668 /* Add a constant to the list in *PCONSTANTS. */
9669
9670 static rtx
add_constant(pconstants,val,mode)9671 add_constant (pconstants, val, mode)
9672 struct constant **pconstants;
9673 rtx val;
9674 enum machine_mode mode;
9675 {
9676 struct constant *c;
9677
9678 for (c = *pconstants; c != NULL; c = c->next)
9679 if (mode == c->mode && rtx_equal_p (val, c->value))
9680 return c->label;
9681
9682 c = (struct constant *) xmalloc (sizeof *c);
9683 c->value = val;
9684 c->mode = mode;
9685 c->label = gen_label_rtx ();
9686 c->next = *pconstants;
9687 *pconstants = c;
9688 return c->label;
9689 }
9690
9691 /* Dump out the constants in CONSTANTS after INSN. */
9692
9693 static void
dump_constants(constants,insn)9694 dump_constants (constants, insn)
9695 struct constant *constants;
9696 rtx insn;
9697 {
9698 struct constant *c;
9699 int align;
9700
9701 c = constants;
9702 align = 0;
9703 while (c != NULL)
9704 {
9705 rtx r;
9706 struct constant *next;
9707
9708 switch (GET_MODE_SIZE (c->mode))
9709 {
9710 case 1:
9711 align = 0;
9712 break;
9713 case 2:
9714 if (align < 1)
9715 insn = emit_insn_after (gen_align_2 (), insn);
9716 align = 1;
9717 break;
9718 case 4:
9719 if (align < 2)
9720 insn = emit_insn_after (gen_align_4 (), insn);
9721 align = 2;
9722 break;
9723 default:
9724 if (align < 3)
9725 insn = emit_insn_after (gen_align_8 (), insn);
9726 align = 3;
9727 break;
9728 }
9729
9730 insn = emit_label_after (c->label, insn);
9731
9732 switch (c->mode)
9733 {
9734 case QImode:
9735 r = gen_consttable_qi (c->value);
9736 break;
9737 case HImode:
9738 r = gen_consttable_hi (c->value);
9739 break;
9740 case SImode:
9741 r = gen_consttable_si (c->value);
9742 break;
9743 case SFmode:
9744 r = gen_consttable_sf (c->value);
9745 break;
9746 case DImode:
9747 r = gen_consttable_di (c->value);
9748 break;
9749 case DFmode:
9750 r = gen_consttable_df (c->value);
9751 break;
9752 default:
9753 abort ();
9754 }
9755
9756 insn = emit_insn_after (r, insn);
9757
9758 next = c->next;
9759 free (c);
9760 c = next;
9761 }
9762
9763 emit_barrier_after (insn);
9764 }
9765
9766 /* Find the symbol in an address expression. */
9767
9768 static rtx
mips_find_symbol(addr)9769 mips_find_symbol (addr)
9770 rtx addr;
9771 {
9772 if (GET_CODE (addr) == MEM)
9773 addr = XEXP (addr, 0);
9774 while (GET_CODE (addr) == CONST)
9775 addr = XEXP (addr, 0);
9776 if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == LABEL_REF)
9777 return addr;
9778 if (GET_CODE (addr) == PLUS)
9779 {
9780 rtx l1, l2;
9781
9782 l1 = mips_find_symbol (XEXP (addr, 0));
9783 l2 = mips_find_symbol (XEXP (addr, 1));
9784 if (l1 != NULL_RTX && l2 == NULL_RTX)
9785 return l1;
9786 else if (l1 == NULL_RTX && l2 != NULL_RTX)
9787 return l2;
9788 }
9789 return NULL_RTX;
9790 }
9791
9792 /* Exported to toplev.c.
9793
9794 Do a final pass over the function, just before delayed branch
9795 scheduling. */
9796
9797 void
machine_dependent_reorg(first)9798 machine_dependent_reorg (first)
9799 rtx first;
9800 {
9801 int insns_len, max_internal_pool_size, pool_size, addr, first_constant_ref;
9802 rtx insn;
9803 struct constant *constants;
9804
9805 if (! TARGET_MIPS16)
9806 return;
9807
9808 /* If $gp is used, try to remove stores, and replace loads with
9809 copies from $gp. */
9810 if (optimize)
9811 mips16_optimize_gp (first);
9812
9813 /* Scan the function looking for PC relative loads which may be out
9814 of range. All such loads will either be from the constant table,
9815 or be getting the address of a constant string. If the size of
9816 the function plus the size of the constant table is less than
9817 0x8000, then all loads are in range. */
9818
9819 insns_len = 0;
9820 for (insn = first; insn; insn = NEXT_INSN (insn))
9821 {
9822 insns_len += get_attr_length (insn);
9823
9824 /* ??? We put switch tables in .text, but we don't define
9825 JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
9826 compute their lengths correctly. */
9827 if (GET_CODE (insn) == JUMP_INSN)
9828 {
9829 rtx body;
9830
9831 body = PATTERN (insn);
9832 if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC)
9833 insns_len += (XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC)
9834 * GET_MODE_SIZE (GET_MODE (body)));
9835 insns_len += GET_MODE_SIZE (GET_MODE (body)) - 1;
9836 }
9837 }
9838
9839 /* Store the original value of insns_len in cfun->machine, so
9840 that simple_memory_operand can look at it. */
9841 cfun->machine->insns_len = insns_len;
9842
9843 pool_size = get_pool_size ();
9844 if (insns_len + pool_size + mips_string_length < 0x8000)
9845 return;
9846
9847 /* Loop over the insns and figure out what the maximum internal pool
9848 size could be. */
9849 max_internal_pool_size = 0;
9850 for (insn = first; insn; insn = NEXT_INSN (insn))
9851 {
9852 if (GET_CODE (insn) == INSN
9853 && GET_CODE (PATTERN (insn)) == SET)
9854 {
9855 rtx src;
9856
9857 src = mips_find_symbol (SET_SRC (PATTERN (insn)));
9858 if (src == NULL_RTX)
9859 continue;
9860 if (CONSTANT_POOL_ADDRESS_P (src))
9861 max_internal_pool_size += GET_MODE_SIZE (get_pool_mode (src));
9862 else if (SYMBOL_REF_FLAG (src))
9863 max_internal_pool_size += GET_MODE_SIZE (Pmode);
9864 }
9865 }
9866
9867 constants = NULL;
9868 addr = 0;
9869 first_constant_ref = -1;
9870
9871 for (insn = first; insn; insn = NEXT_INSN (insn))
9872 {
9873 if (GET_CODE (insn) == INSN
9874 && GET_CODE (PATTERN (insn)) == SET)
9875 {
9876 rtx val, src;
9877 enum machine_mode mode = VOIDmode;
9878
9879 val = NULL_RTX;
9880 src = mips_find_symbol (SET_SRC (PATTERN (insn)));
9881 if (src != NULL_RTX && CONSTANT_POOL_ADDRESS_P (src))
9882 {
9883 /* ??? This is very conservative, which means that we
9884 will generate too many copies of the constant table.
9885 The only solution would seem to be some form of
9886 relaxing. */
9887 if (((insns_len - addr)
9888 + max_internal_pool_size
9889 + get_pool_offset (src))
9890 >= 0x8000)
9891 {
9892 val = get_pool_constant (src);
9893 mode = get_pool_mode (src);
9894 }
9895 max_internal_pool_size -= GET_MODE_SIZE (get_pool_mode (src));
9896 }
9897 else if (src != NULL_RTX && SYMBOL_REF_FLAG (src))
9898 {
9899 /* Including all of mips_string_length is conservative,
9900 and so is including all of max_internal_pool_size. */
9901 if (((insns_len - addr)
9902 + max_internal_pool_size
9903 + pool_size
9904 + mips_string_length)
9905 >= 0x8000)
9906 {
9907 val = src;
9908 mode = Pmode;
9909 }
9910 max_internal_pool_size -= Pmode;
9911 }
9912
9913 if (val != NULL_RTX)
9914 {
9915 rtx lab, newsrc;
9916
9917 /* This PC relative load is out of range. ??? In the
9918 case of a string constant, we are only guessing that
9919 it is range, since we don't know the offset of a
9920 particular string constant. */
9921
9922 lab = add_constant (&constants, val, mode);
9923 newsrc = gen_rtx (MEM, mode,
9924 gen_rtx (LABEL_REF, VOIDmode, lab));
9925 RTX_UNCHANGING_P (newsrc) = 1;
9926 PATTERN (insn) = gen_rtx (SET, VOIDmode,
9927 SET_DEST (PATTERN (insn)),
9928 newsrc);
9929 INSN_CODE (insn) = -1;
9930
9931 if (first_constant_ref < 0)
9932 first_constant_ref = addr;
9933 }
9934 }
9935
9936 addr += get_attr_length (insn);
9937
9938 /* ??? We put switch tables in .text, but we don't define
9939 JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
9940 compute their lengths correctly. */
9941 if (GET_CODE (insn) == JUMP_INSN)
9942 {
9943 rtx body;
9944
9945 body = PATTERN (insn);
9946 if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC)
9947 addr += (XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC)
9948 * GET_MODE_SIZE (GET_MODE (body)));
9949 addr += GET_MODE_SIZE (GET_MODE (body)) - 1;
9950 }
9951
9952 if (GET_CODE (insn) == BARRIER)
9953 {
9954 /* Output any constants we have accumulated. Note that we
9955 don't need to change ADDR, since its only use is
9956 subtraction from INSNS_LEN, and both would be changed by
9957 the same amount.
9958 ??? If the instructions up to the next barrier reuse a
9959 constant, it would often be better to continue
9960 accumulating. */
9961 if (constants != NULL)
9962 dump_constants (constants, insn);
9963 constants = NULL;
9964 first_constant_ref = -1;
9965 }
9966
9967 if (constants != NULL
9968 && (NEXT_INSN (insn) == NULL
9969 || (first_constant_ref >= 0
9970 && (((addr - first_constant_ref)
9971 + 2 /* for alignment */
9972 + 2 /* for a short jump insn */
9973 + pool_size)
9974 >= 0x8000))))
9975 {
9976 /* If we haven't had a barrier within 0x8000 bytes of a
9977 constant reference or we are at the end of the function,
9978 emit a barrier now. */
9979
9980 rtx label, jump, barrier;
9981
9982 label = gen_label_rtx ();
9983 jump = emit_jump_insn_after (gen_jump (label), insn);
9984 JUMP_LABEL (jump) = label;
9985 LABEL_NUSES (label) = 1;
9986 barrier = emit_barrier_after (jump);
9987 emit_label_after (label, barrier);
9988 first_constant_ref = -1;
9989 }
9990 }
9991
9992 /* ??? If we output all references to a constant in internal
9993 constants table, we don't need to output the constant in the real
9994 constant table, but we have no way to prevent that. */
9995 }
9996
9997 /* Return nonzero if X is a SIGN or ZERO extend operator. */
9998 int
extend_operator(x,mode)9999 extend_operator (x, mode)
10000 rtx x;
10001 enum machine_mode mode ATTRIBUTE_UNUSED;
10002 {
10003 enum rtx_code code = GET_CODE (x);
10004 return code == SIGN_EXTEND || code == ZERO_EXTEND;
10005 }
10006
10007 /* Accept any operator that can be used to shift the high half of the
10008 input value to the lower half, suitable for truncation. The
10009 remainder (the lower half of the input, and the upper half of the
10010 output) will be discarded. */
10011 int
highpart_shift_operator(x,mode)10012 highpart_shift_operator (x, mode)
10013 rtx x;
10014 enum machine_mode mode ATTRIBUTE_UNUSED;
10015 {
10016 enum rtx_code code = GET_CODE (x);
10017 return (code == LSHIFTRT
10018 || code == ASHIFTRT
10019 || code == ROTATERT
10020 || code == ROTATE);
10021 }
10022
10023 /* Return a number assessing the cost of moving a register in class
10024 FROM to class TO. The classes are expressed using the enumeration
10025 values such as `GENERAL_REGS'. A value of 2 is the default; other
10026 values are interpreted relative to that.
10027
10028 It is not required that the cost always equal 2 when FROM is the
10029 same as TO; on some machines it is expensive to move between
10030 registers if they are not general registers.
10031
10032 If reload sees an insn consisting of a single `set' between two
10033 hard registers, and if `REGISTER_MOVE_COST' applied to their
10034 classes returns a value of 2, reload does not check to ensure that
10035 the constraints of the insn are met. Setting a cost of other than
10036 2 will allow reload to verify that the constraints are met. You
10037 should do this if the `movM' pattern's constraints do not allow
10038 such copying.
10039
10040 ??? We make make the cost of moving from HI/LO/HILO/MD into general
10041 registers the same as for one of moving general registers to
10042 HI/LO/HILO/MD for TARGET_MIPS16 in order to prevent allocating a
10043 pseudo to HI/LO/HILO/MD. This might hurt optimizations though, it
10044 isn't clear if it is wise. And it might not work in all cases. We
10045 could solve the DImode LO reg problem by using a multiply, just
10046 like reload_{in,out}si. We could solve the SImode/HImode HI reg
10047 problem by using divide instructions. divu puts the remainder in
10048 the HI reg, so doing a divide by -1 will move the value in the HI
10049 reg for all values except -1. We could handle that case by using a
10050 signed divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit
10051 a compare/branch to test the input value to see which instruction
10052 we need to use. This gets pretty messy, but it is feasible. */
10053
10054 int
mips_register_move_cost(mode,to,from)10055 mips_register_move_cost (mode, to, from)
10056 enum machine_mode mode ATTRIBUTE_UNUSED;
10057 enum reg_class to, from;
10058 {
10059 if (from == M16_REGS && GR_REG_CLASS_P (to))
10060 return 2;
10061 else if (from == M16_NA_REGS && GR_REG_CLASS_P (to))
10062 return 2;
10063 else if (GR_REG_CLASS_P (from))
10064 {
10065 if (to == M16_REGS)
10066 return 2;
10067 else if (to == M16_NA_REGS)
10068 return 2;
10069 else if (GR_REG_CLASS_P (to))
10070 {
10071 if (TARGET_MIPS16)
10072 return 4;
10073 else
10074 return 2;
10075 }
10076 else if (to == FP_REGS)
10077 return 4;
10078 else if (to == HI_REG || to == LO_REG || to == MD_REGS
10079 || to == HILO_REG)
10080 {
10081 if (TARGET_MIPS16)
10082 return 12;
10083 else
10084 return 6;
10085 }
10086 else if (COP_REG_CLASS_P (to))
10087 {
10088 return 5;
10089 }
10090 } /* GR_REG_CLASS_P (from) */
10091 else if (from == FP_REGS)
10092 {
10093 if (GR_REG_CLASS_P (to))
10094 return 4;
10095 else if (to == FP_REGS)
10096 return 2;
10097 else if (to == ST_REGS)
10098 return 8;
10099 } /* from == FP_REGS */
10100 else if (from == HI_REG || from == LO_REG || from == MD_REGS
10101 || from == HILO_REG)
10102 {
10103 if (GR_REG_CLASS_P (to))
10104 {
10105 if (TARGET_MIPS16)
10106 return 12;
10107 else
10108 return 6;
10109 }
10110 } /* from == HI_REG, etc. */
10111 else if (from == ST_REGS && GR_REG_CLASS_P (to))
10112 return 4;
10113 else if (COP_REG_CLASS_P (from))
10114 {
10115 return 5;
10116 } /* COP_REG_CLASS_P (from) */
10117
10118 /* fallthru */
10119
10120 return 12;
10121 }
10122
10123 /* Return the length of INSN. LENGTH is the initial length computed by
10124 attributes in the machine-description file. */
10125
10126 int
mips_adjust_insn_length(insn,length)10127 mips_adjust_insn_length (insn, length)
10128 rtx insn;
10129 int length;
10130 {
10131 /* A unconditional jump has an unfilled delay slot if it is not part
10132 of a sequence. A conditional jump normally has a delay slot, but
10133 does not on MIPS16. */
10134 if (simplejump_p (insn)
10135 || (!TARGET_MIPS16 && (GET_CODE (insn) == JUMP_INSN
10136 || GET_CODE (insn) == CALL_INSN)))
10137 length += 4;
10138
10139 /* All MIPS16 instructions are a measly two bytes. */
10140 if (TARGET_MIPS16)
10141 length /= 2;
10142
10143 return length;
10144 }
10145
10146 /* Output assembly instructions to peform a conditional branch.
10147
10148 INSN is the branch instruction. OPERANDS[0] is the condition.
10149 OPERANDS[1] is the target of the branch. OPERANDS[2] is the target
10150 of the first operand to the condition. If TWO_OPERANDS_P is
10151 nonzero the comparison takes two operands; OPERANDS[3] will be the
10152 second operand.
10153
10154 If INVERTED_P is nonzero we are to branch if the condition does
10155 not hold. If FLOAT_P is nonzero this is a floating-point comparison.
10156
10157 LENGTH is the length (in bytes) of the sequence we are to generate.
10158 That tells us whether to generate a simple conditional branch, or a
10159 reversed conditional branch around a `jr' instruction. */
10160 const char *
mips_output_conditional_branch(insn,operands,two_operands_p,float_p,inverted_p,length)10161 mips_output_conditional_branch (insn,
10162 operands,
10163 two_operands_p,
10164 float_p,
10165 inverted_p,
10166 length)
10167 rtx insn;
10168 rtx *operands;
10169 int two_operands_p;
10170 int float_p;
10171 int inverted_p;
10172 int length;
10173 {
10174 static char buffer[200];
10175 /* The kind of comparison we are doing. */
10176 enum rtx_code code = GET_CODE (operands[0]);
10177 /* Nonzero if the opcode for the comparison needs a `z' indicating
10178 that it is a comparision against zero. */
10179 int need_z_p;
10180 /* A string to use in the assembly output to represent the first
10181 operand. */
10182 const char *op1 = "%z2";
10183 /* A string to use in the assembly output to represent the second
10184 operand. Use the hard-wired zero register if there's no second
10185 operand. */
10186 const char *op2 = (two_operands_p ? ",%z3" : ",%.");
10187 /* The operand-printing string for the comparison. */
10188 const char *const comp = (float_p ? "%F0" : "%C0");
10189 /* The operand-printing string for the inverted comparison. */
10190 const char *const inverted_comp = (float_p ? "%W0" : "%N0");
10191
10192 /* The MIPS processors (for levels of the ISA at least two), have
10193 "likely" variants of each branch instruction. These instructions
10194 annul the instruction in the delay slot if the branch is not
10195 taken. */
10196 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
10197
10198 if (!two_operands_p)
10199 {
10200 /* To compute whether than A > B, for example, we normally
10201 subtract B from A and then look at the sign bit. But, if we
10202 are doing an unsigned comparison, and B is zero, we don't
10203 have to do the subtraction. Instead, we can just check to
10204 see if A is nonzero. Thus, we change the CODE here to
10205 reflect the simpler comparison operation. */
10206 switch (code)
10207 {
10208 case GTU:
10209 code = NE;
10210 break;
10211
10212 case LEU:
10213 code = EQ;
10214 break;
10215
10216 case GEU:
10217 /* A condition which will always be true. */
10218 code = EQ;
10219 op1 = "%.";
10220 break;
10221
10222 case LTU:
10223 /* A condition which will always be false. */
10224 code = NE;
10225 op1 = "%.";
10226 break;
10227
10228 default:
10229 /* Not a special case. */
10230 break;
10231 }
10232 }
10233
10234 /* Relative comparisons are always done against zero. But
10235 equality comparisons are done between two operands, and therefore
10236 do not require a `z' in the assembly language output. */
10237 need_z_p = (!float_p && code != EQ && code != NE);
10238 /* For comparisons against zero, the zero is not provided
10239 explicitly. */
10240 if (need_z_p)
10241 op2 = "";
10242
10243 /* Begin by terminating the buffer. That way we can always use
10244 strcat to add to it. */
10245 buffer[0] = '\0';
10246
10247 switch (length)
10248 {
10249 case 4:
10250 case 8:
10251 /* Just a simple conditional branch. */
10252 if (float_p)
10253 sprintf (buffer, "%%*b%s%%?\t%%Z2%%1",
10254 inverted_p ? inverted_comp : comp);
10255 else
10256 sprintf (buffer, "%%*b%s%s%%?\t%s%s,%%1",
10257 inverted_p ? inverted_comp : comp,
10258 need_z_p ? "z" : "",
10259 op1,
10260 op2);
10261 return buffer;
10262
10263 case 12:
10264 case 16:
10265 case 24:
10266 case 28:
10267 {
10268 /* Generate a reversed conditional branch around ` j'
10269 instruction:
10270
10271 .set noreorder
10272 .set nomacro
10273 bc l
10274 delay_slot or #nop
10275 j target
10276 #nop
10277 l:
10278 .set macro
10279 .set reorder
10280
10281 If the original branch was a likely branch, the delay slot
10282 must be executed only if the branch is taken, so generate:
10283
10284 .set noreorder
10285 .set nomacro
10286 bc l
10287 #nop
10288 j target
10289 delay slot or #nop
10290 l:
10291 .set macro
10292 .set reorder
10293
10294 When generating non-embedded PIC, instead of:
10295
10296 j target
10297
10298 we emit:
10299
10300 .set noat
10301 la $at, target
10302 jr $at
10303 .set at
10304 */
10305
10306 rtx orig_target;
10307 rtx target = gen_label_rtx ();
10308
10309 orig_target = operands[1];
10310 operands[1] = target;
10311 /* Generate the reversed comparison. This takes four
10312 bytes. */
10313 if (float_p)
10314 sprintf (buffer, "%%*b%s\t%%Z2%%1",
10315 inverted_p ? comp : inverted_comp);
10316 else
10317 sprintf (buffer, "%%*b%s%s\t%s%s,%%1",
10318 inverted_p ? comp : inverted_comp,
10319 need_z_p ? "z" : "",
10320 op1,
10321 op2);
10322 output_asm_insn (buffer, operands);
10323
10324 if (length != 16 && length != 28 && ! mips_branch_likely)
10325 {
10326 /* Output delay slot instruction. */
10327 rtx insn = final_sequence;
10328 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file,
10329 optimize, 0, 1);
10330 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
10331 }
10332 else
10333 output_asm_insn ("%#", 0);
10334
10335 if (length <= 16)
10336 output_asm_insn ("j\t%0", &orig_target);
10337 else
10338 {
10339 if (Pmode == DImode)
10340 output_asm_insn ("%[dla\t%@,%0\n\tjr\t%@%]", &orig_target);
10341 else
10342 output_asm_insn ("%[la\t%@,%0\n\tjr\t%@%]", &orig_target);
10343 }
10344
10345 if (length != 16 && length != 28 && mips_branch_likely)
10346 {
10347 /* Output delay slot instruction. */
10348 rtx insn = final_sequence;
10349 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file,
10350 optimize, 0, 1);
10351 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
10352 }
10353 else
10354 output_asm_insn ("%#", 0);
10355
10356 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
10357 CODE_LABEL_NUMBER (target));
10358
10359 return "";
10360 }
10361
10362 /* We do not currently use this code. It handles jumps to
10363 arbitrary locations, using `jr', even across a 256MB boundary.
10364 We could add a -mhuge switch, and then use this code instead of
10365 the `j' alternative above when -mhuge was used. */
10366 #if 0
10367 case 16:
10368 case 20:
10369 {
10370 /* Generate a reversed conditional branch around a `jr'
10371 instruction:
10372
10373 .set noreorder
10374 .set nomacro
10375 .set noat
10376 bc l
10377 la $at, target
10378 jr $at
10379 .set at
10380 .set macro
10381 .set reorder
10382 l:
10383
10384 Not pretty, but allows a conditional branch anywhere in the
10385 32-bit address space. If the original branch is annulled,
10386 then the instruction in the delay slot should be executed
10387 only if the branch is taken. The la instruction is really
10388 a macro which will usually take eight bytes, but sometimes
10389 takes only four, if the instruction to which we're jumping
10390 gets its own entry in the global pointer table, which will
10391 happen if its a case label. The assembler will then
10392 generate only a four-byte sequence, rather than eight, and
10393 there seems to be no way to tell it not to. Thus, we can't
10394 just use a `.+x' addressing form; we don't know what value
10395 to give for `x'.
10396
10397 So, we resort to using the explicit relocation syntax
10398 available in the assembler and do:
10399
10400 lw $at,%got_page(target)($gp)
10401 daddiu $at,$at,%got_ofst(target)
10402
10403 That way, this always takes up eight bytes, and we can use
10404 the `.+x' form. Of course, these explicit machinations
10405 with relocation will not work with old assemblers. Then
10406 again, neither do out-of-range branches, so we haven't lost
10407 anything. */
10408
10409 /* The target of the reversed branch. */
10410 const char *const target
10411 = ((mips_branch_likely || length == 20) ? ".+20" : ".+16");
10412 const char *at_register = mips_reg_names[ASSEMBLER_SCRATCH_REGNUM];
10413 const char *gp_register = mips_reg_names[PIC_OFFSET_TABLE_REGNUM];
10414 char *c;
10415
10416 strcpy (buffer, "%(%<%[");
10417 c = strchr (buffer, '\0');
10418 /* Generate the reversed comparision. This takes four
10419 bytes. */
10420 if (float_p)
10421 sprintf (c, "%%*b%s\t%%Z2%s",
10422 inverted_p ? comp : inverted_comp,
10423 target);
10424 else
10425 sprintf (c, "%%*b%s%s\t%s%s,%s",
10426 inverted_p ? comp : inverted_comp,
10427 need_z_p ? "z" : "",
10428 op1,
10429 op2,
10430 target);
10431 c = strchr (buffer, '\0');
10432 /* Generate the load-address, and jump. This takes twelve
10433 bytes, for a total of 16. */
10434 sprintf (c,
10435 "\n\tlw\t%s,%%%%got_page(%%1)(%s)\n\tdaddiu\t%s,%s,%%%%got_ofst(%%1)\n\tjr\t%s",
10436 at_register,
10437 gp_register,
10438 at_register,
10439 at_register,
10440 at_register);
10441 if (length == 20)
10442 /* The delay slot was unfilled. Since we're inside
10443 .noreorder, the assembler will not fill in the NOP for
10444 us, so we must do it ourselves. */
10445 strcat (buffer, "\n\tnop");
10446 strcat (buffer, "%]%>%)");
10447 return buffer;
10448 }
10449 #endif
10450
10451 default:
10452 abort ();
10453 }
10454
10455 /* NOTREACHED */
10456 return 0;
10457 }
10458
10459 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
10460 with a final "000" replaced by "k". Ignore case.
10461
10462 Note: this function is shared between GCC and GAS. */
10463
10464 static bool
mips_strict_matching_cpu_name_p(canonical,given)10465 mips_strict_matching_cpu_name_p (canonical, given)
10466 const char *canonical, *given;
10467 {
10468 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
10469 given++, canonical++;
10470
10471 return ((*given == 0 && *canonical == 0)
10472 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
10473 }
10474
10475
10476 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
10477 CPU name. We've traditionally allowed a lot of variation here.
10478
10479 Note: this function is shared between GCC and GAS. */
10480
10481 static bool
mips_matching_cpu_name_p(canonical,given)10482 mips_matching_cpu_name_p (canonical, given)
10483 const char *canonical, *given;
10484 {
10485 /* First see if the name matches exactly, or with a final "000"
10486 turned into "k". */
10487 if (mips_strict_matching_cpu_name_p (canonical, given))
10488 return true;
10489
10490 /* If not, try comparing based on numerical designation alone.
10491 See if GIVEN is an unadorned number, or 'r' followed by a number. */
10492 if (TOLOWER (*given) == 'r')
10493 given++;
10494 if (!ISDIGIT (*given))
10495 return false;
10496
10497 /* Skip over some well-known prefixes in the canonical name,
10498 hoping to find a number there too. */
10499 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
10500 canonical += 2;
10501 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
10502 canonical += 2;
10503 else if (TOLOWER (canonical[0]) == 'r')
10504 canonical += 1;
10505
10506 return mips_strict_matching_cpu_name_p (canonical, given);
10507 }
10508
10509
10510 /* Parse an option that takes the name of a processor as its argument.
10511 OPTION is the name of the option and CPU_STRING is the argument.
10512 Return the corresponding processor enumeration if the CPU_STRING is
10513 recognized, otherwise report an error and return null.
10514
10515 A similar function exists in GAS. */
10516
10517 static const struct mips_cpu_info *
mips_parse_cpu(option,cpu_string)10518 mips_parse_cpu (option, cpu_string)
10519 const char *option, *cpu_string;
10520 {
10521 const struct mips_cpu_info *p;
10522 const char *s;
10523
10524 /* In the past, we allowed upper-case CPU names, but it doesn't
10525 work well with the multilib machinery. */
10526 for (s = cpu_string; *s != 0; s++)
10527 if (ISUPPER (*s))
10528 {
10529 warning ("the cpu name must be lower case");
10530 break;
10531 }
10532
10533 /* 'from-abi' selects the most compatible architecture for the given
10534 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
10535 EABIs, we have to decide whether we're using the 32-bit or 64-bit
10536 version. Look first at the -mgp options, if given, otherwise base
10537 the choice on MASK_64BIT in TARGET_DEFAULT. */
10538 if (strcasecmp (cpu_string, "from-abi") == 0)
10539 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
10540 : ABI_NEEDS_64BIT_REGS ? 3
10541 : (TARGET_64BIT ? 3 : 1));
10542
10543 /* 'default' has traditionally been a no-op. Probably not very useful. */
10544 if (strcasecmp (cpu_string, "default") == 0)
10545 return 0;
10546
10547 for (p = mips_cpu_info_table; p->name != 0; p++)
10548 if (mips_matching_cpu_name_p (p->name, cpu_string))
10549 return p;
10550
10551 error ("bad value (%s) for %s", cpu_string, option);
10552 return 0;
10553 }
10554
10555
10556 /* Return the processor associated with the given ISA level, or null
10557 if the ISA isn't valid. */
10558
10559 static const struct mips_cpu_info *
mips_cpu_info_from_isa(isa)10560 mips_cpu_info_from_isa (isa)
10561 int isa;
10562 {
10563 const struct mips_cpu_info *p;
10564
10565 for (p = mips_cpu_info_table; p->name != 0; p++)
10566 if (p->isa == isa)
10567 return p;
10568
10569 return 0;
10570 }
10571
10572 /* Adjust the cost of INSN based on the relationship between INSN that
10573 is dependent on DEP_INSN through the dependence LINK. The default
10574 is to make no adjustment to COST.
10575
10576 On the MIPS, ignore the cost of anti- and output-dependencies. */
10577 static int
mips_adjust_cost(insn,link,dep,cost)10578 mips_adjust_cost (insn, link, dep, cost)
10579 rtx insn ATTRIBUTE_UNUSED;
10580 rtx link;
10581 rtx dep ATTRIBUTE_UNUSED;
10582 int cost;
10583 {
10584 if (REG_NOTE_KIND (link) != 0)
10585 return 0; /* Anti or output dependence. */
10586 return cost;
10587 }
10588
10589 /* ??? This could be replaced with the default elf version if
10590 TARGET_IS_SMALL_DATA_P is set properly. */
10591
10592 static void
mips_unique_section(decl,reloc)10593 mips_unique_section (decl, reloc)
10594 tree decl;
10595 int reloc;
10596 {
10597 int len, size, sec;
10598 const char *name, *prefix;
10599 char *string;
10600 static const char *const prefixes[4][2] = {
10601 { ".text.", ".gnu.linkonce.t." },
10602 { ".rodata.", ".gnu.linkonce.r." },
10603 { ".data.", ".gnu.linkonce.d." },
10604 { ".sdata.", ".gnu.linkonce.s." }
10605 };
10606
10607 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
10608 name = (* targetm.strip_name_encoding) (name);
10609 size = int_size_in_bytes (TREE_TYPE (decl));
10610
10611 /* Determine the base section we are interested in:
10612 0=text, 1=rodata, 2=data, 3=sdata, [4=bss]. */
10613 if (TREE_CODE (decl) == FUNCTION_DECL)
10614 sec = 0;
10615 else if (DECL_INITIAL (decl) == 0
10616 || DECL_INITIAL (decl) == error_mark_node)
10617 sec = 2;
10618 else if ((TARGET_EMBEDDED_PIC || TARGET_MIPS16)
10619 && TREE_CODE (decl) == STRING_CST
10620 && !flag_writable_strings)
10621 {
10622 /* For embedded position independent code, put constant
10623 strings in the text section, because the data section
10624 is limited to 64K in size. For mips16 code, put
10625 strings in the text section so that a PC relative load
10626 instruction can be used to get their address. */
10627 sec = 0;
10628 }
10629 else if (TARGET_EMBEDDED_DATA)
10630 {
10631 /* For embedded applications, always put an object in
10632 read-only data if possible, in order to reduce RAM
10633 usage. */
10634
10635 if (decl_readonly_section (decl, reloc))
10636 sec = 1;
10637 else if (size > 0 && size <= mips_section_threshold)
10638 sec = 3;
10639 else
10640 sec = 2;
10641 }
10642 else
10643 {
10644 /* For hosted applications, always put an object in
10645 small data if possible, as this gives the best
10646 performance. */
10647
10648 if (size > 0 && size <= mips_section_threshold)
10649 sec = 3;
10650 else if (decl_readonly_section (decl, reloc))
10651 sec = 1;
10652 else
10653 sec = 2;
10654 }
10655
10656 prefix = prefixes[sec][DECL_ONE_ONLY (decl)];
10657 len = strlen (name) + strlen (prefix);
10658 string = alloca (len + 1);
10659 sprintf (string, "%s%s", prefix, name);
10660
10661 DECL_SECTION_NAME (decl) = build_string (len, string);
10662 }
10663
10664 unsigned int
mips_hard_regno_nregs(regno,mode)10665 mips_hard_regno_nregs (regno, mode)
10666 int regno;
10667 enum machine_mode mode;
10668 {
10669 if (! FP_REG_P (regno))
10670 return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
10671 else
10672 return ((GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG);
10673 }
10674
10675 int
mips_return_in_memory(type)10676 mips_return_in_memory (type)
10677 tree type;
10678 {
10679 /* Under the old (i.e., 32 and O64 ABIs) all BLKmode objects are
10680 returned in memory. Under the new (N32 and 64-bit MIPS ABIs) small
10681 structures are returned in a register. Objects with varying size
10682 must still be returned in memory, of course. */
10683
10684 if (mips_abi == ABI_32 || mips_abi == ABI_O64)
10685 return (TYPE_MODE (type) == BLKmode);
10686 else
10687 return ((int_size_in_bytes (type) > (2 * UNITS_PER_WORD))
10688 || (int_size_in_bytes (type) == -1));
10689 }
10690
10691 static int
mips_issue_rate()10692 mips_issue_rate ()
10693 {
10694 switch (mips_tune)
10695 {
10696 case PROCESSOR_R3000: return 1;
10697 case PROCESSOR_R5400: return 2;
10698 case PROCESSOR_R5500: return 2;
10699
10700 default:
10701 return 1;
10702 }
10703
10704 abort ();
10705
10706 }
10707
10708 /* Implements TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE. Return true for
10709 processors that have a DFA pipeline description. */
10710
10711 static int
mips_use_dfa_pipeline_interface()10712 mips_use_dfa_pipeline_interface ()
10713 {
10714 switch (mips_tune)
10715 {
10716 case PROCESSOR_R5400:
10717 case PROCESSOR_R5500:
10718 case PROCESSOR_SR71000:
10719 return true;
10720
10721 default:
10722 return false;
10723 }
10724 }
10725
10726
10727 const char *
mips_emit_prefetch(operands)10728 mips_emit_prefetch (operands)
10729 rtx operands[];
10730 {
10731 /* For the mips32/64 architectures the hint fields are arranged
10732 by operation (load/store) and locality (normal/streamed/retained).
10733 Irritatingly, numbers 2 and 3 are reserved leaving no simple
10734 algorithm for figuring the hint. */
10735
10736 int write = INTVAL (operands[1]);
10737 int locality = INTVAL (operands[2]);
10738
10739 static const char * const alt[2][4] = {
10740 {
10741 "pref\t4,%a0",
10742 "pref\t0,%a0",
10743 "pref\t0,%a0",
10744 "pref\t6,%a0"
10745 },
10746 {
10747 "pref\t5,%a0",
10748 "pref\t1,%a0",
10749 "pref\t1,%a0",
10750 "pref\t7,%a0"
10751 }
10752 };
10753
10754 return alt[write][locality];
10755 }
10756
10757
10758
10759 #ifdef TARGET_IRIX6
10760 /* Output assembly to switch to section NAME with attribute FLAGS. */
10761
10762 static void
iris6_asm_named_section_1(name,flags,align)10763 iris6_asm_named_section_1 (name, flags, align)
10764 const char *name;
10765 unsigned int flags;
10766 unsigned int align;
10767 {
10768 unsigned int sh_type, sh_flags, sh_entsize;
10769
10770 sh_flags = 0;
10771 if (!(flags & SECTION_DEBUG))
10772 sh_flags |= 2; /* SHF_ALLOC */
10773 if (flags & SECTION_WRITE)
10774 sh_flags |= 1; /* SHF_WRITE */
10775 if (flags & SECTION_CODE)
10776 sh_flags |= 4; /* SHF_EXECINSTR */
10777 if (flags & SECTION_SMALL)
10778 sh_flags |= 0x10000000; /* SHF_MIPS_GPREL */
10779 if (strcmp (name, ".debug_frame") == 0)
10780 sh_flags |= 0x08000000; /* SHF_MIPS_NOSTRIP */
10781 if (flags & SECTION_DEBUG)
10782 sh_type = 0x7000001e; /* SHT_MIPS_DWARF */
10783 else if (flags & SECTION_BSS)
10784 sh_type = 8; /* SHT_NOBITS */
10785 else
10786 sh_type = 1; /* SHT_PROGBITS */
10787
10788 if (flags & SECTION_CODE)
10789 sh_entsize = 4;
10790 else
10791 sh_entsize = 0;
10792
10793 fprintf (asm_out_file, "\t.section %s,%#x,%#x,%u,%u\n",
10794 name, sh_type, sh_flags, sh_entsize, align);
10795 }
10796
10797 static void
iris6_asm_named_section(name,flags)10798 iris6_asm_named_section (name, flags)
10799 const char *name;
10800 unsigned int flags;
10801 {
10802 if (TARGET_FILE_SWITCHING && (flags & SECTION_CODE))
10803 asm_out_file = asm_out_text_file;
10804 iris6_asm_named_section_1 (name, flags, 0);
10805 }
10806
10807 /* In addition to emitting a .align directive, record the maximum
10808 alignment requested for the current section. */
10809
10810 struct iris_section_align_entry
10811 {
10812 const char *name;
10813 unsigned int log;
10814 unsigned int flags;
10815 };
10816
10817 static htab_t iris_section_align_htab;
10818 static FILE *iris_orig_asm_out_file;
10819
10820 static int
iris_section_align_entry_eq(p1,p2)10821 iris_section_align_entry_eq (p1, p2)
10822 const PTR p1;
10823 const PTR p2;
10824 {
10825 const struct iris_section_align_entry *old = p1;
10826 const char *new = p2;
10827
10828 return strcmp (old->name, new) == 0;
10829 }
10830
10831 static hashval_t
iris_section_align_entry_hash(p)10832 iris_section_align_entry_hash (p)
10833 const PTR p;
10834 {
10835 const struct iris_section_align_entry *old = p;
10836 return htab_hash_string (old->name);
10837 }
10838
10839 void
iris6_asm_output_align(file,log)10840 iris6_asm_output_align (file, log)
10841 FILE *file;
10842 unsigned int log;
10843 {
10844 const char *section = current_section_name ();
10845 struct iris_section_align_entry **slot, *entry;
10846
10847 if (! section)
10848 abort ();
10849
10850 slot = (struct iris_section_align_entry **)
10851 htab_find_slot_with_hash (iris_section_align_htab, section,
10852 htab_hash_string (section), INSERT);
10853 entry = *slot;
10854 if (! entry)
10855 {
10856 entry = (struct iris_section_align_entry *)
10857 xmalloc (sizeof (struct iris_section_align_entry));
10858 *slot = entry;
10859 entry->name = section;
10860 entry->log = log;
10861 entry->flags = current_section_flags ();
10862 }
10863 else if (entry->log < log)
10864 entry->log = log;
10865
10866 fprintf (file, "\t.align\t%u\n", log);
10867 }
10868
10869 /* The Iris assembler does not record alignment from .align directives,
10870 but takes it from the first .section directive seen. Play yet more
10871 file switching games so that we can emit a .section directive at the
10872 beginning of the file with the proper alignment attached. */
10873
10874 void
iris6_asm_file_start(stream)10875 iris6_asm_file_start (stream)
10876 FILE *stream;
10877 {
10878 mips_asm_file_start (stream);
10879
10880 iris_orig_asm_out_file = asm_out_file;
10881 stream = tmpfile ();
10882 asm_out_file = stream;
10883 asm_out_data_file = stream;
10884 if (! TARGET_FILE_SWITCHING)
10885 asm_out_text_file = stream;
10886
10887 iris_section_align_htab = htab_create (31, iris_section_align_entry_hash,
10888 iris_section_align_entry_eq, NULL);
10889 }
10890
10891 static int
iris6_section_align_1(slot,data)10892 iris6_section_align_1 (slot, data)
10893 void **slot;
10894 void *data ATTRIBUTE_UNUSED;
10895 {
10896 const struct iris_section_align_entry *entry
10897 = *(const struct iris_section_align_entry **) slot;
10898
10899 iris6_asm_named_section_1 (entry->name, entry->flags, 1 << entry->log);
10900 return 1;
10901 }
10902
10903 void
iris6_asm_file_end(stream)10904 iris6_asm_file_end (stream)
10905 FILE *stream;
10906 {
10907 /* Emit section directives with the proper alignment at the top of the
10908 real output file. */
10909 asm_out_file = iris_orig_asm_out_file;
10910 htab_traverse (iris_section_align_htab, iris6_section_align_1, NULL);
10911
10912 /* Copy the data emitted to the temp file to the real output file. */
10913 copy_file_data (asm_out_file, stream);
10914
10915 mips_asm_file_end (stream);
10916 }
10917 #endif /* TARGET_IRIX6 */
10918
10919 #include "gt-mips.h"
10920