1 /* $NetBSD: nouveau_nvkm_engine_disp_dp.c,v 1.4 2021/12/19 11:34:45 riastradh Exp $ */
2
3 /*
4 * Copyright 2014 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Ben Skeggs
25 */
26 #include <sys/cdefs.h>
27 __KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_engine_disp_dp.c,v 1.4 2021/12/19 11:34:45 riastradh Exp $");
28
29 #include "dp.h"
30 #include "conn.h"
31 #include "head.h"
32 #include "ior.h"
33
34 #include <subdev/bios.h>
35 #include <subdev/bios/init.h>
36 #include <subdev/gpio.h>
37 #include <subdev/i2c.h>
38
39 #include <nvif/event.h>
40
41 #include <linux/nbsd-namespace.h>
42
43 struct lt_state {
44 struct nvkm_dp *dp;
45 u8 stat[6];
46 u8 conf[4];
47 bool pc2;
48 u8 pc2stat;
49 u8 pc2conf[2];
50 };
51
52 static int
nvkm_dp_train_sense(struct lt_state * lt,bool pc,u32 delay)53 nvkm_dp_train_sense(struct lt_state *lt, bool pc, u32 delay)
54 {
55 struct nvkm_dp *dp = lt->dp;
56 int ret;
57
58 if (dp->dpcd[DPCD_RC0E_AUX_RD_INTERVAL])
59 mdelay(dp->dpcd[DPCD_RC0E_AUX_RD_INTERVAL] * 4);
60 else
61 udelay(delay);
62
63 ret = nvkm_rdaux(dp->aux, DPCD_LS02, lt->stat, 6);
64 if (ret)
65 return ret;
66
67 if (pc) {
68 ret = nvkm_rdaux(dp->aux, DPCD_LS0C, <->pc2stat, 1);
69 if (ret)
70 lt->pc2stat = 0x00;
71 OUTP_TRACE(&dp->outp, "status %6ph pc2 %02x",
72 lt->stat, lt->pc2stat);
73 } else {
74 OUTP_TRACE(&dp->outp, "status %6ph", lt->stat);
75 }
76
77 return 0;
78 }
79
80 static int
nvkm_dp_train_drive(struct lt_state * lt,bool pc)81 nvkm_dp_train_drive(struct lt_state *lt, bool pc)
82 {
83 struct nvkm_dp *dp = lt->dp;
84 struct nvkm_ior *ior = dp->outp.ior;
85 struct nvkm_bios *bios = ior->disp->engine.subdev.device->bios;
86 struct nvbios_dpout info;
87 struct nvbios_dpcfg ocfg;
88 u8 ver, hdr, cnt, len;
89 u32 data;
90 int ret, i;
91
92 for (i = 0; i < ior->dp.nr; i++) {
93 u8 lane = (lt->stat[4 + (i >> 1)] >> ((i & 1) * 4)) & 0xf;
94 u8 lpc2 = (lt->pc2stat >> (i * 2)) & 0x3;
95 u8 lpre = (lane & 0x0c) >> 2;
96 u8 lvsw = (lane & 0x03) >> 0;
97 u8 hivs = 3 - lpre;
98 u8 hipe = 3;
99 u8 hipc = 3;
100
101 if (lpc2 >= hipc)
102 lpc2 = hipc | DPCD_LC0F_LANE0_MAX_POST_CURSOR2_REACHED;
103 if (lpre >= hipe) {
104 lpre = hipe | DPCD_LC03_MAX_SWING_REACHED; /* yes. */
105 lvsw = hivs = 3 - (lpre & 3);
106 } else
107 if (lvsw >= hivs) {
108 lvsw = hivs | DPCD_LC03_MAX_SWING_REACHED;
109 }
110
111 lt->conf[i] = (lpre << 3) | lvsw;
112 lt->pc2conf[i >> 1] |= lpc2 << ((i & 1) * 4);
113
114 OUTP_TRACE(&dp->outp, "config lane %d %02x %02x",
115 i, lt->conf[i], lpc2);
116
117 data = nvbios_dpout_match(bios, dp->outp.info.hasht,
118 dp->outp.info.hashm,
119 &ver, &hdr, &cnt, &len, &info);
120 if (!data)
121 continue;
122
123 data = nvbios_dpcfg_match(bios, data, lpc2 & 3, lvsw & 3,
124 lpre & 3, &ver, &hdr, &cnt, &len,
125 &ocfg);
126 if (!data)
127 continue;
128
129 ior->func->dp.drive(ior, i, ocfg.pc, ocfg.dc,
130 ocfg.pe, ocfg.tx_pu);
131 }
132
133 ret = nvkm_wraux(dp->aux, DPCD_LC03(0), lt->conf, 4);
134 if (ret)
135 return ret;
136
137 if (pc) {
138 ret = nvkm_wraux(dp->aux, DPCD_LC0F, lt->pc2conf, 2);
139 if (ret)
140 return ret;
141 }
142
143 return 0;
144 }
145
146 static void
nvkm_dp_train_pattern(struct lt_state * lt,u8 pattern)147 nvkm_dp_train_pattern(struct lt_state *lt, u8 pattern)
148 {
149 struct nvkm_dp *dp = lt->dp;
150 u8 sink_tp;
151
152 OUTP_TRACE(&dp->outp, "training pattern %d", pattern);
153 dp->outp.ior->func->dp.pattern(dp->outp.ior, pattern);
154
155 nvkm_rdaux(dp->aux, DPCD_LC02, &sink_tp, 1);
156 sink_tp &= ~DPCD_LC02_TRAINING_PATTERN_SET;
157 sink_tp |= pattern;
158 nvkm_wraux(dp->aux, DPCD_LC02, &sink_tp, 1);
159 }
160
161 static int
nvkm_dp_train_eq(struct lt_state * lt)162 nvkm_dp_train_eq(struct lt_state *lt)
163 {
164 bool eq_done = false, cr_done = true;
165 int tries = 0, i;
166
167 if (lt->dp->dpcd[DPCD_RC02] & DPCD_RC02_TPS3_SUPPORTED)
168 nvkm_dp_train_pattern(lt, 3);
169 else
170 nvkm_dp_train_pattern(lt, 2);
171
172 do {
173 if ((tries &&
174 nvkm_dp_train_drive(lt, lt->pc2)) ||
175 nvkm_dp_train_sense(lt, lt->pc2, 400))
176 break;
177
178 eq_done = !!(lt->stat[2] & DPCD_LS04_INTERLANE_ALIGN_DONE);
179 for (i = 0; i < lt->dp->outp.ior->dp.nr && eq_done; i++) {
180 u8 lane = (lt->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
181 if (!(lane & DPCD_LS02_LANE0_CR_DONE))
182 cr_done = false;
183 if (!(lane & DPCD_LS02_LANE0_CHANNEL_EQ_DONE) ||
184 !(lane & DPCD_LS02_LANE0_SYMBOL_LOCKED))
185 eq_done = false;
186 }
187 } while (!eq_done && cr_done && ++tries <= 5);
188
189 return eq_done ? 0 : -1;
190 }
191
192 static int
nvkm_dp_train_cr(struct lt_state * lt)193 nvkm_dp_train_cr(struct lt_state *lt)
194 {
195 bool cr_done = false, abort = false;
196 int voltage = lt->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET;
197 int tries = 0, i;
198
199 nvkm_dp_train_pattern(lt, 1);
200
201 do {
202 if (nvkm_dp_train_drive(lt, false) ||
203 nvkm_dp_train_sense(lt, false, 100))
204 break;
205
206 cr_done = true;
207 for (i = 0; i < lt->dp->outp.ior->dp.nr; i++) {
208 u8 lane = (lt->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
209 if (!(lane & DPCD_LS02_LANE0_CR_DONE)) {
210 cr_done = false;
211 if (lt->conf[i] & DPCD_LC03_MAX_SWING_REACHED)
212 abort = true;
213 break;
214 }
215 }
216
217 if ((lt->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET) != voltage) {
218 voltage = lt->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET;
219 tries = 0;
220 }
221 } while (!cr_done && !abort && ++tries < 5);
222
223 return cr_done ? 0 : -1;
224 }
225
226 static int
nvkm_dp_train_links(struct nvkm_dp * dp)227 nvkm_dp_train_links(struct nvkm_dp *dp)
228 {
229 struct nvkm_ior *ior = dp->outp.ior;
230 struct nvkm_disp *disp = dp->outp.disp;
231 struct nvkm_subdev *subdev = &disp->engine.subdev;
232 struct nvkm_bios *bios = subdev->device->bios;
233 struct lt_state lt = {
234 .dp = dp,
235 };
236 u32 lnkcmp;
237 u8 sink[2];
238 int ret;
239
240 OUTP_DBG(&dp->outp, "training %d x %d MB/s",
241 ior->dp.nr, ior->dp.bw * 27);
242
243 /* Intersect misc. capabilities of the OR and sink. */
244 if (disp->engine.subdev.device->chipset < 0xd0)
245 dp->dpcd[DPCD_RC02] &= ~DPCD_RC02_TPS3_SUPPORTED;
246 lt.pc2 = dp->dpcd[DPCD_RC02] & DPCD_RC02_TPS3_SUPPORTED;
247
248 /* Set desired link configuration on the source. */
249 if ((lnkcmp = lt.dp->info.lnkcmp)) {
250 if (dp->version < 0x30) {
251 while ((ior->dp.bw * 2700) < nvbios_rd16(bios, lnkcmp))
252 lnkcmp += 4;
253 lnkcmp = nvbios_rd16(bios, lnkcmp + 2);
254 } else {
255 while (ior->dp.bw < nvbios_rd08(bios, lnkcmp))
256 lnkcmp += 3;
257 lnkcmp = nvbios_rd16(bios, lnkcmp + 1);
258 }
259
260 nvbios_init(subdev, lnkcmp,
261 init.outp = &dp->outp.info;
262 init.or = ior->id;
263 init.link = ior->asy.link;
264 );
265 }
266
267 ret = ior->func->dp.links(ior, dp->aux);
268 if (ret) {
269 if (ret < 0) {
270 OUTP_ERR(&dp->outp, "train failed with %d", ret);
271 return ret;
272 }
273 return 0;
274 }
275
276 ior->func->dp.power(ior, ior->dp.nr);
277
278 /* Set desired link configuration on the sink. */
279 sink[0] = ior->dp.bw;
280 sink[1] = ior->dp.nr;
281 if (ior->dp.ef)
282 sink[1] |= DPCD_LC01_ENHANCED_FRAME_EN;
283
284 ret = nvkm_wraux(dp->aux, DPCD_LC00_LINK_BW_SET, sink, 2);
285 if (ret)
286 return ret;
287
288 /* Attempt to train the link in this configuration. */
289 memset(lt.stat, 0x00, sizeof(lt.stat));
290 ret = nvkm_dp_train_cr(<);
291 if (ret == 0)
292 ret = nvkm_dp_train_eq(<);
293 nvkm_dp_train_pattern(<, 0);
294 return ret;
295 }
296
297 static void
nvkm_dp_train_fini(struct nvkm_dp * dp)298 nvkm_dp_train_fini(struct nvkm_dp *dp)
299 {
300 /* Execute AfterLinkTraining script from DP Info table. */
301 nvbios_init(&dp->outp.disp->engine.subdev, dp->info.script[1],
302 init.outp = &dp->outp.info;
303 init.or = dp->outp.ior->id;
304 init.link = dp->outp.ior->asy.link;
305 );
306 }
307
308 static void
nvkm_dp_train_init(struct nvkm_dp * dp)309 nvkm_dp_train_init(struct nvkm_dp *dp)
310 {
311 /* Execute EnableSpread/DisableSpread script from DP Info table. */
312 if (dp->dpcd[DPCD_RC03] & DPCD_RC03_MAX_DOWNSPREAD) {
313 nvbios_init(&dp->outp.disp->engine.subdev, dp->info.script[2],
314 init.outp = &dp->outp.info;
315 init.or = dp->outp.ior->id;
316 init.link = dp->outp.ior->asy.link;
317 );
318 } else {
319 nvbios_init(&dp->outp.disp->engine.subdev, dp->info.script[3],
320 init.outp = &dp->outp.info;
321 init.or = dp->outp.ior->id;
322 init.link = dp->outp.ior->asy.link;
323 );
324 }
325
326 /* Execute BeforeLinkTraining script from DP Info table. */
327 nvbios_init(&dp->outp.disp->engine.subdev, dp->info.script[0],
328 init.outp = &dp->outp.info;
329 init.or = dp->outp.ior->id;
330 init.link = dp->outp.ior->asy.link;
331 );
332 }
333
334 static const struct dp_rates {
335 u32 rate;
336 u8 bw;
337 u8 nr;
338 } nvkm_dp_rates[] = {
339 { 2160000, 0x14, 4 },
340 { 1080000, 0x0a, 4 },
341 { 1080000, 0x14, 2 },
342 { 648000, 0x06, 4 },
343 { 540000, 0x0a, 2 },
344 { 540000, 0x14, 1 },
345 { 324000, 0x06, 2 },
346 { 270000, 0x0a, 1 },
347 { 162000, 0x06, 1 },
348 {}
349 };
350
351 static int
nvkm_dp_train(struct nvkm_dp * dp,u32 dataKBps)352 nvkm_dp_train(struct nvkm_dp *dp, u32 dataKBps)
353 {
354 struct nvkm_ior *ior = dp->outp.ior;
355 const u8 sink_nr = dp->dpcd[DPCD_RC02] & DPCD_RC02_MAX_LANE_COUNT;
356 const u8 sink_bw = dp->dpcd[DPCD_RC01_MAX_LINK_RATE];
357 const u8 outp_nr = dp->outp.info.dpconf.link_nr;
358 const u8 outp_bw = dp->outp.info.dpconf.link_bw;
359 const struct dp_rates *failsafe = NULL, *cfg;
360 int ret = -EINVAL;
361 u8 pwr;
362
363 /* Find the lowest configuration of the OR that can support
364 * the required link rate.
365 *
366 * We will refuse to program the OR to lower rates, even if
367 * link training fails at higher rates (or even if the sink
368 * can't support the rate at all, though the DD is supposed
369 * to prevent such situations from happening).
370 *
371 * Attempting to do so can cause the entire display to hang,
372 * and it's better to have a failed modeset than that.
373 */
374 for (cfg = nvkm_dp_rates; cfg->rate; cfg++) {
375 if (cfg->nr <= outp_nr && cfg->bw <= outp_bw) {
376 /* Try to respect sink limits too when selecting
377 * lowest link configuration.
378 */
379 if (!failsafe ||
380 (cfg->nr <= sink_nr && cfg->bw <= sink_bw))
381 failsafe = cfg;
382 }
383
384 if (failsafe && cfg[1].rate < dataKBps)
385 break;
386 }
387
388 if (WARN_ON(!failsafe))
389 return ret;
390
391 /* Ensure sink is not in a low-power state. */
392 if (!nvkm_rdaux(dp->aux, DPCD_SC00, &pwr, 1)) {
393 if ((pwr & DPCD_SC00_SET_POWER) != DPCD_SC00_SET_POWER_D0) {
394 pwr &= ~DPCD_SC00_SET_POWER;
395 pwr |= DPCD_SC00_SET_POWER_D0;
396 nvkm_wraux(dp->aux, DPCD_SC00, &pwr, 1);
397 }
398 }
399
400 /* Link training. */
401 OUTP_DBG(&dp->outp, "training (min: %d x %d MB/s)",
402 failsafe->nr, failsafe->bw * 27);
403 nvkm_dp_train_init(dp);
404 for (cfg = nvkm_dp_rates; ret < 0 && cfg <= failsafe; cfg++) {
405 /* Skip configurations not supported by both OR and sink. */
406 if ((cfg->nr > outp_nr || cfg->bw > outp_bw ||
407 cfg->nr > sink_nr || cfg->bw > sink_bw)) {
408 if (cfg != failsafe)
409 continue;
410 OUTP_ERR(&dp->outp, "link rate unsupported by sink");
411 }
412 ior->dp.mst = dp->lt.mst;
413 ior->dp.ef = dp->dpcd[DPCD_RC02] & DPCD_RC02_ENHANCED_FRAME_CAP;
414 ior->dp.bw = cfg->bw;
415 ior->dp.nr = cfg->nr;
416
417 /* Program selected link configuration. */
418 ret = nvkm_dp_train_links(dp);
419 }
420 nvkm_dp_train_fini(dp);
421 if (ret < 0)
422 OUTP_ERR(&dp->outp, "training failed");
423 else
424 OUTP_DBG(&dp->outp, "training done");
425 atomic_set(&dp->lt.done, 1);
426 return ret;
427 }
428
429 static void
nvkm_dp_disable(struct nvkm_outp * outp,struct nvkm_ior * ior)430 nvkm_dp_disable(struct nvkm_outp *outp, struct nvkm_ior *ior)
431 {
432 struct nvkm_dp *dp = nvkm_dp(outp);
433
434 /* Execute DisableLT script from DP Info Table. */
435 nvbios_init(&ior->disp->engine.subdev, dp->info.script[4],
436 init.outp = &dp->outp.info;
437 init.or = ior->id;
438 init.link = ior->arm.link;
439 );
440 }
441
442 static void
nvkm_dp_release(struct nvkm_outp * outp)443 nvkm_dp_release(struct nvkm_outp *outp)
444 {
445 struct nvkm_dp *dp = nvkm_dp(outp);
446
447 /* Prevent link from being retrained if sink sends an IRQ. */
448 atomic_set(&dp->lt.done, 0);
449 dp->outp.ior->dp.nr = 0;
450 }
451
452 static int
nvkm_dp_acquire(struct nvkm_outp * outp)453 nvkm_dp_acquire(struct nvkm_outp *outp)
454 {
455 struct nvkm_dp *dp = nvkm_dp(outp);
456 struct nvkm_ior *ior = dp->outp.ior;
457 struct nvkm_head *head;
458 bool retrain = true;
459 u32 datakbps = 0;
460 u32 dataKBps;
461 u32 linkKBps;
462 u8 stat[3];
463 int ret, i;
464
465 mutex_lock(&dp->mutex);
466
467 /* Check that link configuration meets current requirements. */
468 list_for_each_entry(head, &outp->disp->head, head) {
469 if (ior->asy.head & (1 << head->id)) {
470 u32 khz = (head->asy.hz >> ior->asy.rgdiv) / 1000;
471 datakbps += khz * head->asy.or.depth;
472 }
473 }
474
475 linkKBps = ior->dp.bw * 27000 * ior->dp.nr;
476 dataKBps = DIV_ROUND_UP(datakbps, 8);
477 OUTP_DBG(&dp->outp, "data %d KB/s link %d KB/s mst %d->%d",
478 dataKBps, linkKBps, ior->dp.mst, dp->lt.mst);
479 if (linkKBps < dataKBps || ior->dp.mst != dp->lt.mst) {
480 OUTP_DBG(&dp->outp, "link requirements changed");
481 goto done;
482 }
483
484 /* Check that link is still trained. */
485 ret = nvkm_rdaux(dp->aux, DPCD_LS02, stat, 3);
486 if (ret) {
487 OUTP_DBG(&dp->outp,
488 "failed to read link status, assuming no sink");
489 goto done;
490 }
491
492 if (stat[2] & DPCD_LS04_INTERLANE_ALIGN_DONE) {
493 for (i = 0; i < ior->dp.nr; i++) {
494 u8 lane = (stat[i >> 1] >> ((i & 1) * 4)) & 0x0f;
495 if (!(lane & DPCD_LS02_LANE0_CR_DONE) ||
496 !(lane & DPCD_LS02_LANE0_CHANNEL_EQ_DONE) ||
497 !(lane & DPCD_LS02_LANE0_SYMBOL_LOCKED)) {
498 OUTP_DBG(&dp->outp,
499 "lane %d not equalised", lane);
500 goto done;
501 }
502 }
503 retrain = false;
504 } else {
505 OUTP_DBG(&dp->outp, "no inter-lane alignment");
506 }
507
508 done:
509 if (retrain || !atomic_read(&dp->lt.done))
510 ret = nvkm_dp_train(dp, dataKBps);
511 mutex_unlock(&dp->mutex);
512 return ret;
513 }
514
515 static bool
nvkm_dp_enable(struct nvkm_dp * dp,bool enable)516 nvkm_dp_enable(struct nvkm_dp *dp, bool enable)
517 {
518 struct nvkm_i2c_aux *aux = dp->aux;
519
520 if (enable) {
521 if (!dp->present) {
522 OUTP_DBG(&dp->outp, "aux power -> always");
523 nvkm_i2c_aux_monitor(aux, true);
524 dp->present = true;
525 }
526
527 if (!nvkm_rdaux(aux, DPCD_RC00_DPCD_REV, dp->dpcd,
528 sizeof(dp->dpcd)))
529 return true;
530 }
531
532 if (dp->present) {
533 OUTP_DBG(&dp->outp, "aux power -> demand");
534 nvkm_i2c_aux_monitor(aux, false);
535 dp->present = false;
536 }
537
538 atomic_set(&dp->lt.done, 0);
539 return false;
540 }
541
542 static int
nvkm_dp_hpd(struct nvkm_notify * notify)543 nvkm_dp_hpd(struct nvkm_notify *notify)
544 {
545 const struct nvkm_i2c_ntfy_rep *line = notify->data;
546 struct nvkm_dp *dp = container_of(notify, typeof(*dp), hpd);
547 struct nvkm_conn *conn = dp->outp.conn;
548 struct nvkm_disp *disp = dp->outp.disp;
549 struct nvif_notify_conn_rep_v0 rep = {};
550
551 OUTP_DBG(&dp->outp, "HPD: %d", line->mask);
552 if (line->mask & NVKM_I2C_IRQ) {
553 if (atomic_read(&dp->lt.done))
554 dp->outp.func->acquire(&dp->outp);
555 rep.mask |= NVIF_NOTIFY_CONN_V0_IRQ;
556 } else {
557 nvkm_dp_enable(dp, true);
558 }
559
560 if (line->mask & NVKM_I2C_UNPLUG)
561 rep.mask |= NVIF_NOTIFY_CONN_V0_UNPLUG;
562 if (line->mask & NVKM_I2C_PLUG)
563 rep.mask |= NVIF_NOTIFY_CONN_V0_PLUG;
564
565 nvkm_event_send(&disp->hpd, rep.mask, conn->index, &rep, sizeof(rep));
566 return NVKM_NOTIFY_KEEP;
567 }
568
569 static void
nvkm_dp_fini(struct nvkm_outp * outp)570 nvkm_dp_fini(struct nvkm_outp *outp)
571 {
572 struct nvkm_dp *dp = nvkm_dp(outp);
573 nvkm_notify_put(&dp->hpd);
574 nvkm_dp_enable(dp, false);
575 }
576
577 static void
nvkm_dp_init(struct nvkm_outp * outp)578 nvkm_dp_init(struct nvkm_outp *outp)
579 {
580 struct nvkm_gpio *gpio = outp->disp->engine.subdev.device->gpio;
581 struct nvkm_dp *dp = nvkm_dp(outp);
582
583 nvkm_notify_put(&dp->outp.conn->hpd);
584
585 /* eDP panels need powering on by us (if the VBIOS doesn't default it
586 * to on) before doing any AUX channel transactions. LVDS panel power
587 * is handled by the SOR itself, and not required for LVDS DDC.
588 */
589 if (dp->outp.conn->info.type == DCB_CONNECTOR_eDP) {
590 int power = nvkm_gpio_get(gpio, 0, DCB_GPIO_PANEL_POWER, 0xff);
591 if (power == 0)
592 nvkm_gpio_set(gpio, 0, DCB_GPIO_PANEL_POWER, 0xff, 1);
593
594 /* We delay here unconditionally, even if already powered,
595 * because some laptop panels having a significant resume
596 * delay before the panel begins responding.
597 *
598 * This is likely a bit of a hack, but no better idea for
599 * handling this at the moment.
600 */
601 msleep(300);
602
603 /* If the eDP panel can't be detected, we need to restore
604 * the panel power GPIO to avoid breaking another output.
605 */
606 if (!nvkm_dp_enable(dp, true) && power == 0)
607 nvkm_gpio_set(gpio, 0, DCB_GPIO_PANEL_POWER, 0xff, 0);
608 } else {
609 nvkm_dp_enable(dp, true);
610 }
611
612 nvkm_notify_get(&dp->hpd);
613 }
614
615 static void *
nvkm_dp_dtor(struct nvkm_outp * outp)616 nvkm_dp_dtor(struct nvkm_outp *outp)
617 {
618 struct nvkm_dp *dp = nvkm_dp(outp);
619 nvkm_notify_fini(&dp->hpd);
620 mutex_destroy(&dp->mutex);
621 return dp;
622 }
623
624 static const struct nvkm_outp_func
625 nvkm_dp_func = {
626 .dtor = nvkm_dp_dtor,
627 .init = nvkm_dp_init,
628 .fini = nvkm_dp_fini,
629 .acquire = nvkm_dp_acquire,
630 .release = nvkm_dp_release,
631 .disable = nvkm_dp_disable,
632 };
633
634 static int
nvkm_dp_ctor(struct nvkm_disp * disp,int index,struct dcb_output * dcbE,struct nvkm_i2c_aux * aux,struct nvkm_dp * dp)635 nvkm_dp_ctor(struct nvkm_disp *disp, int index, struct dcb_output *dcbE,
636 struct nvkm_i2c_aux *aux, struct nvkm_dp *dp)
637 {
638 struct nvkm_device *device = disp->engine.subdev.device;
639 struct nvkm_bios *bios = device->bios;
640 struct nvkm_i2c *i2c = device->i2c;
641 u8 hdr, cnt, len;
642 u32 data;
643 int ret;
644
645 ret = nvkm_outp_ctor(&nvkm_dp_func, disp, index, dcbE, &dp->outp);
646 if (ret)
647 return ret;
648
649 dp->aux = aux;
650 if (!dp->aux) {
651 OUTP_ERR(&dp->outp, "no aux");
652 return -EINVAL;
653 }
654
655 /* bios data is not optional */
656 data = nvbios_dpout_match(bios, dp->outp.info.hasht,
657 dp->outp.info.hashm, &dp->version,
658 &hdr, &cnt, &len, &dp->info);
659 if (!data) {
660 OUTP_ERR(&dp->outp, "no bios dp data");
661 return -EINVAL;
662 }
663
664 OUTP_DBG(&dp->outp, "bios dp %02x %02x %02x %02x",
665 dp->version, hdr, cnt, len);
666
667 /* hotplug detect, replaces gpio-based mechanism with aux events */
668 ret = nvkm_notify_init(NULL, &i2c->event, nvkm_dp_hpd, true,
669 &(struct nvkm_i2c_ntfy_req) {
670 .mask = NVKM_I2C_PLUG | NVKM_I2C_UNPLUG |
671 NVKM_I2C_IRQ,
672 .port = dp->aux->id,
673 },
674 sizeof(struct nvkm_i2c_ntfy_req),
675 sizeof(struct nvkm_i2c_ntfy_rep),
676 &dp->hpd);
677 if (ret) {
678 OUTP_ERR(&dp->outp, "error monitoring aux hpd: %d", ret);
679 return ret;
680 }
681
682 mutex_init(&dp->mutex);
683 atomic_set(&dp->lt.done, 0);
684 return 0;
685 }
686
687 int
nvkm_dp_new(struct nvkm_disp * disp,int index,struct dcb_output * dcbE,struct nvkm_outp ** poutp)688 nvkm_dp_new(struct nvkm_disp *disp, int index, struct dcb_output *dcbE,
689 struct nvkm_outp **poutp)
690 {
691 struct nvkm_i2c *i2c = disp->engine.subdev.device->i2c;
692 struct nvkm_i2c_aux *aux;
693 struct nvkm_dp *dp;
694
695 if (dcbE->location == 0)
696 aux = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_CCB(dcbE->i2c_index));
697 else
698 aux = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbE->extdev));
699
700 if (!(dp = kzalloc(sizeof(*dp), GFP_KERNEL)))
701 return -ENOMEM;
702 *poutp = &dp->outp;
703
704 return nvkm_dp_ctor(disp, index, dcbE, aux, dp);
705 }
706