1 /* $NetBSD: imx6sx_clk.c,v 1.4 2024/09/01 07:55:27 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2019 Genetec Corporation. All rights reserved. 5 * Written by Hashimoto Kenichi for Genetec Corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: imx6sx_clk.c,v 1.4 2024/09/01 07:55:27 skrll Exp $"); 31 32 #include "opt_fdt.h" 33 34 #include <sys/types.h> 35 #include <sys/time.h> 36 #include <sys/bus.h> 37 #include <sys/device.h> 38 #include <sys/sysctl.h> 39 #include <sys/cpufreq.h> 40 #include <sys/kmem.h> 41 #include <sys/param.h> 42 43 #include <arm/nxp/imx6_ccmreg.h> 44 #include <arm/nxp/imx6_ccmvar.h> 45 46 #include <dev/clk/clk_backend.h> 47 #include <dev/fdt/fdtvar.h> 48 49 /* Clock IDs - should match dt-bindings/clock/imx6sx-clock.h */ 50 51 #define IMX6SXCLK_DUMMY 0 52 #define IMX6SXCLK_CKIL 1 53 #define IMX6SXCLK_CKIH 2 54 #define IMX6SXCLK_OSC 3 55 #define IMX6SXCLK_PLL1_SYS 4 56 #define IMX6SXCLK_PLL2_BUS 5 57 #define IMX6SXCLK_PLL3_USB_OTG 6 58 #define IMX6SXCLK_PLL4_AUDIO 7 59 #define IMX6SXCLK_PLL5_VIDEO 8 60 #define IMX6SXCLK_PLL6_ENET 9 61 #define IMX6SXCLK_PLL7_USB_HOST 10 62 #define IMX6SXCLK_USBPHY1 11 63 #define IMX6SXCLK_USBPHY2 12 64 #define IMX6SXCLK_USBPHY1_GATE 13 65 #define IMX6SXCLK_USBPHY2_GATE 14 66 #define IMX6SXCLK_PCIE_REF 15 67 #define IMX6SXCLK_PCIE_REF_125M 16 68 #define IMX6SXCLK_ENET_REF 17 69 #define IMX6SXCLK_PLL2_PFD0 18 70 #define IMX6SXCLK_PLL2_PFD1 19 71 #define IMX6SXCLK_PLL2_PFD2 20 72 #define IMX6SXCLK_PLL2_PFD3 21 73 #define IMX6SXCLK_PLL3_PFD0 22 74 #define IMX6SXCLK_PLL3_PFD1 23 75 #define IMX6SXCLK_PLL3_PFD2 24 76 #define IMX6SXCLK_PLL3_PFD3 25 77 #define IMX6SXCLK_PLL2_198M 26 78 #define IMX6SXCLK_PLL3_120M 27 79 #define IMX6SXCLK_PLL3_80M 28 80 #define IMX6SXCLK_PLL3_60M 29 81 #define IMX6SXCLK_TWD 30 82 #define IMX6SXCLK_PLL4_POST_DIV 31 83 #define IMX6SXCLK_PLL4_AUDIO_DIV 32 84 #define IMX6SXCLK_PLL5_POST_DIV 33 85 #define IMX6SXCLK_PLL5_VIDEO_DIV 34 86 #define IMX6SXCLK_STEP 35 87 #define IMX6SXCLK_PLL1_SW 36 88 #define IMX6SXCLK_OCRAM_SEL 37 89 #define IMX6SXCLK_PERIPH_PRE 38 90 #define IMX6SXCLK_PERIPH2_PRE 39 91 #define IMX6SXCLK_PERIPH_CLK2_SEL 40 92 #define IMX6SXCLK_PERIPH2_CLK2_SEL 41 93 #define IMX6SXCLK_PCIE_AXI_SEL 42 94 #define IMX6SXCLK_GPU_AXI_SEL 43 95 #define IMX6SXCLK_GPU_CORE_SEL 44 96 #define IMX6SXCLK_EIM_SLOW_SEL 45 97 #define IMX6SXCLK_USDHC1_SEL 46 98 #define IMX6SXCLK_USDHC2_SEL 47 99 #define IMX6SXCLK_USDHC3_SEL 48 100 #define IMX6SXCLK_USDHC4_SEL 49 101 #define IMX6SXCLK_SSI1_SEL 50 102 #define IMX6SXCLK_SSI2_SEL 51 103 #define IMX6SXCLK_SSI3_SEL 52 104 #define IMX6SXCLK_QSPI1_SEL 53 105 #define IMX6SXCLK_PERCLK_SEL 54 106 #define IMX6SXCLK_VID_SEL 55 107 #define IMX6SXCLK_ESAI_SEL 56 108 #define IMX6SXCLK_LDB_DI0_DIV_SEL 57 109 #define IMX6SXCLK_LDB_DI1_DIV_SEL 58 110 #define IMX6SXCLK_CAN_SEL 59 111 #define IMX6SXCLK_UART_SEL 60 112 #define IMX6SXCLK_QSPI2_SEL 61 113 #define IMX6SXCLK_LDB_DI1_SEL 62 114 #define IMX6SXCLK_LDB_DI0_SEL 63 115 #define IMX6SXCLK_SPDIF_SEL 64 116 #define IMX6SXCLK_AUDIO_SEL 65 117 #define IMX6SXCLK_ENET_PRE_SEL 66 118 #define IMX6SXCLK_ENET_SEL 67 119 #define IMX6SXCLK_M4_PRE_SEL 68 120 #define IMX6SXCLK_M4_SEL 69 121 #define IMX6SXCLK_ECSPI_SEL 70 122 #define IMX6SXCLK_LCDIF1_PRE_SEL 71 123 #define IMX6SXCLK_LCDIF2_PRE_SEL 72 124 #define IMX6SXCLK_LCDIF1_SEL 73 125 #define IMX6SXCLK_LCDIF2_SEL 74 126 #define IMX6SXCLK_DISPLAY_SEL 75 127 #define IMX6SXCLK_CSI_SEL 76 128 #define IMX6SXCLK_CKO1_SEL 77 129 #define IMX6SXCLK_CKO2_SEL 78 130 #define IMX6SXCLK_CKO 79 131 #define IMX6SXCLK_PERIPH_CLK2 80 132 #define IMX6SXCLK_PERIPH2_CLK2 81 133 #define IMX6SXCLK_IPG 82 134 #define IMX6SXCLK_GPU_CORE_PODF 83 135 #define IMX6SXCLK_GPU_AXI_PODF 84 136 #define IMX6SXCLK_LCDIF1_PODF 85 137 #define IMX6SXCLK_QSPI1_PODF 86 138 #define IMX6SXCLK_EIM_SLOW_PODF 87 139 #define IMX6SXCLK_LCDIF2_PODF 88 140 #define IMX6SXCLK_PERCLK 89 141 #define IMX6SXCLK_VID_PODF 90 142 #define IMX6SXCLK_CAN_PODF 91 143 #define IMX6SXCLK_USDHC1_PODF 92 144 #define IMX6SXCLK_USDHC2_PODF 93 145 #define IMX6SXCLK_USDHC3_PODF 94 146 #define IMX6SXCLK_USDHC4_PODF 95 147 #define IMX6SXCLK_UART_PODF 96 148 #define IMX6SXCLK_ESAI_PRED 97 149 #define IMX6SXCLK_ESAI_PODF 98 150 #define IMX6SXCLK_SSI3_PRED 99 151 #define IMX6SXCLK_SSI3_PODF 100 152 #define IMX6SXCLK_SSI1_PRED 101 153 #define IMX6SXCLK_SSI1_PODF 102 154 #define IMX6SXCLK_QSPI2_PRED 103 155 #define IMX6SXCLK_QSPI2_PODF 104 156 #define IMX6SXCLK_SSI2_PRED 105 157 #define IMX6SXCLK_SSI2_PODF 106 158 #define IMX6SXCLK_SPDIF_PRED 107 159 #define IMX6SXCLK_SPDIF_PODF 108 160 #define IMX6SXCLK_AUDIO_PRED 109 161 #define IMX6SXCLK_AUDIO_PODF 110 162 #define IMX6SXCLK_ENET_PODF 111 163 #define IMX6SXCLK_M4_PODF 112 164 #define IMX6SXCLK_ECSPI_PODF 113 165 #define IMX6SXCLK_LCDIF1_PRED 114 166 #define IMX6SXCLK_LCDIF2_PRED 115 167 #define IMX6SXCLK_DISPLAY_PODF 116 168 #define IMX6SXCLK_CSI_PODF 117 169 #define IMX6SXCLK_LDB_DI0_DIV_3_5 118 170 #define IMX6SXCLK_LDB_DI0_DIV_7 119 171 #define IMX6SXCLK_LDB_DI1_DIV_3_5 120 172 #define IMX6SXCLK_LDB_DI1_DIV_7 121 173 #define IMX6SXCLK_CKO1_PODF 122 174 #define IMX6SXCLK_CKO2_PODF 123 175 #define IMX6SXCLK_PERIPH 124 176 #define IMX6SXCLK_PERIPH2 125 177 #define IMX6SXCLK_OCRAM 126 178 #define IMX6SXCLK_AHB 127 179 #define IMX6SXCLK_MMDC_PODF 128 180 #define IMX6SXCLK_ARM 129 181 #define IMX6SXCLK_AIPS_TZ1 130 182 #define IMX6SXCLK_AIPS_TZ2 131 183 #define IMX6SXCLK_APBH_DMA 132 184 #define IMX6SXCLK_ASRC_GATE 133 185 #define IMX6SXCLK_CAAM_MEM 134 186 #define IMX6SXCLK_CAAM_ACLK 135 187 #define IMX6SXCLK_CAAM_IPG 136 188 #define IMX6SXCLK_CAN1_IPG 137 189 #define IMX6SXCLK_CAN1_SERIAL 138 190 #define IMX6SXCLK_CAN2_IPG 139 191 #define IMX6SXCLK_CAN2_SERIAL 140 192 #define IMX6SXCLK_CPU_DEBUG 141 193 #define IMX6SXCLK_DCIC1 142 194 #define IMX6SXCLK_DCIC2 143 195 #define IMX6SXCLK_AIPS_TZ3 144 196 #define IMX6SXCLK_ECSPI1 145 197 #define IMX6SXCLK_ECSPI2 146 198 #define IMX6SXCLK_ECSPI3 147 199 #define IMX6SXCLK_ECSPI4 148 200 #define IMX6SXCLK_ECSPI5 149 201 #define IMX6SXCLK_EPIT1 150 202 #define IMX6SXCLK_EPIT2 151 203 #define IMX6SXCLK_ESAI_EXTAL 152 204 #define IMX6SXCLK_WAKEUP 153 205 #define IMX6SXCLK_GPT_BUS 154 206 #define IMX6SXCLK_GPT_SERIAL 155 207 #define IMX6SXCLK_GPU 156 208 #define IMX6SXCLK_OCRAM_S 157 209 #define IMX6SXCLK_CANFD 158 210 #define IMX6SXCLK_CSI 159 211 #define IMX6SXCLK_I2C1 160 212 #define IMX6SXCLK_I2C2 161 213 #define IMX6SXCLK_I2C3 162 214 #define IMX6SXCLK_OCOTP 163 215 #define IMX6SXCLK_IOMUXC 164 216 #define IMX6SXCLK_IPMUX1 165 217 #define IMX6SXCLK_IPMUX2 166 218 #define IMX6SXCLK_IPMUX3 167 219 #define IMX6SXCLK_TZASC1 168 220 #define IMX6SXCLK_LCDIF_APB 169 221 #define IMX6SXCLK_PXP_AXI 170 222 #define IMX6SXCLK_M4 171 223 #define IMX6SXCLK_ENET 172 224 #define IMX6SXCLK_DISPLAY_AXI 173 225 #define IMX6SXCLK_LCDIF2_PIX 174 226 #define IMX6SXCLK_LCDIF1_PIX 175 227 #define IMX6SXCLK_LDB_DI0 176 228 #define IMX6SXCLK_QSPI1 177 229 #define IMX6SXCLK_MLB 178 230 #define IMX6SXCLK_MMDC_P0_FAST 179 231 #define IMX6SXCLK_MMDC_P0_IPG 180 232 #define IMX6SXCLK_AXI 181 233 #define IMX6SXCLK_PCIE_AXI 182 234 #define IMX6SXCLK_QSPI2 183 235 #define IMX6SXCLK_PER1_BCH 184 236 #define IMX6SXCLK_PER2_MAIN 185 237 #define IMX6SXCLK_PWM1 186 238 #define IMX6SXCLK_PWM2 187 239 #define IMX6SXCLK_PWM3 188 240 #define IMX6SXCLK_PWM4 189 241 #define IMX6SXCLK_GPMI_BCH_APB 190 242 #define IMX6SXCLK_GPMI_BCH 191 243 #define IMX6SXCLK_GPMI_IO 192 244 #define IMX6SXCLK_GPMI_APB 193 245 #define IMX6SXCLK_ROM 194 246 #define IMX6SXCLK_SDMA 195 247 #define IMX6SXCLK_SPBA 196 248 #define IMX6SXCLK_SPDIF 197 249 #define IMX6SXCLK_SSI1_IPG 198 250 #define IMX6SXCLK_SSI2_IPG 199 251 #define IMX6SXCLK_SSI3_IPG 200 252 #define IMX6SXCLK_SSI1 201 253 #define IMX6SXCLK_SSI2 202 254 #define IMX6SXCLK_SSI3 203 255 #define IMX6SXCLK_UART_IPG 204 256 #define IMX6SXCLK_UART_SERIAL 205 257 #define IMX6SXCLK_SAI1 206 258 #define IMX6SXCLK_SAI2 207 259 #define IMX6SXCLK_USBOH3 208 260 #define IMX6SXCLK_USDHC1 209 261 #define IMX6SXCLK_USDHC2 210 262 #define IMX6SXCLK_USDHC3 211 263 #define IMX6SXCLK_USDHC4 212 264 #define IMX6SXCLK_EIM_SLOW 213 265 #define IMX6SXCLK_PWM8 214 266 #define IMX6SXCLK_VADC 215 267 #define IMX6SXCLK_GIS 216 268 #define IMX6SXCLK_I2C4 217 269 #define IMX6SXCLK_PWM5 218 270 #define IMX6SXCLK_PWM6 219 271 #define IMX6SXCLK_PWM7 220 272 #define IMX6SXCLK_CKO1 221 273 #define IMX6SXCLK_CKO2 222 274 #define IMX6SXCLK_IPP_DI0 223 275 #define IMX6SXCLK_IPP_DI1 224 276 #define IMX6SXCLK_ENET_AHB 225 277 #define IMX6SXCLK_OCRAM_PODF 226 278 #define IMX6SXCLK_GPT_3M 227 279 #define IMX6SXCLK_ENET_PTP 228 280 #define IMX6SXCLK_ENET_PTP_REF 229 281 #define IMX6SXCLK_ENET2_REF 230 282 #define IMX6SXCLK_ENET2_REF_125M 231 283 #define IMX6SXCLK_AUDIO 232 284 #define IMX6SXCLK_LVDS1_SEL 233 285 #define IMX6SXCLK_LVDS1_OUT 234 286 #define IMX6SXCLK_ASRC_IPG 235 287 #define IMX6SXCLK_ASRC_MEM 236 288 #define IMX6SXCLK_SAI1_IPG 237 289 #define IMX6SXCLK_SAI2_IPG 238 290 #define IMX6SXCLK_ESAI_IPG 239 291 #define IMX6SXCLK_ESAI_MEM 240 292 #define IMX6SXCLK_LVDS1_IN 241 293 #define IMX6SXCLK_ANACLK1 242 294 #define IMX6SXCLK_PLL1_BYPASS_SRC 243 295 #define IMX6SXCLK_PLL2_BYPASS_SRC 244 296 #define IMX6SXCLK_PLL3_BYPASS_SRC 245 297 #define IMX6SXCLK_PLL4_BYPASS_SRC 246 298 #define IMX6SXCLK_PLL5_BYPASS_SRC 247 299 #define IMX6SXCLK_PLL6_BYPASS_SRC 248 300 #define IMX6SXCLK_PLL7_BYPASS_SRC 249 301 #define IMX6SXCLK_PLL1 250 302 #define IMX6SXCLK_PLL2 251 303 #define IMX6SXCLK_PLL3 252 304 #define IMX6SXCLK_PLL4 253 305 #define IMX6SXCLK_PLL5 254 306 #define IMX6SXCLK_PLL6 255 307 #define IMX6SXCLK_PLL7 256 308 #define IMX6SXCLK_PLL1_BYPASS 257 309 #define IMX6SXCLK_PLL2_BYPASS 258 310 #define IMX6SXCLK_PLL3_BYPASS 259 311 #define IMX6SXCLK_PLL4_BYPASS 260 312 #define IMX6SXCLK_PLL5_BYPASS 261 313 #define IMX6SXCLK_PLL6_BYPASS 262 314 #define IMX6SXCLK_PLL7_BYPASS 263 315 #define IMX6SXCLK_SPDIF_GCLK 264 316 #define IMX6SXCLK_LVDS2_SEL 265 317 #define IMX6SXCLK_LVDS2_OUT 266 318 #define IMX6SXCLK_LVDS2_IN 267 319 #define IMX6SXCLK_ANACLK2 268 320 #define IMX6SXCLK_MMDC_P1_IPG 269 321 #define IMX6SXCLK_END 270 322 323 /* Clock Parents Tables */ 324 static const char *step_p[] = { 325 "osc", 326 "pll2_pfd2_396m" 327 }; 328 329 static const char *pll1_sw_p[] = { 330 "pll1_sys", 331 "step" 332 }; 333 334 static const char *periph_pre_p[] = { 335 "pll2_bus", 336 "pll2_pfd2_396m", 337 "pll2_pfd0_352m", 338 "pll2_198m" 339 }; 340 341 static const char *periph2_pre_p[] = { 342 "pll2_bus", 343 "pll2_pfd2_396m", 344 "pll2_pfd0_352m", 345 "pll4_audio_div" 346 }; 347 348 static const char *periph_clk2_p[] = { 349 "pll3_usb_otg", 350 "osc", 351 "osc" 352 }; 353 354 static const char *periph2_clk2_p[] = { 355 "pll3_usb_otg", 356 "pll2_bus" 357 }; 358 359 static const char *audio_p[] = { 360 "pll4_audio_div", 361 "pll3_pfd2_508m", 362 "pll5_video_div", 363 "pll3_usb_otg" 364 }; 365 366 static const char *gpu_axi_p[] = { 367 "pll2_pfd2_396m", 368 "pll3_pfd0_720m", 369 "pll3_pfd1_540m", 370 "pll2_bus" 371 }; 372 373 static const char *gpu_core_p[] = { 374 "pll3_pfd1_540m", 375 "pll3_pfd0_720m", 376 "pll2_bus", 377 "pll2_pfd2_396m" 378 }; 379 380 static const char *ldb_di0_div_p[] = { 381 "ldb_di0_div_3_5", 382 "ldb_di0_div_7", 383 }; 384 385 static const char *ldb_di1_div_p[] = { 386 "ldb_di1_div_3_5", 387 "ldb_di1_div_7", 388 }; 389 390 static const char *ldb_di0_p[] = { 391 "pll5_video_div", 392 "pll2_pfd0_352m", 393 "pll2_pfd2_396m", 394 "pll2_pfd3_594m", 395 "pll2_pfd1_594m", 396 "pll3_pfd3_454m", 397 }; 398 399 static const char *ldb_di1_p[] = { 400 "pll3_usb_otg", 401 "pll2_pfd0_352m", 402 "pll2_pfd2_396m", 403 "pll2_bus", 404 "pll3_pfd3_454m", 405 "pll3_pfd2_508m", 406 }; 407 408 static const char *pll_bypass_src_p[] = { 409 "osc", 410 "lvds1_in", 411 "lvds2_in", 412 "dummy" 413 }; 414 415 static const char *pll1_bypass_p[] = { 416 "pll1", 417 "pll1_bypass_src" 418 }; 419 420 static const char *pll2_bypass_p[] = { 421 "pll2", 422 "pll2_bypass_src" 423 }; 424 425 static const char *pll3_bypass_p[] = { 426 "pll3", 427 "pll3_bypass_src" 428 }; 429 430 static const char *pll4_bypass_p[] = { 431 "pll4", 432 "pll4_bypass_src" 433 }; 434 435 static const char *pll5_bypass_p[] = { 436 "pll5", 437 "pll5_bypass_src" 438 }; 439 440 static const char *pll6_bypass_p[] = { 441 "pll6", 442 "pll6_bypass_src" 443 }; 444 445 static const char *pll7_bypass_p[] = { 446 "pll7", 447 "pll7_bypass_src" 448 }; 449 450 static const char *periph_p[] = { 451 "periph_pre", 452 "periph_clk2" 453 }; 454 455 static const char *periph2_p[] = { 456 "periph2_pre", 457 "periph2_clk2" 458 }; 459 460 static const char *ocram_p[] = { 461 "periph", 462 "pll2_pfd2_396m", 463 "periph", 464 "pll3_pfd1_540m", 465 }; 466 467 static const char *cko1_p[] = { 468 "dummy", 469 "dummy", 470 "dummy", 471 "dummy", 472 "vadc", 473 "ocram", 474 "qspi2", 475 "m4", 476 "enet_ahb", 477 "lcdif2_pix", 478 "lcdif1_pix", 479 "ahb", 480 "ipg", 481 "perclk", 482 "ckil", 483 "pll4_audio_div", 484 }; 485 486 static const char *cko2_p[] = { 487 "dummy", 488 "mmdc_p0_fast", 489 "usdhc4", 490 "usdhc1", 491 "dummy", 492 "wrck", 493 "ecspi_root", 494 "dummy", 495 "usdhc3", 496 "pcie", 497 "arm", 498 "csi_core", 499 "display_axi", 500 "dummy", 501 "osc", 502 "dummy", 503 "dummy", 504 "usdhc2", 505 "ssi1", 506 "ssi2", 507 "ssi3", 508 "gpu_axi_podf", 509 "dummy", 510 "can_podf", 511 "lvds1_out", 512 "qspi1", 513 "esai_extal", 514 "eim_slow", 515 "uart_serial", 516 "spdif", 517 "audio", 518 "dummy", 519 }; 520 521 static const char *cko_p[] = { 522 "cko1", 523 "cko2" 524 }; 525 526 static const char *pcie_axi_p[] = { 527 "ocram", 528 "ahb" 529 }; 530 531 static const char *ssi_p[] = { 532 "pll3_pfd2_508m", 533 "pll5_video_div", 534 "pll4_audio_div" 535 }; 536 537 static const char *qspi1_p[] = { 538 "pll3_usb_otg", 539 "pll2_pfd0_352m", 540 "pll2_pfd2_396m", 541 "pll2_bus", 542 "pll3_pfd3_454m", 543 "pll3_pfd2_508m", 544 }; 545 546 static const char *perclk_p[] = { 547 "ipg", 548 "osc" 549 }; 550 551 static const char *usdhc_p[] = { 552 "pll2_pfd2_396m", 553 "pll2_pfd0_352m" 554 }; 555 556 static const char *vid_p[] = { 557 "pll3_pfd1_540m", 558 "pll3_usb_otg", 559 "pll3_pfd3_454m", 560 "pll4_audio_div", 561 "pll5_video_div", 562 }; 563 564 static const char *can_p[] = { 565 "pll3_60m", 566 "osc", 567 "pll3_80m", 568 "dummy", 569 }; 570 571 static const char *uart_p[] = { 572 "pll3_80m", 573 "osc", 574 }; 575 576 static const char *qspi2_p[] = { 577 "pll2_pfd0_352m", 578 "pll2_bus", 579 "pll3_usb_otg", 580 "pll2_pfd2_396m", 581 "pll3_pfd3_454m", 582 "dummy", 583 "dummy", 584 "dummy", 585 }; 586 587 static const char *enet_pre_p[] = { 588 "pll2_bus", 589 "pll3_usb_otg", 590 "pll5_video_div", 591 "pll2_pfd0_352m", 592 "pll2_pfd2_396m", 593 "pll3_pfd2_508m", 594 }; 595 596 static const char *enet_p[] = { 597 "enet_podf", 598 "ipp_di0", 599 "ipp_di1", 600 "ldb_di0", 601 "ldb_di1", 602 }; 603 604 static const char *m4_pre_p[] = { 605 "pll2_bus", 606 "pll3_usb_otg", 607 "osc", 608 "pll2_pfd0_352m", 609 "pll2_pfd2_396m", 610 "pll3_pfd3_454m", 611 }; 612 613 static const char *m4_p[] = { 614 "m4_pre_sel", 615 "ipp_di0", 616 "ipp_di1", 617 "ldb_di0", 618 "ldb_di1", 619 }; 620 621 static const char *eim_slow_p[] = { 622 "ocram", 623 "pll3_usb_otg", 624 "pll2_pfd2_396m", 625 "pll2_pfd0_352m" 626 }; 627 628 static const char *ecspi_p[] = { 629 "pll3_60m", 630 "osc", 631 }; 632 633 static const char *lcdif1_pre_p[] = { 634 "pll2_bus", 635 "pll3_pfd3_454m", 636 "pll5_video_div", 637 "pll2_pfd0_352m", 638 "pll2_pfd1_594m", 639 "pll3_pfd1_540m", 640 }; 641 642 static const char *lcdif1_p[] = { 643 "lcdif1_podf", 644 "ipp_di0", 645 "ipp_di1", 646 "ldb_di0", 647 "ldb_di1", 648 }; 649 650 static const char *lcdif2_pre_p[] = { 651 "pll2_bus", 652 "pll3_pfd3_454m", 653 "pll5_video_div", 654 "pll2_pfd0_352m", 655 "pll2_pfd3_594m", 656 "pll3_pfd1_540m", 657 }; 658 659 static const char *lcdif2_p[] = { 660 "lcdif2_podf", 661 "ipp_di0", 662 "ipp_di1", 663 "ldb_di0", 664 "ldb_di1", 665 }; 666 667 static const char *display_p[] = { 668 "pll2_bus", 669 "pll2_pfd2_396m", 670 "pll3_usb_otg", 671 "pll3_pfd1_540m", 672 }; 673 674 static const char *csi_p[] = { 675 "osc", 676 "pll2_pfd2_396m", 677 "pll3_120m", 678 "pll3_pfd1_540m", 679 }; 680 681 static const char *lvds_p[] = { 682 "arm", 683 "pll1_sys", 684 "dummy", 685 "dummy", 686 "dummy", 687 "dummy", 688 "dummy", 689 "pll5_video_div", 690 "dummy", 691 "dummy", 692 "pcie_ref_125m", 693 "dummy", 694 "usbphy1", 695 "usbphy2", 696 }; 697 698 /* DT clock ID to clock name mappings */ 699 static struct imx_clock_id { 700 u_int id; 701 const char *name; 702 } imx6sx_clock_ids[] = { 703 { IMX6SXCLK_DUMMY, "dummy" }, 704 { IMX6SXCLK_CKIL, "ckil" }, 705 { IMX6SXCLK_OSC, "osc" }, 706 { IMX6SXCLK_PLL1_SYS, "pll1_sys" }, 707 { IMX6SXCLK_PLL2_BUS, "pll2_bus" }, 708 { IMX6SXCLK_PLL3_USB_OTG, "pll3_usb_otg" }, 709 { IMX6SXCLK_PLL4_AUDIO, "pll4_audio" }, 710 { IMX6SXCLK_PLL5_VIDEO, "pll5_video" }, 711 { IMX6SXCLK_PLL6_ENET, "pll6_enet" }, 712 { IMX6SXCLK_PLL7_USB_HOST, "pll7_usb_host" }, 713 { IMX6SXCLK_USBPHY1, "usbphy1" }, 714 { IMX6SXCLK_USBPHY2, "usbphy2" }, 715 { IMX6SXCLK_USBPHY1_GATE, "usbphy1_gate" }, 716 { IMX6SXCLK_USBPHY2_GATE, "usbphy2_gate" }, 717 { IMX6SXCLK_PCIE_REF, "pcie_ref" }, 718 { IMX6SXCLK_PCIE_REF_125M, "pcie_ref_125m" }, 719 { IMX6SXCLK_PLL2_PFD0, "pll2_pfd0_352m" }, 720 { IMX6SXCLK_PLL2_PFD1, "pll2_pfd1_594m" }, 721 { IMX6SXCLK_PLL2_PFD2, "pll2_pfd2_396m" }, 722 { IMX6SXCLK_PLL2_PFD3, "pll2_pfd3_594m" }, 723 { IMX6SXCLK_PLL3_PFD0, "pll3_pfd0_720m" }, 724 { IMX6SXCLK_PLL3_PFD1, "pll3_pfd1_540m" }, 725 { IMX6SXCLK_PLL3_PFD2, "pll3_pfd2_508m" }, 726 { IMX6SXCLK_PLL3_PFD3, "pll3_pfd3_454m" }, 727 { IMX6SXCLK_PLL2_198M, "pll2_198m" }, 728 { IMX6SXCLK_PLL3_120M, "pll3_120m" }, 729 { IMX6SXCLK_PLL3_80M, "pll3_80m" }, 730 { IMX6SXCLK_PLL3_60M, "pll3_60m" }, 731 { IMX6SXCLK_TWD, "twd" }, 732 { IMX6SXCLK_PLL4_POST_DIV, "pll4_post_div" }, 733 { IMX6SXCLK_PLL4_AUDIO_DIV, "pll4_audio_div" }, 734 { IMX6SXCLK_PLL5_POST_DIV, "pll5_post_div" }, 735 { IMX6SXCLK_PLL5_VIDEO_DIV, "pll5_video_div" }, 736 { IMX6SXCLK_STEP, "step" }, 737 { IMX6SXCLK_PLL1_SW, "pll1_sw" }, 738 { IMX6SXCLK_OCRAM_SEL, "ocram_sel" }, 739 { IMX6SXCLK_PERIPH_PRE, "periph_pre" }, 740 { IMX6SXCLK_PERIPH2_PRE, "periph2_pre" }, 741 { IMX6SXCLK_PERIPH_CLK2_SEL, "periph_clk2_sel" }, 742 { IMX6SXCLK_PERIPH2_CLK2_SEL, "periph2_clk2_sel" }, 743 { IMX6SXCLK_PCIE_AXI_SEL, "pcie_axi_sel" }, 744 { IMX6SXCLK_GPU_AXI_SEL, "gpu_axi_sel" }, 745 { IMX6SXCLK_GPU_CORE_SEL, "gpu_core_sel" }, 746 { IMX6SXCLK_EIM_SLOW_SEL, "eim_slow_sel" }, 747 { IMX6SXCLK_USDHC1_SEL, "usdhc1_sel" }, 748 { IMX6SXCLK_USDHC2_SEL, "usdhc2_sel" }, 749 { IMX6SXCLK_USDHC3_SEL, "usdhc3_sel" }, 750 { IMX6SXCLK_USDHC4_SEL, "usdhc4_sel" }, 751 { IMX6SXCLK_SSI1_SEL, "ssi1_sel" }, 752 { IMX6SXCLK_SSI2_SEL, "ssi2_sel" }, 753 { IMX6SXCLK_SSI3_SEL, "ssi3_sel" }, 754 { IMX6SXCLK_QSPI1_SEL, "qspi1_sel" }, 755 { IMX6SXCLK_PERCLK_SEL, "perclk_sel" }, 756 { IMX6SXCLK_VID_SEL, "vid_sel" }, 757 { IMX6SXCLK_ESAI_SEL, "esai_sel" }, 758 { IMX6SXCLK_LDB_DI0_DIV_SEL, "ldb_di0_div_sel" }, 759 { IMX6SXCLK_LDB_DI1_DIV_SEL, "ldb_di1_div_sel" }, 760 { IMX6SXCLK_CAN_SEL, "can_sel" }, 761 { IMX6SXCLK_UART_SEL, "uart_sel" }, 762 { IMX6SXCLK_QSPI2_SEL, "qspi2_sel" }, 763 { IMX6SXCLK_LDB_DI0_SEL, "ldb_di0_sel" }, 764 { IMX6SXCLK_LDB_DI1_SEL, "ldb_di1_sel" }, 765 { IMX6SXCLK_SPDIF_SEL, "spdif_sel" }, 766 { IMX6SXCLK_AUDIO_SEL, "audio_sel" }, 767 { IMX6SXCLK_ENET_PRE_SEL, "enet_pre_sel" }, 768 { IMX6SXCLK_ENET_SEL, "enet_sel" }, 769 { IMX6SXCLK_M4_PRE_SEL, "m4_pre_sel" }, 770 { IMX6SXCLK_M4_SEL, "m4_sel" }, 771 { IMX6SXCLK_ECSPI_SEL, "ecspi_sel" }, 772 { IMX6SXCLK_LCDIF1_PRE_SEL, "lcdif1_pre_sel" }, 773 { IMX6SXCLK_LCDIF2_PRE_SEL, "lcdif2_pre_sel" }, 774 { IMX6SXCLK_LCDIF1_SEL, "lcdif1_sel" }, 775 { IMX6SXCLK_LCDIF2_SEL, "lcdif2_sel" }, 776 { IMX6SXCLK_DISPLAY_SEL, "display_sel" }, 777 { IMX6SXCLK_CSI_SEL, "csi_sel" }, 778 { IMX6SXCLK_CKO1_SEL, "cko1_sel" }, 779 { IMX6SXCLK_CKO2_SEL, "cko2_sel" }, 780 { IMX6SXCLK_CKO, "cko" }, 781 { IMX6SXCLK_PERIPH_CLK2, "periph_clk2" }, 782 { IMX6SXCLK_PERIPH2_CLK2, "periph2_clk2" }, 783 { IMX6SXCLK_IPG, "ipg" }, 784 { IMX6SXCLK_GPU_CORE_PODF, "gpu_core_podf" }, 785 { IMX6SXCLK_GPU_AXI_PODF, "gpu_axi_podf" }, 786 { IMX6SXCLK_LCDIF1_PODF, "lcdif1_podf" }, 787 { IMX6SXCLK_QSPI1_PODF, "qspi1_podf" }, 788 { IMX6SXCLK_EIM_SLOW_PODF, "eim_slow_podf" }, 789 { IMX6SXCLK_LCDIF2_PODF, "lcdif2_podf" }, 790 { IMX6SXCLK_PERCLK, "perclk" }, 791 { IMX6SXCLK_VID_PODF, "vid_podf" }, 792 { IMX6SXCLK_CAN_PODF, "can_podf" }, 793 { IMX6SXCLK_USDHC1_PODF, "usdhc1_podf" }, 794 { IMX6SXCLK_USDHC2_PODF, "usdhc2_podf" }, 795 { IMX6SXCLK_USDHC3_PODF, "usdhc3_podf" }, 796 { IMX6SXCLK_USDHC4_PODF, "usdhc4_podf" }, 797 { IMX6SXCLK_UART_PODF, "uart_podf" }, 798 { IMX6SXCLK_ESAI_PRED, "esai_pred" }, 799 { IMX6SXCLK_ESAI_PODF, "esai_podf" }, 800 { IMX6SXCLK_SSI3_PRED, "ssi3_pred" }, 801 { IMX6SXCLK_SSI3_PODF, "ssi3_podf" }, 802 { IMX6SXCLK_SSI1_PRED, "ssi1_pred" }, 803 { IMX6SXCLK_SSI1_PODF, "ssi1_podf" }, 804 { IMX6SXCLK_QSPI2_PRED, "qspi2_pred" }, 805 { IMX6SXCLK_QSPI2_PODF, "qspi2_podf" }, 806 { IMX6SXCLK_SSI2_PRED, "ssi2_pred" }, 807 { IMX6SXCLK_SSI2_PODF, "ssi2_podf" }, 808 { IMX6SXCLK_SPDIF_PRED, "spdif_pred" }, 809 { IMX6SXCLK_SPDIF_PODF, "spdif_podf" }, 810 { IMX6SXCLK_AUDIO_PRED, "audio_pred" }, 811 { IMX6SXCLK_AUDIO_PODF, "audio_podf" }, 812 { IMX6SXCLK_ENET_PODF, "enet_podf" }, 813 { IMX6SXCLK_M4_PODF, "m4_podf" }, 814 { IMX6SXCLK_ECSPI_PODF, "ecspi_podf" }, 815 { IMX6SXCLK_LCDIF1_PRED, "lcdif1_pred" }, 816 { IMX6SXCLK_LCDIF2_PRED, "lcdif2_pred" }, 817 { IMX6SXCLK_DISPLAY_PODF, "display_podf" }, 818 { IMX6SXCLK_CSI_PODF, "csi_podf" }, 819 { IMX6SXCLK_LDB_DI0_DIV_3_5, "ldb_di0_div_3_5" }, 820 { IMX6SXCLK_LDB_DI0_DIV_7, "ldb_di0_div_7" }, 821 { IMX6SXCLK_LDB_DI1_DIV_3_5, "ldb_di1_div_3_5" }, 822 { IMX6SXCLK_LDB_DI1_DIV_7, "ldb_di1_div_7" }, 823 { IMX6SXCLK_CKO1_PODF, "cko1_podf" }, 824 { IMX6SXCLK_CKO2_PODF, "cko2_podf" }, 825 { IMX6SXCLK_PERIPH, "periph" }, 826 { IMX6SXCLK_PERIPH2, "periph2" }, 827 { IMX6SXCLK_OCRAM, "ocram" }, 828 { IMX6SXCLK_AHB, "ahb" }, 829 { IMX6SXCLK_MMDC_PODF, "mmdc_podf" }, 830 { IMX6SXCLK_ARM, "arm" }, 831 { IMX6SXCLK_AIPS_TZ1, "aips_tz1" }, 832 { IMX6SXCLK_AIPS_TZ2, "aips_tz2" }, 833 { IMX6SXCLK_APBH_DMA, "apbh_dma" }, 834 { IMX6SXCLK_CAAM_MEM, "caam_mem" }, 835 { IMX6SXCLK_CAAM_ACLK, "caam_aclk" }, 836 { IMX6SXCLK_CAAM_IPG, "caam_ipg" }, 837 { IMX6SXCLK_CAN1_IPG, "can1_ipg" }, 838 { IMX6SXCLK_CAN1_SERIAL, "can1_serial" }, 839 { IMX6SXCLK_CAN2_IPG, "can2_ipg" }, 840 { IMX6SXCLK_CAN2_SERIAL, "can2_serial" }, 841 { IMX6SXCLK_DCIC1, "dcic1" }, 842 { IMX6SXCLK_DCIC2, "dcic2" }, 843 { IMX6SXCLK_AIPS_TZ3, "aips_tz3" }, 844 { IMX6SXCLK_ECSPI1, "ecspi1" }, 845 { IMX6SXCLK_ECSPI2, "ecspi2" }, 846 { IMX6SXCLK_ECSPI3, "ecspi3" }, 847 { IMX6SXCLK_ECSPI4, "ecspi4" }, 848 { IMX6SXCLK_ECSPI5, "ecspi5" }, 849 { IMX6SXCLK_EPIT1, "epit1" }, 850 { IMX6SXCLK_EPIT2, "epit2" }, 851 { IMX6SXCLK_ESAI_EXTAL, "esai_extal" }, 852 { IMX6SXCLK_WAKEUP, "wakeup" }, 853 { IMX6SXCLK_GPT_BUS, "gpt_bus" }, 854 { IMX6SXCLK_GPT_SERIAL, "gpt_serial" }, 855 { IMX6SXCLK_GPU, "gpu" }, 856 { IMX6SXCLK_OCRAM_S, "ocram_s" }, 857 { IMX6SXCLK_CANFD, "canfd" }, 858 { IMX6SXCLK_CSI, "csi" }, 859 { IMX6SXCLK_I2C1, "i2c1" }, 860 { IMX6SXCLK_I2C2, "i2c2" }, 861 { IMX6SXCLK_I2C3, "i2c3" }, 862 { IMX6SXCLK_OCOTP, "ocotp" }, 863 { IMX6SXCLK_IOMUXC, "iomuxc" }, 864 { IMX6SXCLK_IPMUX1, "ipmux1" }, 865 { IMX6SXCLK_IPMUX2, "ipmux2" }, 866 { IMX6SXCLK_IPMUX3, "ipmux3" }, 867 { IMX6SXCLK_TZASC1, "tzasc1" }, 868 { IMX6SXCLK_LCDIF_APB, "lcdif_apb" }, 869 { IMX6SXCLK_PXP_AXI, "pxp_axi" }, 870 { IMX6SXCLK_M4, "m4" }, 871 { IMX6SXCLK_ENET, "enet" }, 872 { IMX6SXCLK_DISPLAY_AXI, "display_axi" }, 873 { IMX6SXCLK_LCDIF2_PIX, "lcdif2_pix" }, 874 { IMX6SXCLK_LCDIF1_PIX, "lcdif1_pix" }, 875 { IMX6SXCLK_LDB_DI0, "ldb_di0" }, 876 { IMX6SXCLK_QSPI1, "qspi1" }, 877 { IMX6SXCLK_MLB, "mlb" }, 878 { IMX6SXCLK_MMDC_P0_FAST, "mmdc_p0_fast" }, 879 { IMX6SXCLK_MMDC_P0_IPG, "mmdc_p0_ipg" }, 880 { IMX6SXCLK_PCIE_AXI, "pcie_axi" }, 881 { IMX6SXCLK_QSPI2, "qspi2" }, 882 { IMX6SXCLK_PER1_BCH, "per1_bch" }, 883 { IMX6SXCLK_PER2_MAIN, "per2_main" }, 884 { IMX6SXCLK_PWM1, "pwm1" }, 885 { IMX6SXCLK_PWM2, "pwm2" }, 886 { IMX6SXCLK_PWM3, "pwm3" }, 887 { IMX6SXCLK_PWM4, "pwm4" }, 888 { IMX6SXCLK_GPMI_BCH_APB, "gpmi_bch_apb" }, 889 { IMX6SXCLK_GPMI_BCH, "gpmi_bch" }, 890 { IMX6SXCLK_GPMI_IO, "gpmi_io" }, 891 { IMX6SXCLK_GPMI_APB, "gpmi_apb" }, 892 { IMX6SXCLK_ROM, "rom" }, 893 { IMX6SXCLK_SDMA, "sdma" }, 894 { IMX6SXCLK_SPBA, "spba" }, 895 { IMX6SXCLK_SPDIF, "spdif" }, 896 { IMX6SXCLK_SSI1_IPG, "ssi1_ipg" }, 897 { IMX6SXCLK_SSI2_IPG, "ssi2_ipg" }, 898 { IMX6SXCLK_SSI3_IPG, "ssi3_ipg" }, 899 { IMX6SXCLK_SSI1, "ssi1" }, 900 { IMX6SXCLK_SSI2, "ssi2" }, 901 { IMX6SXCLK_SSI3, "ssi3" }, 902 { IMX6SXCLK_UART_IPG, "uart_ipg" }, 903 { IMX6SXCLK_UART_SERIAL, "uart_serial" }, 904 { IMX6SXCLK_SAI1, "sai1" }, 905 { IMX6SXCLK_SAI2, "sai2" }, 906 { IMX6SXCLK_USBOH3, "usboh3" }, 907 { IMX6SXCLK_USDHC1, "usdhc1" }, 908 { IMX6SXCLK_USDHC2, "usdhc2" }, 909 { IMX6SXCLK_USDHC3, "usdhc3" }, 910 { IMX6SXCLK_USDHC4, "usdhc4" }, 911 { IMX6SXCLK_EIM_SLOW, "eim_slow" }, 912 { IMX6SXCLK_PWM8, "pwm8" }, 913 { IMX6SXCLK_VADC, "vadc" }, 914 { IMX6SXCLK_GIS, "gis" }, 915 { IMX6SXCLK_I2C4, "i2c4" }, 916 { IMX6SXCLK_PWM5, "pwm5" }, 917 { IMX6SXCLK_PWM6, "pwm6" }, 918 { IMX6SXCLK_PWM7, "pwm7" }, 919 { IMX6SXCLK_CKO1, "cko1" }, 920 { IMX6SXCLK_CKO2, "cko2" }, 921 { IMX6SXCLK_IPP_DI0, "ipp_di0" }, 922 { IMX6SXCLK_IPP_DI1, "ipp_di1" }, 923 { IMX6SXCLK_ENET_AHB, "enet_ahb" }, 924 { IMX6SXCLK_OCRAM_PODF, "ocram_podf" }, 925 { IMX6SXCLK_GPT_3M, "gpt_3m" }, 926 { IMX6SXCLK_ENET_PTP, "enet_ptp_25m" }, 927 { IMX6SXCLK_ENET_PTP_REF, "enet_ptp_ref" }, 928 { IMX6SXCLK_ENET2_REF, "enet2_ref" }, 929 { IMX6SXCLK_ENET2_REF_125M, "enet2_ref_125m" }, 930 { IMX6SXCLK_AUDIO, "audio" }, 931 { IMX6SXCLK_LVDS1_SEL, "lvds1_sel" }, 932 { IMX6SXCLK_LVDS1_OUT, "lvds1_out" }, 933 { IMX6SXCLK_ASRC_IPG, "asrc_ipg" }, 934 { IMX6SXCLK_ASRC_MEM, "asrc_mem" }, 935 { IMX6SXCLK_SAI1_IPG, "sai1_ipg" }, 936 { IMX6SXCLK_SAI2_IPG, "sai2_ipg" }, 937 { IMX6SXCLK_ESAI_IPG, "esai_ipg" }, 938 { IMX6SXCLK_ESAI_MEM, "esai_mem" }, 939 { IMX6SXCLK_LVDS1_IN, "lvds1_in" }, 940 { IMX6SXCLK_ANACLK1, "anaclk1" }, 941 { IMX6SXCLK_PLL1_BYPASS_SRC, "pll1_bypass_src" }, 942 { IMX6SXCLK_PLL2_BYPASS_SRC, "pll2_bypass_src" }, 943 { IMX6SXCLK_PLL3_BYPASS_SRC, "pll3_bypass_src" }, 944 { IMX6SXCLK_PLL4_BYPASS_SRC, "pll4_bypass_src" }, 945 { IMX6SXCLK_PLL5_BYPASS_SRC, "pll5_bypass_src" }, 946 { IMX6SXCLK_PLL6_BYPASS_SRC, "pll6_bypass_src" }, 947 { IMX6SXCLK_PLL7_BYPASS_SRC, "pll7_bypass_src" }, 948 { IMX6SXCLK_PLL1, "pll1" }, 949 { IMX6SXCLK_PLL2, "pll2" }, 950 { IMX6SXCLK_PLL3, "pll3" }, 951 { IMX6SXCLK_PLL4, "pll4" }, 952 { IMX6SXCLK_PLL5, "pll5" }, 953 { IMX6SXCLK_PLL6, "pll6" }, 954 { IMX6SXCLK_PLL7, "pll7" }, 955 { IMX6SXCLK_PLL1_BYPASS, "pll1_bypass" }, 956 { IMX6SXCLK_PLL2_BYPASS, "pll2_bypass" }, 957 { IMX6SXCLK_PLL3_BYPASS, "pll3_bypass" }, 958 { IMX6SXCLK_PLL4_BYPASS, "pll4_bypass" }, 959 { IMX6SXCLK_PLL5_BYPASS, "pll5_bypass" }, 960 { IMX6SXCLK_PLL6_BYPASS, "pll6_bypass" }, 961 { IMX6SXCLK_PLL7_BYPASS, "pll7_bypass" }, 962 { IMX6SXCLK_SPDIF_GCLK, "spdif_gclk" }, 963 { IMX6SXCLK_LVDS2_SEL, "lvds2_sel" }, 964 { IMX6SXCLK_LVDS2_OUT, "lvds2_out" }, 965 { IMX6SXCLK_LVDS2_IN, "lvds2_in" }, 966 { IMX6SXCLK_ANACLK2, "anaclk2" }, 967 { IMX6SXCLK_MMDC_P1_IPG, "mmdc_p1_ipg" }, 968 { IMX6SXCLK_END, "end" }, 969 }; 970 971 /* Clock Divider Tables */ 972 static const int enet_ref_tbl[] = { 20, 10, 5, 4, 0 }; 973 static const int post_div_tbl[] = { 4, 2, 1, 0 }; 974 static const int audiovideo_div_tbl[] = { 1, 2, 1, 4, 0 }; 975 976 static struct imx6_clk imx6sx_clks[] = { 977 CLK_FIXED("dummy", 0), 978 CLK_FIXED("ckil", IMX6_CKIL_FREQ), 979 CLK_FIXED("osc", IMX6_OSC_FREQ), 980 CLK_FIXED("ipp_di0", IMX6_OSC_FREQ), 981 CLK_FIXED("ipp_di1", IMX6_OSC_FREQ), 982 CLK_FIXED("anaclk1", IMX6_ANACLK1_FREQ), 983 CLK_FIXED("anaclk2", IMX6_ANACLK2_FREQ), 984 985 CLK_FIXED_FACTOR("pcie_ref", "pll6_enet", 5, 1), 986 CLK_FIXED_FACTOR("pll2_198m", "pll2_pfd2_396m", 2, 1), 987 CLK_FIXED_FACTOR("pll3_120m", "pll3_usb_otg", 4, 1), 988 CLK_FIXED_FACTOR("pll3_80m", "pll3_usb_otg", 6, 1), 989 CLK_FIXED_FACTOR("pll3_60m", "pll3_usb_otg", 8, 1), 990 CLK_FIXED_FACTOR("twd", "arm", 2, 1), 991 CLK_FIXED_FACTOR("gpt_3m", "osc", 8, 1), 992 CLK_FIXED_FACTOR("ldb_di0_div_3_5", "ldb_di0_sel", 7, 2), 993 CLK_FIXED_FACTOR("ldb_di0_div_7", "ldb_di0_sel", 7, 1), 994 CLK_FIXED_FACTOR("ldb_di1_div_3_5", "ldb_di1_sel", 7, 2), 995 CLK_FIXED_FACTOR("ldb_di1_div_7", "ldb_di1_sel", 7, 1), 996 CLK_FIXED_FACTOR("enet_ptp_ref", "pll6_enet", 20, 1), 997 998 CLK_PFD("pll2_pfd0_352m", "pll2_bus", PFD_528, 0), 999 CLK_PFD("pll2_pfd1_594m", "pll2_bus", PFD_528, 1), 1000 CLK_PFD("pll2_pfd2_396m", "pll2_bus", PFD_528, 2), 1001 CLK_PFD("pll2_pfd3_594m", "pll2_bus", PFD_528, 3), 1002 CLK_PFD("pll3_pfd0_720m", "pll3_usb_otg", PFD_480, 0), 1003 CLK_PFD("pll3_pfd1_540m", "pll3_usb_otg", PFD_480, 1), 1004 CLK_PFD("pll3_pfd2_508m", "pll3_usb_otg", PFD_480, 2), 1005 CLK_PFD("pll3_pfd3_454m", "pll3_usb_otg", PFD_480, 3), 1006 1007 CLK_PLL("pll1", "osc", SYS, PLL_ARM, DIV_SELECT, POWERDOWN, 0), 1008 CLK_PLL("pll2", "osc", GENERIC, PLL_SYS, DIV_SELECT, POWERDOWN, 0), 1009 CLK_PLL("pll3", "osc", USB, PLL_USB1, DIV_SELECT, POWER, 0), 1010 CLK_PLL("pll4", "osc", AUDIO_VIDEO, PLL_AUDIO, DIV_SELECT, POWERDOWN, 0), 1011 CLK_PLL("pll5", "osc", AUDIO_VIDEO, PLL_VIDEO, DIV_SELECT, POWERDOWN, 0), 1012 CLK_PLL("pll6", "osc", ENET, PLL_ENET, DIV_SELECT, POWERDOWN, 500000000), 1013 CLK_PLL("pll7", "osc", USB, PLL_USB2, DIV_SELECT, POWER, 0), 1014 1015 CLK_DIV("periph_clk2", "periph_clk2_sel", CBCDR, PERIPH_CLK2_PODF), 1016 CLK_DIV("periph2_clk2", "periph2_clk2_sel", CBCDR, PERIPH2_CLK2_PODF), 1017 CLK_DIV_BUSY("ocram_podf", "ocram_sel", CBCDR, AXI_PODF, CDHIPR, AXI_PODF_BUSY), 1018 CLK_DIV("ipg", "ahb", CBCDR, IPG_PODF), 1019 CLK_DIV("gpu_core_podf", "gpu_core_sel", CBCMR, GPU3D_SHADER_PODF), 1020 CLK_DIV("gpu_axi_podf", "gpu_axi_sel", CBCMR, GPU3D_CORE_PODF), 1021 CLK_DIV("lcdif1_podf", "lcdif1_pred", CBCMR, GPU2D_CORE_CLK_PODF), 1022 CLK_DIV("esai_pred", "esai_sel", CS1CDR, ESAI_CLK_PRED), 1023 CLK_DIV("esai_podf", "esai_pred", CS1CDR, ESAI_CLK_PODF), 1024 CLK_DIV("spdif_pred", "spdif_sel", CDCDR, SPDIF0_CLK_PRED), 1025 CLK_DIV("spdif_podf", "spdif_pred", CDCDR, SPDIF0_CLK_PODF), 1026 CLK_DIV("audio_pred", "audio_sel", CDCDR, SPDIF1_CLK_PRED), 1027 CLK_DIV("audio_podf", "audio_pred", CDCDR, SPDIF1_CLK_PODF), 1028 CLK_DIV("vid_podf", "vid_sel", CSCMR2, VID_CLK_PODF), 1029 CLK_DIV("can_podf", "can_sel", CSCMR2, CAN_CLK_PODF), 1030 CLK_DIV("display_podf", "display_sel", CSCDR3, IPU2_HSP_PODF), 1031 CLK_DIV("csi_podf", "csi_sel", CSCDR3, IPU1_HSP_PODF), 1032 CLK_DIV("enet_podf", "enet_pre_sel", CHSCCDR, IPU1_DI1_PODF), 1033 CLK_DIV("m4_podf", "m4_sel", CHSCCDR, IPU1_DI0_PODF), 1034 CLK_DIV("ecspi_podf", "ecspi_sel", CSCDR2, ECSPI_CLK_PODF), 1035 CLK_DIV("lcdif1_pred", "lcdif1_pre_sel", CSCDR2, IPU2_DI1_PODF), 1036 CLK_DIV("lcdif2_pred", "lcdif2_pre_sel", CSCDR2, IPU2_DI0_PODF), 1037 CLK_DIV("ssi1_pred", "ssi1_sel", CS1CDR, SSI1_CLK_PRED), 1038 CLK_DIV("ssi1_podf", "ssi1_pred", CS1CDR, SSI1_CLK_PODF), 1039 CLK_DIV("ssi2_pred", "ssi2_sel", CS2CDR, SSI2_CLK_PRED), 1040 CLK_DIV("ssi2_podf", "ssi2_pred", CS2CDR, SSI2_CLK_PODF), 1041 CLK_DIV("ssi3_pred", "ssi3_sel", CS1CDR, SSI3_CLK_PRED), 1042 CLK_DIV("ssi3_podf", "ssi3_pred", CS1CDR, SSI3_CLK_PODF), 1043 CLK_DIV("usdhc1_podf", "usdhc1_sel", CSCDR1, USDHC1_PODF), 1044 CLK_DIV("usdhc2_podf", "usdhc2_sel", CSCDR1, USDHC2_PODF), 1045 CLK_DIV("usdhc3_podf", "usdhc3_sel", CSCDR1, USDHC3_PODF), 1046 CLK_DIV("usdhc4_podf", "usdhc4_sel", CSCDR1, USDHC4_PODF), 1047 CLK_DIV("uart_podf", "uart_sel", CSCDR1, UART_CLK_PODF), 1048 CLK_DIV("qspi2_pred", "qspi2_sel", CS2CDR, ENFC_CLK_PRED), 1049 CLK_DIV("qspi2_podf", "qspi2_pred", CS2CDR, ENFC_CLK_PODF), 1050 CLK_DIV("cko1_podf", "cko1_sel", CCOSR, CLKO1_DIV), 1051 CLK_DIV("cko2_podf", "cko2_sel", CCOSR, CLKO2_DIV), 1052 CLK_DIV("qspi1_podf", "qspi1_sel", CSCMR1, QSPI1_PODF), 1053 CLK_DIV("eim_slow_podf", "eim_slow_sel", CSCMR1, ACLK_EIM_SLOW_PODF), 1054 CLK_DIV("lcdif2_podf", "lcdif2_pred", CSCMR1, ACLK_PODF), 1055 CLK_DIV("perclk", "perclk_sel", CSCMR1, PERCLK_PODF), 1056 1057 CLK_DIV_BUSY("arm", "pll1_sw", CACRR, ARM_PODF, CDHIPR, ARM_PODF_BUSY), 1058 CLK_DIV_BUSY("ahb", "periph", CBCDR, AHB_PODF, CDHIPR, AHB_PODF_BUSY), 1059 CLK_DIV_BUSY("mmdc_podf", "periph2", CBCDR, MMDC_CH1_AXI_PODF, CDHIPR, MMDC_CH1_PODF_BUSY), 1060 1061 CLK_DIV_TABLE("pll4_post_div", "pll4_audio", PLL_AUDIO, POST_DIV_SELECT, post_div_tbl), 1062 CLK_DIV_TABLE("pll4_audio_div", "pll4_post_div", MISC2, AUDIO_DIV_LSB, audiovideo_div_tbl), 1063 CLK_DIV_TABLE("pll5_post_div", "pll5_video", PLL_VIDEO, POST_DIV_SELECT, post_div_tbl), 1064 CLK_DIV_TABLE("pll5_video_div", "pll5_post_div", MISC2, VIDEO_DIV, audiovideo_div_tbl), 1065 CLK_DIV_TABLE("enet_ref", "pll6_enet", PLL_ENET, DIV_SELECT, enet_ref_tbl), 1066 CLK_DIV_TABLE("enet2_ref", "pll6_enet", PLL_ENET, DIV2_SELECT, enet_ref_tbl), 1067 1068 CLK_MUX("step", step_p, CCM, CCSR, STEP_SEL), 1069 CLK_MUX("pll1_sw", pll1_sw_p, CCM, CCSR, PLL1_SW_CLK_SEL), 1070 CLK_MUX("ocram_sel", ocram_p, CCM, CBCDR, AXI_SEL), 1071 CLK_MUX("periph_pre", periph_pre_p, CCM, CBCMR, PRE_PERIPH_CLK_SEL), 1072 CLK_MUX("periph2_pre", periph2_pre_p, CCM, CBCMR, PRE_PERIPH2_CLK_SEL), 1073 CLK_MUX("periph_clk2_sel", periph_clk2_p, CCM,CBCMR, PERIPH_CLK2_SEL), 1074 CLK_MUX("periph2_clk2_sel", periph2_clk2_p, CCM,CBCMR, PERIPH2_CLK2_SEL), 1075 CLK_MUX("spdif_sel", audio_p, CCM, CDCDR, SPDIF0_CLK_SEL), 1076 CLK_MUX("audio_sel", audio_p, CCM, CDCDR, SPDIF1_CLK_SEL), 1077 CLK_MUX("vid_sel", vid_p, CCM, CSCMR2, VID_CLK_SEL), 1078 CLK_MUX("esai_sel", audio_p, CCM, CSCMR2, ESAI_CLK_SEL), 1079 CLK_MUX("ldb_di0_div_sel", ldb_di0_div_p, CCM, CSCMR2, LDB_DI0_IPU_DIV), 1080 CLK_MUX("ldb_di1_div_sel", ldb_di1_div_p, CCM, CSCMR2, LDB_DI1_IPU_DIV), 1081 CLK_MUX("can_sel", can_p, CCM, CSCMR2, CAN_CLK_SEL), 1082 CLK_MUX("uart_sel", uart_p, CCM, CSCDR1, UART_CLK_SEL), 1083 CLK_MUX("enet_pre_sel", enet_pre_p, CCM, CHSCCDR, ENET_PRE_CLK_SEL), 1084 CLK_MUX("enet_sel", enet_p, CCM, CHSCCDR, ENET_CLK_SEL), 1085 CLK_MUX("m4_pre_sel", m4_pre_p, CCM, CHSCCDR, M4_PRE_CLK_SEL), 1086 CLK_MUX("m4_sel", m4_p, CCM, CHSCCDR, M4_CLK_SEL), 1087 CLK_MUX("ecspi_sel", ecspi_p, CCM, CSCDR2, ECSPI_SEL), 1088 CLK_MUX("lcdif1_sel", lcdif1_p, CCM, CSCDR2, IPU2_DI1_CLK_SEL), 1089 CLK_MUX("lcdif1_pre_sel", lcdif1_pre_p, CCM, CSCDR2, IPU2_DI1_PRE_CLK_SEL), 1090 CLK_MUX("lcdif1_sel", lcdif1_p, CCM, CSCDR2, IPU2_DI1_CLK_SEL), 1091 CLK_MUX("lcdif2_pre_sel", lcdif2_pre_p, CCM, CSCDR2, IPU2_DI0_PRE_CLK_SEL), 1092 CLK_MUX("lcdif2_sel", lcdif2_p, CCM, CSCDR2, IPU2_DI0_CLK_SEL), 1093 CLK_MUX("display_sel", display_p, CCM, CSCDR3, IPU2_HSP_CLK_SEL), 1094 CLK_MUX("csi_sel", csi_p, CCM, CSCDR3, IPU1_HSP_CLK_SEL), 1095 CLK_MUX("qspi2_sel", qspi2_p, CCM, CS2CDR, QSPI2_CLK_SEL), 1096 CLK_MUX("ldb_di0_sel", ldb_di0_p, CCM, CS2CDR, LDB_DI0_CLK_SEL), 1097 CLK_MUX("ldb_di1_sel", ldb_di1_p, CCM, CS2CDR, LDB_DI1_CLK_SEL), 1098 CLK_MUX("cko1_sel", cko1_p, CCM, CCOSR, CLKO1_SEL), 1099 CLK_MUX("cko2_sel", cko2_p, CCM, CCOSR, CLKO2_SEL), 1100 CLK_MUX("cko", cko_p, CCM, CCOSR, CLK_OUT_SEL), 1101 CLK_MUX("pcie_axi_sel", pcie_axi_p, CCM, CBCMR, PCIE_AXI_CLK_SEL), 1102 CLK_MUX("gpu_axi_sel", gpu_axi_p, CCM, CBCMR, GPU3D_SHADER_CLK_SEL), 1103 CLK_MUX("gpu_core_sel", gpu_core_p, CCM, CBCMR, GPU3D_CORE_CLK_SEL), 1104 CLK_MUX("ssi1_sel", ssi_p, CCM, CSCMR1, SSI1_CLK_SEL), 1105 CLK_MUX("ssi2_sel", ssi_p, CCM, CSCMR1, SSI2_CLK_SEL), 1106 CLK_MUX("ssi3_sel", ssi_p, CCM, CSCMR1, SSI3_CLK_SEL), 1107 CLK_MUX("usdhc1_sel", usdhc_p, CCM, CSCMR1, USDHC1_CLK_SEL), 1108 CLK_MUX("usdhc2_sel", usdhc_p, CCM, CSCMR1, USDHC2_CLK_SEL), 1109 CLK_MUX("usdhc3_sel", usdhc_p, CCM, CSCMR1, USDHC3_CLK_SEL), 1110 CLK_MUX("usdhc4_sel", usdhc_p, CCM, CSCMR1, USDHC4_CLK_SEL), 1111 CLK_MUX("qspi1_sel", qspi1_p, CCM, CSCMR1, QSOI1_SEL), 1112 CLK_MUX("perclk_sel", perclk_p, CCM, CSCMR1, PERCLK_SEL), 1113 CLK_MUX("eim_slow_sel", eim_slow_p, CCM, CSCMR1, ACLK_EIM_SLOW_SEL), 1114 CLK_MUX("pll1_bypass_src", pll_bypass_src_p, CCM_ANALOG, PLL_ARM, BYPASS_CLK_SRC_6SX), 1115 CLK_MUX("pll2_bypass_src", pll_bypass_src_p, CCM_ANALOG, PLL_SYS, BYPASS_CLK_SRC_6SX), 1116 CLK_MUX("pll3_bypass_src", pll_bypass_src_p, CCM_ANALOG, PLL_USB1, BYPASS_CLK_SRC_6SX), 1117 CLK_MUX("pll4_bypass_src", pll_bypass_src_p, CCM_ANALOG, PLL_AUDIO, BYPASS_CLK_SRC_6SX), 1118 CLK_MUX("pll5_bypass_src", pll_bypass_src_p, CCM_ANALOG, PLL_VIDEO, BYPASS_CLK_SRC_6SX), 1119 CLK_MUX("pll6_bypass_src", pll_bypass_src_p, CCM_ANALOG, PLL_ENET, BYPASS_CLK_SRC_6SX), 1120 CLK_MUX("pll7_bypass_src", pll_bypass_src_p, CCM_ANALOG, PLL_USB2, BYPASS_CLK_SRC_6SX), 1121 CLK_MUX("pll1_bypass", pll1_bypass_p, CCM_ANALOG, PLL_ARM, BYPASS), 1122 CLK_MUX("pll2_bypass", pll2_bypass_p, CCM_ANALOG, PLL_SYS, BYPASS), 1123 CLK_MUX("pll3_bypass", pll3_bypass_p, CCM_ANALOG, PLL_USB1, BYPASS), 1124 CLK_MUX("pll4_bypass", pll4_bypass_p, CCM_ANALOG, PLL_AUDIO, BYPASS), 1125 CLK_MUX("pll5_bypass", pll5_bypass_p, CCM_ANALOG, PLL_VIDEO, BYPASS), 1126 CLK_MUX("pll6_bypass", pll6_bypass_p, CCM_ANALOG, PLL_ENET, BYPASS), 1127 CLK_MUX("pll7_bypass", pll7_bypass_p, CCM_ANALOG, PLL_USB2, BYPASS), 1128 1129 CLK_MUX("lvds1_sel", lvds_p, CCM_ANALOG, MISC1, LVDS_CLK1_SRC), 1130 CLK_MUX("lvds2_sel", lvds_p, CCM_ANALOG, MISC1, LVDS_CLK2_SRC), 1131 1132 CLK_MUX_BUSY("periph", periph_p, CBCDR, PERIPH_CLK_SEL, CDHIPR, PERIPH_CLK_SEL_BUSY), 1133 CLK_MUX_BUSY("periph2", periph2_p, CBCDR, PERIPH2_CLK_SEL, CDHIPR, PERIPH2_CLK_SEL_BUSY), 1134 1135 CLK_GATE("aips_tz1", "ahb", CCM, CCGR0, AIPS_TZ1_CLK_ENABLE), 1136 CLK_GATE("aips_tz2", "ahb", CCM, CCGR0, AIPS_TZ2_CLK_ENABLE), 1137 CLK_GATE("apbh_dma", "usdhc3", CCM, CCGR0, APBHDMA_HCLK_ENABLE), 1138 CLK_GATE("asrc_ipg", "ahb", CCM, CCGR0, ASRC_CLK_ENABLE), 1139 CLK_GATE("asrc_mem", "ahb", CCM, CCGR0, ASRC_CLK_ENABLE), 1140 CLK_GATE("caam_mem", "ahb", CCM, CCGR0, CAAM_SECURE_MEM_CLK_ENABLE), 1141 CLK_GATE("caam_aclk", "ahb", CCM, CCGR0, CAAM_WRAPPER_ACLK_ENABLE), 1142 CLK_GATE("caam_ipg", "ipg", CCM, CCGR0, CAAM_WRAPPER_IPG_ENABLE), 1143 CLK_GATE("can1_ipg", "ipg", CCM, CCGR0, CAN1_CLK_ENABLE), 1144 CLK_GATE("can1_serial", "can_podf", CCM, CCGR0, CAN1_SERIAL_CLK_ENABLE), 1145 CLK_GATE("can2_ipg", "ipg", CCM, CCGR0, CAN2_CLK_ENABLE), 1146 CLK_GATE("can2_serial", "can_podf", CCM, CCGR0, CAN2_SERIAL_CLK_ENABLE), 1147 CLK_GATE("dcic1", "display_podf", CCM, CCGR0, DCIC1_CLK_ENABLE), 1148 CLK_GATE("dcic2", "display_podf", CCM, CCGR0, DCIC2_CLK_ENABLE), 1149 CLK_GATE("aips_tz3", "ahb", CCM, CCGR0, TZ3_CLK_ENABLE), 1150 CLK_GATE("ecspi1", "ecspi_podf", CCM, CCGR1, ECSPI1_CLK_ENABLE), 1151 CLK_GATE("ecspi2", "ecspi_podf", CCM, CCGR1, ECSPI2_CLK_ENABLE), 1152 CLK_GATE("ecspi3", "ecspi_podf", CCM, CCGR1, ECSPI3_CLK_ENABLE), 1153 CLK_GATE("ecspi4", "ecspi_podf", CCM, CCGR1, ECSPI4_CLK_ENABLE), 1154 CLK_GATE("ecspi5", "ecspi_podf", CCM, CCGR1, ECSPI5_CLK_ENABLE), 1155 CLK_GATE("epit1", "perclk", CCM, CCGR1, EPIT1_CLK_ENABLE), 1156 CLK_GATE("epit2", "perclk", CCM, CCGR1, EPIT2_CLK_ENABLE), 1157 CLK_GATE("esai_extal", "esai_podf", CCM, CCGR1, ESAI_CLK_ENABLE), 1158 CLK_GATE("esai_ipg", "ahb", CCM, CCGR1, ESAI_CLK_ENABLE), 1159 CLK_GATE("esai_mem", "ahb", CCM, CCGR1, ESAI_CLK_ENABLE), 1160 CLK_GATE("wakeup", "ipg", CCM, CCGR1, WAKEUP_CLK_ENABLE), 1161 CLK_GATE("gpt_bus", "perclk", CCM, CCGR1, GPT_CLK_ENABLE), 1162 CLK_GATE("gpt_serial", "perclk", CCM, CCGR1, GPT_SERIAL_CLK_ENABLE), 1163 CLK_GATE("gpu", "gpu_core_podf", CCM, CCGR1, GPU3D_CLK_ENABLE), 1164 CLK_GATE("ocram_s", "ahb", CCM, CCGR1, OCRAM_CLK_ENABLE), 1165 CLK_GATE("canfd", "can_podf", CCM, CCGR1, CANFD_CLK_ENABLE), 1166 CLK_GATE("csi", "csi_podf", CCM, CCGR2, CSI_CLK_ENABLE), 1167 CLK_GATE("i2c1", "perclk", CCM, CCGR2, I2C1_SERIAL_CLK_ENABLE), 1168 CLK_GATE("i2c2", "perclk", CCM, CCGR2, I2C2_SERIAL_CLK_ENABLE), 1169 CLK_GATE("i2c3", "perclk", CCM, CCGR2, I2C3_SERIAL_CLK_ENABLE), 1170 CLK_GATE("ocotp", "ipg", CCM, CCGR2, IIM_CLK_ENABLE), 1171 CLK_GATE("iomuxc", "lcdif1_podf", CCM, CCGR2, IOMUX_IPT_CLK_IO_CLK_ENABLE), 1172 CLK_GATE("ipmux1", "ahb", CCM, CCGR2, IPMUX1_CLK_ENABLE), 1173 CLK_GATE("ipmux2", "ahb", CCM, CCGR2, IPMUX2_CLK_ENABLE), 1174 CLK_GATE("ipmux3", "ahb", CCM, CCGR2, IPMUX3_CLK_ENABLE), 1175 CLK_GATE("tzasc1", "mmdc_podf", CCM, CCGR2, IPSYNC_IP2APB_TZASC1_IPG_CLK_ENABLE), 1176 CLK_GATE("lcdif_apb", "display_podf", CCM, CCGR2, LCDIF_APB_CLK_ENABLE), 1177 CLK_GATE("pxp_axi", "display_podf", CCM, CCGR2, PXP_AXI_CLK_ENABLE), 1178 CLK_GATE("enet", "ipg", CCM, CCGR3, IPU1_IPU_DI1_CLK_ENABLE), 1179 CLK_GATE("enet_ahb", "enet_sel", CCM, CCGR3, IPU1_IPU_DI1_CLK_ENABLE), 1180 CLK_GATE("m4", "m4_podf", CCM, CCGR3, IPU1_IPU_DI0_CLK_ENABLE), 1181 CLK_GATE("display_axi", "display_podf", CCM, CCGR3, IPU2_IPU_CLK_ENABLE), 1182 CLK_GATE("lcdif2_pix", "lcdif2_sel", CCM, CCGR3, IPU2_IPU_DI0_CLK_ENABLE), 1183 CLK_GATE("lcdif1_pix", "lcdif1_sel", CCM, CCGR3, IPU2_IPU_DI1_CLK_ENABLE), 1184 CLK_GATE("ldb_di0", "ldb_di0_div_sel", CCM, CCGR3, LDB_DI0_CLK_ENABLE), 1185 CLK_GATE("qspi1", "qspi1_podf", CCM, CCGR3, LDB_DI1_CLK_ENABLE), 1186 CLK_GATE("mlb", "ahb", CCM, CCGR3, MLB_CLK_ENABLE), 1187 CLK_GATE("mmdc_p0_fast", "mmdc_podf", CCM, CCGR3, MMDC_CORE_ACLK_FAST_CORE_P0_ENABLE), 1188 CLK_GATE("mmdc_p0_ipg", "ipg", CCM, CCGR3, MMDC_CORE_IPG_CLK_P0_ENABLE), 1189 CLK_GATE("mmdc_p1_ipg", "ipg", CCM, CCGR3, MMDC_P1_IPG_CLK_ENABLE), 1190 CLK_GATE("ocram", "ahb", CCM, CCGR3, OCRAM_CLK_ENABLE), 1191 CLK_GATE("pcie_axi", "display_podf", CCM, CCGR4, PCIE_ROOT_ENABLE), 1192 CLK_GATE("qspi2", "qspi2_podf", CCM, CCGR4, QSPI2_ENABLE), 1193 CLK_GATE("per1_bch", "usdhc3", CCM, CCGR4, PL301_MX6QPER1_BCHCLK_ENABLE), 1194 CLK_GATE("per2_main", "ahb", CCM, CCGR4, PL301_MX6QPER2_MAINCLK_ENABLE), 1195 CLK_GATE("pwm1", "perclk", CCM, CCGR4, PWM1_CLK_ENABLE), 1196 CLK_GATE("pwm2", "perclk", CCM, CCGR4, PWM2_CLK_ENABLE), 1197 CLK_GATE("pwm3", "perclk", CCM, CCGR4, PWM3_CLK_ENABLE), 1198 CLK_GATE("pwm4", "perclk", CCM, CCGR4, PWM4_CLK_ENABLE), 1199 CLK_GATE("gpmi_bch_apb", "usdhc3", CCM, CCGR4, RAWNAND_U_BCH_INPUT_APB_CLK_ENABLE), 1200 CLK_GATE("gpmi_bch", "usdhc4", CCM, CCGR4, RAWNAND_U_GPMI_BCH_INPUT_BCH_CLK_ENABLE), 1201 CLK_GATE("gpmi_io", "qspi2_podf", CCM, CCGR4, RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_CLK_ENABLE), 1202 CLK_GATE("gpmi_apb", "usdhc3", CCM, CCGR4, RAWNAND_U_GPMI_INPUT_APB_CLK_ENABLE), 1203 CLK_GATE("rom", "ahb", CCM, CCGR5, ROM_CLK_ENABLE), 1204 CLK_GATE("sdma", "ahb", CCM, CCGR5, SDMA_CLK_ENABLE), 1205 CLK_GATE("spba", "ipg", CCM, CCGR5, SPBA_CLK_ENABLE), 1206 CLK_GATE("audio", "audio_podf", CCM, CCGR5, SPDIF_CLK_ENABLE), 1207 CLK_GATE("spdif", "spdif_podf", CCM, CCGR5, SPDIF_CLK_ENABLE), 1208 CLK_GATE("spdif_gclk", "ipg", CCM, CCGR5, SPDIF_CLK_ENABLE), 1209 CLK_GATE("ssi1_ipg", "ipg", CCM, CCGR5, SSI1_CLK_ENABLE), 1210 CLK_GATE("ssi2_ipg", "ipg", CCM, CCGR5, SSI2_CLK_ENABLE), 1211 CLK_GATE("ssi3_ipg", "ipg", CCM, CCGR5, SSI3_CLK_ENABLE), 1212 CLK_GATE("ssi1", "ssi1_podf", CCM, CCGR5, SSI1_CLK_ENABLE), 1213 CLK_GATE("ssi2", "ssi2_podf", CCM, CCGR5, SSI2_CLK_ENABLE), 1214 CLK_GATE("ssi3", "ssi3_podf", CCM, CCGR5, SSI3_CLK_ENABLE), 1215 CLK_GATE("uart_ipg", "ipg", CCM, CCGR5, UART_CLK_ENABLE), 1216 CLK_GATE("uart_serial", "uart_podf", CCM, CCGR5, UART_SERIAL_CLK_ENABLE), 1217 CLK_GATE("sai1", "ssi1_podf", CCM, CCGR5, SAI1_ENABLE), 1218 CLK_GATE("sai2", "ssi2_podf", CCM, CCGR5, SAI2_ENABLE), 1219 CLK_GATE("sai1_ipg", "ipg", CCM, CCGR5, SAI1_ENABLE), 1220 CLK_GATE("sai2_ipg", "ipg", CCM, CCGR5, SAI2_ENABLE), 1221 CLK_GATE("usboh3", "ipg", CCM, CCGR6, USBOH3_CLK_ENABLE), 1222 CLK_GATE("usdhc1", "usdhc1_podf", CCM, CCGR6, USDHC1_CLK_ENABLE), 1223 CLK_GATE("usdhc2", "usdhc2_podf", CCM, CCGR6, USDHC2_CLK_ENABLE), 1224 CLK_GATE("usdhc3", "usdhc3_podf", CCM, CCGR6, USDHC3_CLK_ENABLE), 1225 CLK_GATE("usdhc4", "usdhc4_podf", CCM, CCGR6, USDHC4_CLK_ENABLE), 1226 CLK_GATE("eim_slow", "eim_slow_podf", CCM, CCGR6, EIM_SLOW_CLK_ENABLE), 1227 CLK_GATE("pwm8", "perclk", CCM, CCGR6, PWM8_CLK_ENABLE), 1228 CLK_GATE("vadc", "vid_podf", CCM, CCGR6, VADC_CLK_ENABLE), 1229 CLK_GATE("gis", "display_podf", CCM, CCGR6, GIS_CLK_ENABLE), 1230 CLK_GATE("i2c4", "perclk", CCM, CCGR6, I2CS4_CLK_ENABLE), 1231 CLK_GATE("pwm5", "perclk", CCM, CCGR6, PWM5_CLK_ENABLE), 1232 CLK_GATE("pwm6", "perclk", CCM, CCGR6, PWM6_CLK_ENABLE), 1233 CLK_GATE("pwm7", "perclk", CCM, CCGR6, PWM7_CLK_ENABLE), 1234 CLK_GATE("cko1", "cko1_podf", CCM, CCOSR, CLKO1_EN), 1235 CLK_GATE("cko2", "cko2_podf", CCM, CCOSR, CLKO2_EN), 1236 CLK_GATE("enet_ptp_25m", "enet_ptp_ref", CCM_ANALOG, PLL_ENET, ENET_25M_REF_EN), 1237 CLK_GATE("enet2_ref_125m", "enet2_ref", CCM_ANALOG, PLL_ENET, ENABLE_100M), 1238 CLK_GATE("pcie_ref_125m", "pcie_ref", CCM_ANALOG, PLL_ENET, ENABLE_125M), 1239 CLK_GATE("pll1_sys", "pll1_bypass", CCM_ANALOG, PLL_ARM, ENABLE), 1240 CLK_GATE("pll2_bus", "pll2_bypass", CCM_ANALOG, PLL_SYS, ENABLE), 1241 CLK_GATE("pll3_usb_otg", "pll3_bypass", CCM_ANALOG, PLL_USB1, ENABLE), 1242 CLK_GATE("pll4_audio", "pll4_bypass", CCM_ANALOG, PLL_AUDIO, ENABLE), 1243 CLK_GATE("pll5_video", "pll5_bypass", CCM_ANALOG, PLL_VIDEO, ENABLE), 1244 CLK_GATE("pll6_enet", "pll6_bypass", CCM_ANALOG, PLL_ENET, ENABLE), 1245 CLK_GATE("pll7_usb_host", "pll7_bypass", CCM_ANALOG, PLL_USB2, ENABLE), 1246 1247 CLK_GATE("usbphy1", "pll3_usb_otg", CCM_ANALOG, PLL_USB1, RESERVED), 1248 CLK_GATE("usbphy2", "pll7_usb_host", CCM_ANALOG, PLL_USB2, RESERVED), 1249 CLK_GATE("usbphy1_gate", "dummy", CCM_ANALOG, PLL_USB2, EN_USB_CLK), 1250 CLK_GATE("usbphy2_gate", "dummy", CCM_ANALOG, PLL_USB2, EN_USB_CLK), 1251 1252 CLK_GATE_EXCLUSIVE("lvds2_out", "lvds2_sel", CCM_ANALOG, MISC1, LVDS_CLK2_OBEN, LVDS_CLK2_IBEN), 1253 CLK_GATE_EXCLUSIVE("lvds2_in", "anaclk2", CCM_ANALOG, MISC1, LVDS_CLK2_IBEN, LVDS_CLK2_OBEN), 1254 CLK_GATE_EXCLUSIVE("lvds1_in", "anaclk1", CCM_ANALOG, MISC1, LVDS_CLK1_IBEN, LVDS_CLK1_OBEN), 1255 }; 1256 1257 struct imxccm_init_parent imx6sxccm_init_parents[] = { 1258 { "pll1_bypass", "pll1" }, 1259 { "pll2_bypass", "pll2" }, 1260 { "pll3_bypass", "pll3" }, 1261 { "pll4_bypass", "pll4" }, 1262 { "pll5_bypass", "pll5" }, 1263 { "pll6_bypass", "pll6" }, 1264 { "pll7_bypass", "pll7" }, 1265 { "lvds1_sel", "pcie_ref_125m" }, 1266 { 0 }, 1267 }; 1268 1269 static struct imx6_clk * 1270 imx6sx_clk_find_by_id(struct imx6ccm_softc *sc, u_int clock_id) 1271 { 1272 for (int n = 0; n < __arraycount(imx6sx_clock_ids); n++) { 1273 if (imx6sx_clock_ids[n].id == clock_id) { 1274 const char *name = imx6sx_clock_ids[n].name; 1275 return imx6_clk_find(sc, name); 1276 } 1277 } 1278 1279 return NULL; 1280 } 1281 1282 static struct clk * 1283 imx6sx_get_clock_by_id(struct imx6ccm_softc *sc, u_int clock_id) 1284 { 1285 struct imx6_clk *iclk; 1286 iclk = imx6sx_clk_find_by_id(sc, clock_id); 1287 1288 if (iclk == NULL) 1289 return NULL; 1290 1291 return &iclk->base; 1292 } 1293 1294 static struct clk *imx6sx_clk_decode(device_t, int, const void *, size_t); 1295 1296 static const struct fdtbus_clock_controller_func imx6sx_ccm_fdtclock_funcs = { 1297 .decode = imx6sx_clk_decode 1298 }; 1299 1300 static struct clk * 1301 imx6sx_clk_decode(device_t dev, int cc_phandle, const void *data, size_t len) 1302 { 1303 struct clk *clk; 1304 struct imx6ccm_softc *sc = device_private(dev); 1305 1306 /* #clock-cells should be 1 */ 1307 if (len != 4) 1308 return NULL; 1309 1310 const u_int clock_id = be32dec(data); 1311 1312 clk = imx6sx_get_clock_by_id(sc, clock_id); 1313 if (clk) 1314 return clk; 1315 1316 return NULL; 1317 } 1318 1319 static void 1320 imx6sx_clk_fixed_from_fdt(struct imx6ccm_softc *sc, const char *name) 1321 { 1322 struct imx6_clk *iclk = (struct imx6_clk *)imx6_get_clock(sc, name); 1323 1324 KASSERTMSG((iclk != NULL), "failed to find clock %s", name); 1325 1326 char *path = kmem_asprintf("/clock-%s", name); 1327 /* in device tree path, '_' are remplaced by '-' */ 1328 for (char *p = path; *p != '\0'; p++) { 1329 if (*p == '_') 1330 *p = '-'; 1331 } 1332 int phandle = OF_finddevice(path); 1333 KASSERTMSG((phandle >= 0), "failed to find device %s", path); 1334 kmem_free(path, strlen(path) + 1); 1335 1336 if (of_getprop_uint32(phandle, "clock-frequency", &iclk->clk.fixed.rate) != 0) 1337 iclk->clk.fixed.rate = 0; 1338 } 1339 1340 static int imx6sxccm_match(device_t, cfdata_t, void *); 1341 static void imx6sxccm_attach(device_t, device_t, void *); 1342 1343 CFATTACH_DECL_NEW(imx6sxccm, sizeof(struct imx6ccm_softc), 1344 imx6sxccm_match, imx6sxccm_attach, NULL, NULL); 1345 1346 static const struct device_compatible_entry compat_data[] = { 1347 { .compat = "fsl,imx6sx-ccm" }, 1348 DEVICE_COMPAT_EOL 1349 }; 1350 1351 static int 1352 imx6sxccm_match(device_t parent, cfdata_t cfdata, void *aux) 1353 { 1354 struct fdt_attach_args * const faa = aux; 1355 1356 return of_compatible_match(faa->faa_phandle, compat_data); 1357 } 1358 1359 static void 1360 imx6sxccm_attach(device_t parent, device_t self, void *aux) 1361 { 1362 struct imx6ccm_softc * const sc = device_private(self); 1363 struct fdt_attach_args * const faa = aux; 1364 bus_addr_t addr; 1365 bus_size_t size; 1366 1367 if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) { 1368 aprint_error(": couldn't get registers\n"); 1369 return; 1370 } 1371 1372 sc->sc_dev = self; 1373 sc->sc_iot = faa->faa_bst; 1374 1375 if (bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh)) { 1376 aprint_error(": can't map ccm registers\n"); 1377 return; 1378 } 1379 1380 int phandle = of_find_bycompat(OF_finddevice("/"), "fsl,imx6sx-anatop"); 1381 1382 if (phandle == -1) { 1383 aprint_error(": can't find anatop device\n"); 1384 return; 1385 } 1386 1387 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 1388 aprint_error(": can't get anatop registers\n"); 1389 return; 1390 } 1391 1392 1393 if (bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh_analog)) { 1394 aprint_error(": can't map anatop registers\n"); 1395 return; 1396 } 1397 1398 aprint_naive("\n"); 1399 aprint_normal(": Clock Control Module\n"); 1400 1401 imx6ccm_attach_common(self, &imx6sx_clks[0], __arraycount(imx6sx_clks), 1402 imx6sxccm_init_parents); 1403 1404 imx6sx_clk_fixed_from_fdt(sc, "ckil"); 1405 imx6sx_clk_fixed_from_fdt(sc, "osc"); 1406 imx6sx_clk_fixed_from_fdt(sc, "ipp_di0"); 1407 imx6sx_clk_fixed_from_fdt(sc, "ipp_di1"); 1408 imx6sx_clk_fixed_from_fdt(sc, "anaclk1"); 1409 imx6sx_clk_fixed_from_fdt(sc, "anaclk2"); 1410 1411 fdtbus_register_clock_controller(self, faa->faa_phandle, 1412 &imx6sx_ccm_fdtclock_funcs); 1413 } 1414