1 /* $NetBSD: shpcic_machdep.c,v 1.9 2022/10/31 15:56:40 martin Exp $ */
2
3 /*
4 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
5 * Copyright (c) 1994 Charles M. Hannum. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Charles M. Hannum.
18 * 4. The name of the author may not be used to endorse or promote products
19 * derived from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 /*
34 * Machine-specific functions for PCI autoconfiguration.
35 */
36
37 #include <sys/cdefs.h>
38 __KERNEL_RCSID(0, "$NetBSD: shpcic_machdep.c,v 1.9 2022/10/31 15:56:40 martin Exp $");
39
40 #include <sys/types.h>
41 #include <sys/param.h>
42 #include <sys/time.h>
43 #include <sys/systm.h>
44 #include <sys/errno.h>
45 #include <sys/extent.h>
46 #include <sys/device.h>
47
48 #include <uvm/uvm_extern.h>
49
50 #include <dev/pci/pcivar.h>
51 #include <dev/pci/pcireg.h>
52 #include <dev/pci/pcidevs.h>
53 #include <dev/pci/pciconf.h>
54
55 #include <sys/bus.h>
56 #include <machine/intr.h>
57 #include <machine/pci_machdep.h>
58
59 bus_space_tag_t
shpcic_get_bus_io_tag(void)60 shpcic_get_bus_io_tag(void)
61 {
62 extern struct _bus_space landisk_pci_bus_io;
63
64 return &landisk_pci_bus_io;
65 }
66
67 bus_space_tag_t
shpcic_get_bus_mem_tag(void)68 shpcic_get_bus_mem_tag(void)
69 {
70 extern struct _bus_space landisk_pci_bus_mem;
71
72 return &landisk_pci_bus_mem;
73 }
74
75 bus_dma_tag_t
shpcic_get_bus_dma_tag(void)76 shpcic_get_bus_dma_tag(void)
77 {
78 extern struct _bus_dma_tag landisk_bus_dma;
79
80 return &landisk_bus_dma;
81 }
82
83 void
landisk_pci_attach_hook(device_t parent,device_t self,struct pcibus_attach_args * pba)84 landisk_pci_attach_hook(device_t parent, device_t self,
85 struct pcibus_attach_args *pba)
86 {
87
88 /* Nothing to do */
89 }
90
91 int
landisk_pci_intr_map(const struct pci_attach_args * pa,pci_intr_handle_t * ihp)92 landisk_pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp)
93 {
94 int pin = pa->pa_intrpin;
95 int line = pa->pa_intrline;
96
97 if (pin == 0) {
98 /* No IRQ used. */
99 goto bad;
100 }
101
102 if (pin > 4) {
103 printf("pci_intr_map: bad interrupt pin %d\n", pin);
104 goto bad;
105 }
106
107 if (line == 0 || line == 255) {
108 printf("pci_intr_map: no mapping for pin %c\n", '@' + pin);
109 goto bad;
110 }
111
112 *ihp = line;
113 return 0;
114
115 bad:
116 *ihp = -1;
117 return 1;
118 }
119
120 int
landisk_pci_intr_setattr(pci_chipset_tag_t pc,pci_intr_handle_t * ihp,int attr,uint64_t data)121 landisk_pci_intr_setattr(pci_chipset_tag_t pc,
122 pci_intr_handle_t *ihp, int attr, uint64_t data)
123 {
124
125 switch (attr) {
126 case PCI_INTR_MPSAFE:
127 return 0;
128 default:
129 return ENODEV;
130 }
131 }
132
133 const char *
landisk_pci_intr_string(void * v,pci_intr_handle_t ih,char * buf,size_t len)134 landisk_pci_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len)
135 {
136 if (ih == 0)
137 panic("pci_intr_string: bogus handle 0x%x", ih);
138
139 snprintf(buf, len, "irq %d", ih);
140
141 return buf;
142 }
143
144 const struct evcnt *
landisk_pci_intr_evcnt(void * v,pci_intr_handle_t ih)145 landisk_pci_intr_evcnt(void *v, pci_intr_handle_t ih)
146 {
147
148 /* XXX for now, no evcnt parent reported */
149 return (NULL);
150 }
151
152 void *
landisk_pci_intr_establish(void * v,pci_intr_handle_t ih,int level,int (* ih_fun)(void *),void * ih_arg)153 landisk_pci_intr_establish(void *v, pci_intr_handle_t ih, int level,
154 int (*ih_fun)(void *), void *ih_arg)
155 {
156
157 if (ih == 0)
158 panic("pci_intr_establish: bogus handle 0x%x", ih);
159
160 return extintr_establish(ih, level, ih_fun, ih_arg);
161 }
162
163 void
landisk_pci_intr_disestablish(void * v,void * cookie)164 landisk_pci_intr_disestablish(void *v, void *cookie)
165 {
166
167 extintr_disestablish(cookie);
168 }
169
170 void
landisk_pci_conf_interrupt(void * v,int bus,int dev,int pin,int swiz,int * iline)171 landisk_pci_conf_interrupt(void *v, int bus, int dev, int pin, int swiz,
172 int *iline)
173 {
174 static const int irq[4] = { 5, 6, 7, 8 };
175
176 *iline = -1;
177 if ((dev >= 0 && dev <= 3) && (pin >= 1 && pin <= 4)) {
178 *iline = irq[(dev + pin - 1) & 3];
179 }
180 }
181
182 int
landisk_pci_conf_hook(void * v,int bus,int dev,int func,pcireg_t id)183 landisk_pci_conf_hook(void *v, int bus, int dev, int func, pcireg_t id)
184 {
185
186 return (PCI_CONF_ALL & ~PCI_CONF_MAP_ROM);
187 }
188
189 /*
190 * shpcic bus space
191 */
192 struct _bus_space landisk_pci_bus_io =
193 {
194 .bs_cookie = NULL,
195
196 .bs_map = shpcic_iomem_map,
197 .bs_unmap = shpcic_iomem_unmap,
198 .bs_subregion = shpcic_iomem_subregion,
199
200 .bs_alloc = shpcic_iomem_alloc,
201 .bs_free = shpcic_iomem_free,
202
203 .bs_mmap = shpcic_iomem_mmap,
204
205 .bs_r_1 = shpcic_io_read_1,
206 .bs_r_2 = shpcic_io_read_2,
207 .bs_r_4 = shpcic_io_read_4,
208
209 .bs_rm_1 = shpcic_io_read_multi_1,
210 .bs_rm_2 = shpcic_io_read_multi_2,
211 .bs_rm_4 = shpcic_io_read_multi_4,
212
213 .bs_rr_1 = shpcic_io_read_region_1,
214 .bs_rr_2 = shpcic_io_read_region_2,
215 .bs_rr_4 = shpcic_io_read_region_4,
216
217 .bs_w_1 = shpcic_io_write_1,
218 .bs_w_2 = shpcic_io_write_2,
219 .bs_w_4 = shpcic_io_write_4,
220
221 .bs_wm_1 = shpcic_io_write_multi_1,
222 .bs_wm_2 = shpcic_io_write_multi_2,
223 .bs_wm_4 = shpcic_io_write_multi_4,
224
225 .bs_wr_1 = shpcic_io_write_region_1,
226 .bs_wr_2 = shpcic_io_write_region_2,
227 .bs_wr_4 = shpcic_io_write_region_4,
228
229 .bs_sm_1 = shpcic_io_set_multi_1,
230 .bs_sm_2 = shpcic_io_set_multi_2,
231 .bs_sm_4 = shpcic_io_set_multi_4,
232
233 .bs_sr_1 = shpcic_io_set_region_1,
234 .bs_sr_2 = shpcic_io_set_region_2,
235 .bs_sr_4 = shpcic_io_set_region_4,
236
237 .bs_c_1 = shpcic_io_copy_region_1,
238 .bs_c_2 = shpcic_io_copy_region_2,
239 .bs_c_4 = shpcic_io_copy_region_4,
240 };
241
242 struct _bus_space landisk_pci_bus_mem =
243 {
244 .bs_cookie = NULL,
245
246 .bs_map = shpcic_iomem_map,
247 .bs_unmap = shpcic_iomem_unmap,
248 .bs_subregion = shpcic_iomem_subregion,
249
250 .bs_alloc = shpcic_iomem_alloc,
251 .bs_free = shpcic_iomem_free,
252
253 .bs_mmap = shpcic_iomem_mmap,
254
255 .bs_r_1 = shpcic_mem_read_1,
256 .bs_r_2 = shpcic_mem_read_2,
257 .bs_r_4 = shpcic_mem_read_4,
258
259 .bs_rm_1 = shpcic_mem_read_multi_1,
260 .bs_rm_2 = shpcic_mem_read_multi_2,
261 .bs_rm_4 = shpcic_mem_read_multi_4,
262
263 .bs_rr_1 = shpcic_mem_read_region_1,
264 .bs_rr_2 = shpcic_mem_read_region_2,
265 .bs_rr_4 = shpcic_mem_read_region_4,
266
267 .bs_w_1 = shpcic_mem_write_1,
268 .bs_w_2 = shpcic_mem_write_2,
269 .bs_w_4 = shpcic_mem_write_4,
270
271 .bs_wm_1 = shpcic_mem_write_multi_1,
272 .bs_wm_2 = shpcic_mem_write_multi_2,
273 .bs_wm_4 = shpcic_mem_write_multi_4,
274
275 .bs_wr_1 = shpcic_mem_write_region_1,
276 .bs_wr_2 = shpcic_mem_write_region_2,
277 .bs_wr_4 = shpcic_mem_write_region_4,
278
279 .bs_sm_1 = shpcic_mem_set_multi_1,
280 .bs_sm_2 = shpcic_mem_set_multi_2,
281 .bs_sm_4 = shpcic_mem_set_multi_4,
282
283 .bs_sr_1 = shpcic_mem_set_region_1,
284 .bs_sr_2 = shpcic_mem_set_region_2,
285 .bs_sr_4 = shpcic_mem_set_region_4,
286
287 .bs_c_1 = shpcic_mem_copy_region_1,
288 .bs_c_2 = shpcic_mem_copy_region_2,
289 .bs_c_4 = shpcic_mem_copy_region_4,
290 };
291